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cfg_timer_tim5.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef CFG_TIMER_TIM5_H
20#define CFG_TIMER_TIM5_H
21
22#include "periph_cpu.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32static const timer_conf_t timer_config[] = {
33 {
34 .dev = TIM5,
35 .max = 0xffffffff,
36#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
37 defined(CPU_FAM_STM32U5)
38 .rcc_mask = RCC_APB1ENR1_TIM5EN,
39#else
40 .rcc_mask = RCC_APB1ENR_TIM5EN,
41#endif
42 .bus = APB1,
43 .irqn = TIM5_IRQn
44 }
45};
46
47#define TIMER_0_ISR isr_tim5
48
49#define TIMER_NUMOF ARRAY_SIZE(timer_config)
52#ifdef __cplusplus
53}
54#endif
55
56#endif /* CFG_TIMER_TIM5_H */
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265