cpu.h
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1 /*
2  * Copyright (C) 2014-2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
30 #ifndef CPU_H
31 #define CPU_H
32 
33 #include <stdio.h>
34 
35 #include "irq.h"
36 #include "sched.h"
37 #include "thread.h"
38 #include "cpu_conf.h"
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
51 #define STACK_CANARY_WORD (0xE7FEE7FEu)
52 
59 #define PROVIDES_PM_SET_LOWEST
60 
67 #define CORTEXM_SCB_CPACR_FPU_ACCESS_FULL (0x00f00000)
68 
72 void cpu_init(void);
73 
88 void cortexm_init(void);
89 
99 static inline void cortexm_init_fpu(void)
100 {
101  /* initialize the FPU on Cortex-M4F CPUs */
102 #if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
103  /* give full access to the FPU */
104  SCB->CPACR |= (uint32_t)CORTEXM_SCB_CPACR_FPU_ACCESS_FULL;
105 #endif
106 }
107 
108 #if defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN)
109 
119 void cortexm_init_isr_priorities(void);
120 
130 void cortexm_init_misc(void);
131 
132 #endif /* defined(CPU_CORTEXM_INIT_SUBFUNCTIONS) || defined(DOXYGEN) */
133 
137 static inline void cpu_print_last_instruction(void)
138 {
139  uint32_t *lr_ptr;
140  __asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
141  printf("%p\n", (void*) lr_ptr);
142 }
143 
150 static inline void cortexm_sleep_until_event(void)
151 {
152  __WFE();
153 }
154 
160 static inline void cortexm_sleep(int deep)
161 {
162  if (deep) {
163  SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);
164  }
165  else {
166  SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
167  }
168 
169  /* ensure that all memory accesses have completed and trigger sleeping */
170  unsigned state = irq_disable();
171  __DSB();
172  __WFI();
173 #if defined(CPU_MODEL_STM32L152RE)
174  /* STM32L152RE crashes if branching to irq_restore(state). See #11830. */
175  __set_PRIMASK(state);
176 #else
177  irq_restore(state);
178 #endif
179 }
180 
186 static inline void cortexm_isr_end(void)
187 {
190  }
191 }
192 
200 static inline void cpu_jump_to_image(uint32_t image_address)
201 {
202  /* On Cortex-M platforms, the flash begins with:
203  *
204  * 1. 4 byte pointer to stack to be used at startup
205  * 2. 4 byte pointer to the reset vector function
206  *
207  * On powerup, the CPU sets the stack pointer and starts executing the
208  * reset vector.
209  *
210  * We're doing the same here, but we'd like to start at image_address.
211  *
212  * This function must be called while executing from MSP (Master Stack
213  * Pointer).
214  */
215 
216  /* set MSP */
217  __set_MSP(*(uint32_t*)image_address);
218 
219  /* skip stack pointer */
220  image_address += 4;
221 
222  /* load the images reset_vector address */
223  uint32_t destination_address = *(uint32_t*)image_address;
224 
225  /* Make sure the Thumb State bit is set. */
226  destination_address |= 0x1;
227 
228  /* Branch execution */
229  __asm("BX %0" :: "r" (destination_address));
230 }
231 
232 /* The following register is only present for
233  Cortex-M0+, -M3, -M4, -M7 and -M23 CPUs */
234 #if defined(CPU_ARCH_CORTEX_M0PLUS) || defined(CPU_ARCH_CORTEX_M3) || \
235  defined(CPU_ARCH_CORTEX_M4) || defined(CPU_ARCH_CORTEX_M4F) || \
236  defined(CPU_ARCH_CORTEX_M7) || defined(CPU_ARCH_CORTEX_M23)
237 static inline uint32_t cpu_get_image_baseaddr(void)
238 {
239  return SCB->VTOR;
240 }
241 #endif
242 
252 bool cpu_check_address(volatile const char *address);
253 
254 #ifdef __cplusplus
255 }
256 #endif
257 
258 #endif /* CPU_H */
259 
static void cortexm_init_fpu(void)
Initialize Cortex-M FPU.
Definition: cpu.h:99
void cortexm_init_misc(void)
Initialize Cortex-M misc functions.
int printf(const char *format,...)
System standard printf function.
void cpu_init(void)
Initialization of the CPU.
void irq_restore(unsigned state)
This function restores the IRQ disable bit in the status register to the value contained within passe...
void cortexm_init_isr_priorities(void)
Initialize Cortex-M interrupt priorities.
Threading API.
volatile unsigned int sched_context_switch_request
Flag indicating whether a context switch is necessary after handling an interrupt.
static void cortexm_sleep_until_event(void)
Put the CPU into the &#39;wait for event&#39; sleep mode.
Definition: cpu.h:150
Scheduler API definition.
static void cpu_print_last_instruction(void)
Prints the current content of the link register (lr)
Definition: cpu.h:137
static void cortexm_isr_end(void)
Trigger a conditional context scheduler run / context switch.
Definition: cpu.h:186
bool cpu_check_address(volatile const char *address)
Checks is memory address valid or not.
#define CORTEXM_SCB_CPACR_FPU_ACCESS_FULL
Pattern to write into the co-processor Access Control Register to allow full FPU access.
Definition: cpu.h:67
static void cortexm_sleep(int deep)
Put the CPU into (deep) sleep mode, using the WFI instruction.
Definition: cpu.h:160
void cortexm_init(void)
Initialize Cortex-M specific core parts of the CPU.
void thread_yield_higher(void)
Lets current thread yield in favor of a higher prioritized thread.
unsigned irq_disable(void)
This function sets the IRQ disable bit in the status register.
IRQ driver interface.
static void cpu_jump_to_image(uint32_t image_address)
Jumps to another image in flash.
Definition: cpu.h:200