Register definitions for the ENC28J60 Ethernet device. More...

Detailed Description

Register definitions for the ENC28J60 Ethernet device.

Author: Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

SPI instruction set
#define	CMD_RCR 0x00 /* read control register */

#define	CMD_RBM 0x3a /* read buffer memory */

#define	CMD_WCR 0x40 /* write control register */

#define	CMD_WBM 0x7a /* write buffer memory */

#define	CMD_BFS 0x80 /* bit field set */

#define	CMD_BFC 0xa0 /* bit field clear */

#define	CMD_SRC 0xff /* system reset command (soft reset) */

Available address pointers
#define	ADDR_READ_PTR 0x00
	Read pointer.

#define	ADDR_WRITE_PTR 0x02
	Write data pointer.

#define	ADDR_TX_START 0x04
	TX buffer start.

#define	ADDR_TX_END 0x06
	TX buffer end.

#define	ADDR_RX_START 0x08
	RX buffer start.

#define	ADDR_RX_END 0x0a
	RX buffer end.

#define	ADDR_RX_READ 0x0c
	start of oldest packet in RX buffer

#define	ADDR_RX_WRITE 0x0e
	start of free space in RX buffer

Shared registers (accessible on each bank)
#define	REG_EIE 0x1b
	interrupt enable

#define	REG_EIR 0x1c
	interrupt flags

#define	REG_ESTAT 0x1d
	status

#define	REG_ECON2 0x1e
	configuration 1

#define	REG_ECON1 0x1f
	configuration 2

Register in bank 0 - Ethernet registers
#define	REG_B0_ERDPTL 0x00 /* read data pointer - low byte */

#define	REG_B0_ERDPTH 0x01 /* read data pointer - high byte */

#define	REG_B0_EWRPTL 0x02 /* write data pointer - low byte */

#define	REG_B0_EWRPTH 0x03 /* write data pointer - high byte */

#define	REG_B0_ETXSTL 0x04 /* TX start pointer - low byte */

#define	REG_B0_ETXSTH 0x05 /* TX start pointer - high byte */

#define	REG_B0_ETXNDL 0x06 /* TX end pointer - low byte */

#define	REG_B0_ETXNDH 0x07 /* TX end pointer - high byte */

#define	REG_B0_ERXSTL 0x08 /* RX start pointer - low byte */

#define	REG_B0_ERXSTH 0x09 /* RX start pointer - high byte */

#define	REG_B0_ERXNDL 0x0a /* RX end pointer - low byte */

#define	REG_B0_ERXNDH 0x0b /* RX end pointer - high byte */

#define	REG_B0_ERXRDPTL 0x0c /* RX read pointer - low byte */

#define	REG_B0_ERXRDPTH 0x0d /* RX read pointer - high byte */

#define	REG_B0_ERXWRPTL 0x0e /* RX write pointer - low byte */

#define	REG_B0_ERXWRPTH 0x0f /* RX write pointer - high byte */

#define	REG_B0_EDMASTL 0x10 /* DMA start pointer - low byte */

#define	REG_B0_EDMASTH 0x11 /* DMA start pointer - high byte */

#define	REG_B0_EDMANDL 0x12 /* DMA end pointer - low byte */

#define	REG_B0_EDMANDH 0x13 /* DMA end pointer - high byte */

#define	REG_B0_EDMADSTL 0x14 /* DMA destination pointer - low byte */

#define	REG_B0_EDMADSTH 0x15 /* DMA destination pointer - high byte */

#define	REG_B0_EDMACSL 0x16 /* DMA checksum - low byte */

#define	REG_B0_EDMACSH 0x17 /* DMA checksum - high byte */

Registers in bank 1 - Ethernet registers
#define	REG_B1_EHT0 0x00 /* hash table - byte 0 */

#define	REG_B1_EHT1 0x01 /* hash table - byte 1 */

#define	REG_B1_EHT2 0x02 /* hash table - byte 2 */

#define	REG_B1_EHT3 0x03 /* hash table - byte 3 */

#define	REG_B1_EHT4 0x04 /* hash table - byte 4 */

#define	REG_B1_EHT5 0x05 /* hash table - byte 5 */

#define	REG_B1_EHT6 0x06 /* hash table - byte 6 */

#define	REG_B1_EHT7 0x07 /* hash table - byte 7 */

#define	REG_B1_EPMM0 0x08 /* pattern match mask - byte 0 */

#define	REG_B1_EPMM1 0x09 /* pattern match mask - byte 1 */

#define	REG_B1_EPMM2 0x0a /* pattern match mask - byte 2 */

#define	REG_B1_EPMM3 0x0b /* pattern match mask - byte 3 */

#define	REG_B1_EPMM4 0x0c /* pattern match mask - byte 4 */

#define	REG_B1_EPMM5 0x0d /* pattern match mask - byte 5 */

#define	REG_B1_EPMM6 0x0e /* pattern match mask - byte 6 */

#define	REG_B1_EPMM7 0x0f /* pattern match mask - byte 7 */

#define	REG_B1_EPMCSL 0x10 /* pattern match checksum - low byte */

#define	REG_B1_EPMCSH 0x11 /* pattern match checksum - high byte */

#define	REG_B1_EPMOL 0x14 /* pattern match offset - low byte */

#define	REG_B1_EPMOH 0x15 /* pattern match offset - high byte */

#define	REG_B1_ERXFCON 0x18 /* receive filter control register */

#define	REG_B1_EPKTCNT 0x19 /* packet count */

Registers in bank 2 - MAC registers
#define	REG_B2_MACON1 0x00 /* MAC control register 1 */

#define	REG_B2_MACON3 0x02 /* MAC control register 3 */

#define	REG_B2_MACON4 0x03 /* MAC control register 4 */

#define	REG_B2_MABBIPG 0x04 /* back-to-back inter-packet gap */

#define	REG_B2_MAIPGL 0x06 /* non-back-to-back inter-packet gap - low byte */

#define	REG_B2_MAIPGH 0x07 /* non-back-to-back inter-packet gap - high byte */

#define	REG_B2_MACLCON1 0x08 /* retransmission maximum */

#define	REG_B2_MACLCON2 0x09 /* collision window */

#define	REG_B2_MAMXFLL 0x0a /* maximum frame length - low byte */

#define	REG_B2_MAMXFLH 0x0b /* maximum frame length - high byte */

#define	REG_B2_MICMD 0x12 /* MIIM command */

#define	REG_B2_MIREGADR 0x14 /* MIIM register address */

#define	REG_B2_MIWRL 0x16 /* MIIM write data register - low byte */

#define	REG_B2_MIWRH 0x17 /* MIIM write data register - high byte */

#define	REG_B2_MIRDL 0x18 /* MIIM read data register - low byte */

#define	REG_B2_MIRDH 0x19 /* MIIM read data register - high byte */

Registers in bank 3 - MIXED registers
#define	REG_B3_MAADR5 0x00 /* MAC address - byte 5 */

#define	REG_B3_MAADR6 0x01 /* MAC address - byte 6 */

#define	REG_B3_MAADR3 0x02 /* MAC address - byte 3 */

#define	REG_B3_MAADR4 0x03 /* MAC address - byte 4 */

#define	REG_B3_MAADR1 0x04 /* MAC address - byte 1 */

#define	REG_B3_MAADR2 0x05 /* MAC address - byte 2 */

#define	REG_B3_EBSTSD 0x06 /* built-in self-test fill seed */

#define	REG_B3_EBSTCON 0x07 /* built-in self-test control register */

#define	REG_B3_EBSTCSL 0x08 /* built-in self-test checksum - low byte */

#define	REG_B3_EBSTCSH 0x09 /* built-in self-test checksum - high byte */

#define	REG_B3_MISTAT 0x0a /* MIIM status register */

#define	REG_B3_EREVID 0x12 /* Ethernet revision ID */

#define	REG_B3_ECOCON 0x15 /* clock output control */

#define	REG_B3_EFLOCON 0x17 /* Ethernet flow control */

#define	REG_B3_EPAUSL 0x18 /* pause timer value - low byte */

#define	REG_B3_EPAUSH 0x19 /* pause timer value - high byte */

PHY Registers
#define	REG_PHY_PHCON1 0x00

#define	REG_PHY_PHSTAT1 0x01

#define	REG_PHY_PHID1 0x02

#define	REG_PHY_PHID2 0x03

#define	REG_PHY_PHCON2 0x10

#define	REG_PHY_PHSTAT2 0x11

#define	REG_PHY_PHIE 0x12

#define	REG_PHY_PHIR 0x13

#define	REG_PHY_PHLCON 0x14

EIE bitfields
#define	EIE_INTIE 0x80

#define	EIE_PKTIE 0x40

#define	EIE_DMAIE 0x20

#define	EIE_LINKIE 0x10

#define	EIE_TXIE 0x08

#define	EIE_TXERIE 0x02

#define	EIE_RXERIE 0x01

EIR bitfields
#define	EIR_PKTIF 0x40

#define	EIR_DMAIF 0x20

#define	EIR_LINKIF 0x10

#define	EIR_TXIF 0x08

#define	EIR_TXERIF 0x02

#define	EIR_RXERIF 0x01

ESTAT bitfields
#define	ESTAT_INT 0x80

#define	ESTAT_BUFFER 0x40

#define	ESTAT_LATECOL 0x10

#define	ESTAT_RXBUSY 0x40

#define	ESTAT_TXABRT 0x20

#define	ESTAT_CLKRDY 0x01

ECON1 bitfields
#define	ECON1_TXRST 0x80

#define	ECON1_RXRST 0x40

#define	ECON1_DMAST 0x20

#define	ECON1_CSUMEN 0x10

#define	ECON1_TXRTS 0x08

#define	ECON1_RXEN 0x04

#define	ECON1_BSEL1 0x02

#define	ECON1_BSEL0 0x01

#define	ECON1_BSEL_MASK 0x03

ECON2 bitfields
#define	ECON2_AUTOINC 0x80

#define	ECON2_PKTDEC 0x40

#define	ECON2_PWRSV 0x20

#define	ECON2_VRPS 0x40

ERXFCON bitfields
#define	ERXFCON_UCEN 0x80

#define	ERXFCON_ANDOR 0x40

#define	ERXFCON_CRCEN 0x20

#define	ERXFCON_PMEN 0x10

#define	ERXFCON_MPEN 0x08

#define	ERXFCON_HTEN 0x04

#define	ERXFCON_MCEN 0x02

#define	ERXFCON_BCEN 0x01

MACON1 bitfields
#define	MACON1_TXPAUS 0x08

#define	MACON1_RXPAUS 0x04

#define	MACON1_PASSALL 0x02

#define	MACON1_MARXEN 0x01

MACON3 bitfields
#define	MACON3_PADCFG2 0x80

#define	MACON3_PADCFG1 0x40

#define	MACON3_PADCFG0 0x20

#define	MACON3_TXCRCEN 0x10

#define	MACON3_PHDREN 0x08

#define	MACON3_HFRMEN 0x04

#define	MACON3_FRMLNEN 0x02

#define	MACON3_FULDPX 0x01

MACON4 bitfields
#define	MACON4_DEFER 0x40

#define	MACON4_BPEN 0x20

#define	MACON4_NOBKOFF 0x10

MABBIPG bitfields
#define	MABBIPG_FD 0x15

#define	MABBIPG_HD 0x12

MAIPGL bitfields
#define	MAIPGL_FD 0x12

MICMD bitfields
#define	MICMD_MIISCAN 0x02

#define	MICMD_MIIRD 0x01

MISTAT bitfields
#define	MISTAT_NVALID 0x04

#define	MISTAT_SCAN 0x02

#define	MISTAT_BUSY 0x01

EFLOCON bitfields
#define	EFLOCON_FULDPXS 0x04

#define	EFLOCON_FCEN1 0x02

#define	EFLOCON_FCEN0 0x01

#define	EFLOCON_FCEN_MASK 0x03

PHCON1 bitfields
#define	PHCON1_PRST 0x8000

#define	PHCON1_PLOOPBK 0x4000

#define	PHCON1_PPWRSV 0x0800

#define	PHCON1_PDPXMD 0x0100

PHSTAT1 bitfields
#define	PHSTAT1_PFDPX 0x1000

#define	PHSTAT1_PHDPX 0x0800

#define	PHSTAT1_LLSTAT 0x0004

#define	PHSTAT1_JBSTAT 0x0002

PHCON2 bitfields
#define	PHCON2_FRCLNK 0x4000

#define	PHCON2_TXDIS 0x2000

#define	PHCON2_JABBER 0x0400

#define	PHCON2_HDLDIS 0x0100

PHSTAT2 bitfields
#define	PHSTAT2_TXSTAT 0x2000

#define	PHSTAT2_RXSTAT 0x1000

#define	PHSTAT2_COLSTAT 0x0800

#define	PHSTAT2_LSTAT 0x0400

#define	PHSTAT2_DPXSTAT 0x0200

#define	PHSTAT2_PLRITY 0x0020

PHIE bitfields
#define	PHIE_PLNKIE 0x0010

#define	PHIE_PGEIE 0x0002

PHIR bitfields
#define	PHIR_PLNKIF 0x0010

#define	PHIR_PGIF 0x0004

PHLCON bitfields
#define	PHLCON_LACFG(x) ((x & 0xf) << 8)

#define	PHLCON_LBCFG(x) ((x & 0xf) << 4)

#define	PHLCON_LFRQ(x) ((x & 0x3) << 2)

#define	PHLCON_STRCH 0x0002

Frame status bitfields
#define	FRAME_4_RECV_OK 0x80

#define	FRAME_4_LENGTH_OOR 0x40

#define	FRAME_4_LENGTH_ERR 0x20

#define	FRAME_4_CRC_ERR 0x10

#define	FRAME_4_CARRIER_EVT 0x04

#define	FRAME_4_LONG_EVT 0x01

#define	FRAME_5_VLAN 0x40

#define	FRAME_5_UKWN_OPCODE 0x20

#define	FRAME_5_PAUSE 0x10

#define	FRAME_5_RCV_CTRL 0x08

#define	FRAME_5_DRIPPLE 0x04

#define	FRAME_5_BCAST 0x02

#define	FRAME_5_MCAST 0x01

TX control byte bitfields
#define	TX_PHUGEEN 0x08

#define	TX_PPADEN 0x04

#define	TX_PCRCEN 0x02

#define	TX_POVERRIDE 0x01

Macro Definition Documentation

◆ ADDR_READ_PTR

#define ADDR_READ_PTR 0x00

Read pointer.

Definition at line 43 of file enc28j60_regs.h.

◆ ADDR_RX_END

#define ADDR_RX_END 0x0a

RX buffer end.

Definition at line 48 of file enc28j60_regs.h.

◆ ADDR_RX_READ

#define ADDR_RX_READ 0x0c

start of oldest packet in RX buffer

Definition at line 49 of file enc28j60_regs.h.

◆ ADDR_RX_START

#define ADDR_RX_START 0x08

RX buffer start.

Definition at line 47 of file enc28j60_regs.h.

◆ ADDR_RX_WRITE

#define ADDR_RX_WRITE 0x0e

start of free space in RX buffer

Definition at line 50 of file enc28j60_regs.h.

◆ ADDR_TX_END

#define ADDR_TX_END 0x06

TX buffer end.

Definition at line 46 of file enc28j60_regs.h.

◆ ADDR_TX_START

#define ADDR_TX_START 0x04

TX buffer start.

Definition at line 45 of file enc28j60_regs.h.

◆ ADDR_WRITE_PTR

#define ADDR_WRITE_PTR 0x02

Write data pointer.

Definition at line 44 of file enc28j60_regs.h.

◆ CMD_BFC

#define CMD_BFC 0xa0 /* bit field clear */

Definition at line 35 of file enc28j60_regs.h.

◆ CMD_BFS

#define CMD_BFS 0x80 /* bit field set */

Definition at line 34 of file enc28j60_regs.h.

◆ CMD_RBM

#define CMD_RBM 0x3a /* read buffer memory */

Definition at line 31 of file enc28j60_regs.h.

◆ CMD_RCR

#define CMD_RCR 0x00 /* read control register */

Definition at line 30 of file enc28j60_regs.h.

◆ CMD_SRC

#define CMD_SRC 0xff /* system reset command (soft reset) */

Definition at line 36 of file enc28j60_regs.h.

◆ CMD_WBM

#define CMD_WBM 0x7a /* write buffer memory */

Definition at line 33 of file enc28j60_regs.h.

◆ CMD_WCR

#define CMD_WCR 0x40 /* write control register */

Definition at line 32 of file enc28j60_regs.h.

◆ ECON1_BSEL0

#define ECON1_BSEL0 0x01

Definition at line 229 of file enc28j60_regs.h.

◆ ECON1_BSEL1

#define ECON1_BSEL1 0x02

Definition at line 228 of file enc28j60_regs.h.

◆ ECON1_BSEL_MASK

#define ECON1_BSEL_MASK 0x03

Definition at line 230 of file enc28j60_regs.h.

◆ ECON1_CSUMEN

#define ECON1_CSUMEN 0x10

Definition at line 225 of file enc28j60_regs.h.

◆ ECON1_DMAST

#define ECON1_DMAST 0x20

Definition at line 224 of file enc28j60_regs.h.

◆ ECON1_RXEN

#define ECON1_RXEN 0x04

Definition at line 227 of file enc28j60_regs.h.

◆ ECON1_RXRST

#define ECON1_RXRST 0x40

Definition at line 223 of file enc28j60_regs.h.

◆ ECON1_TXRST

#define ECON1_TXRST 0x80

Definition at line 222 of file enc28j60_regs.h.

◆ ECON1_TXRTS

#define ECON1_TXRTS 0x08

Definition at line 226 of file enc28j60_regs.h.

◆ ECON2_AUTOINC

#define ECON2_AUTOINC 0x80

Definition at line 237 of file enc28j60_regs.h.

◆ ECON2_PKTDEC

#define ECON2_PKTDEC 0x40

Definition at line 238 of file enc28j60_regs.h.

◆ ECON2_PWRSV

#define ECON2_PWRSV 0x20

Definition at line 239 of file enc28j60_regs.h.

◆ ECON2_VRPS

#define ECON2_VRPS 0x40

Definition at line 240 of file enc28j60_regs.h.

◆ EFLOCON_FCEN0

#define EFLOCON_FCEN0 0x01

Definition at line 328 of file enc28j60_regs.h.

◆ EFLOCON_FCEN1

#define EFLOCON_FCEN1 0x02

Definition at line 327 of file enc28j60_regs.h.

◆ EFLOCON_FCEN_MASK

#define EFLOCON_FCEN_MASK 0x03

Definition at line 329 of file enc28j60_regs.h.

◆ EFLOCON_FULDPXS

#define EFLOCON_FULDPXS 0x04

Definition at line 326 of file enc28j60_regs.h.

◆ EIE_DMAIE

#define EIE_DMAIE 0x20

Definition at line 187 of file enc28j60_regs.h.

◆ EIE_INTIE

#define EIE_INTIE 0x80

Definition at line 185 of file enc28j60_regs.h.

◆ EIE_LINKIE

#define EIE_LINKIE 0x10

Definition at line 188 of file enc28j60_regs.h.

◆ EIE_PKTIE

#define EIE_PKTIE 0x40

Definition at line 186 of file enc28j60_regs.h.

◆ EIE_RXERIE

#define EIE_RXERIE 0x01

Definition at line 191 of file enc28j60_regs.h.

◆ EIE_TXERIE

#define EIE_TXERIE 0x02

Definition at line 190 of file enc28j60_regs.h.

◆ EIE_TXIE

#define EIE_TXIE 0x08

Definition at line 189 of file enc28j60_regs.h.

◆ EIR_DMAIF

#define EIR_DMAIF 0x20

Definition at line 199 of file enc28j60_regs.h.

◆ EIR_LINKIF

#define EIR_LINKIF 0x10

Definition at line 200 of file enc28j60_regs.h.

◆ EIR_PKTIF

#define EIR_PKTIF 0x40

Definition at line 198 of file enc28j60_regs.h.

◆ EIR_RXERIF

#define EIR_RXERIF 0x01

Definition at line 203 of file enc28j60_regs.h.

◆ EIR_TXERIF

#define EIR_TXERIF 0x02

Definition at line 202 of file enc28j60_regs.h.

◆ EIR_TXIF

#define EIR_TXIF 0x08

Definition at line 201 of file enc28j60_regs.h.

◆ ERXFCON_ANDOR

#define ERXFCON_ANDOR 0x40

Definition at line 248 of file enc28j60_regs.h.

◆ ERXFCON_BCEN

#define ERXFCON_BCEN 0x01

Definition at line 254 of file enc28j60_regs.h.

◆ ERXFCON_CRCEN

#define ERXFCON_CRCEN 0x20

Definition at line 249 of file enc28j60_regs.h.

◆ ERXFCON_HTEN

#define ERXFCON_HTEN 0x04

Definition at line 252 of file enc28j60_regs.h.

◆ ERXFCON_MCEN

#define ERXFCON_MCEN 0x02

Definition at line 253 of file enc28j60_regs.h.

◆ ERXFCON_MPEN

#define ERXFCON_MPEN 0x08

Definition at line 251 of file enc28j60_regs.h.

◆ ERXFCON_PMEN

#define ERXFCON_PMEN 0x10

Definition at line 250 of file enc28j60_regs.h.

◆ ERXFCON_UCEN

#define ERXFCON_UCEN 0x80

Definition at line 247 of file enc28j60_regs.h.

◆ ESTAT_BUFFER

#define ESTAT_BUFFER 0x40

Definition at line 211 of file enc28j60_regs.h.

◆ ESTAT_CLKRDY

#define ESTAT_CLKRDY 0x01

Definition at line 215 of file enc28j60_regs.h.

◆ ESTAT_INT

#define ESTAT_INT 0x80

Definition at line 210 of file enc28j60_regs.h.

◆ ESTAT_LATECOL

#define ESTAT_LATECOL 0x10

Definition at line 212 of file enc28j60_regs.h.

◆ ESTAT_RXBUSY

#define ESTAT_RXBUSY 0x40

Definition at line 213 of file enc28j60_regs.h.

◆ ESTAT_TXABRT

#define ESTAT_TXABRT 0x20

Definition at line 214 of file enc28j60_regs.h.

◆ FRAME_4_CARRIER_EVT

#define FRAME_4_CARRIER_EVT 0x04

Definition at line 408 of file enc28j60_regs.h.

◆ FRAME_4_CRC_ERR

#define FRAME_4_CRC_ERR 0x10

Definition at line 407 of file enc28j60_regs.h.

◆ FRAME_4_LENGTH_ERR

#define FRAME_4_LENGTH_ERR 0x20

Definition at line 406 of file enc28j60_regs.h.

◆ FRAME_4_LENGTH_OOR

#define FRAME_4_LENGTH_OOR 0x40

Definition at line 405 of file enc28j60_regs.h.

◆ FRAME_4_LONG_EVT

#define FRAME_4_LONG_EVT 0x01

Definition at line 409 of file enc28j60_regs.h.

◆ FRAME_4_RECV_OK

#define FRAME_4_RECV_OK 0x80

Definition at line 404 of file enc28j60_regs.h.

◆ FRAME_5_BCAST

#define FRAME_5_BCAST 0x02

Definition at line 416 of file enc28j60_regs.h.

◆ FRAME_5_DRIPPLE

#define FRAME_5_DRIPPLE 0x04

Definition at line 415 of file enc28j60_regs.h.

◆ FRAME_5_MCAST

#define FRAME_5_MCAST 0x01

Definition at line 417 of file enc28j60_regs.h.

◆ FRAME_5_PAUSE

#define FRAME_5_PAUSE 0x10

Definition at line 413 of file enc28j60_regs.h.

◆ FRAME_5_RCV_CTRL

#define FRAME_5_RCV_CTRL 0x08

Definition at line 414 of file enc28j60_regs.h.

◆ FRAME_5_UKWN_OPCODE

#define FRAME_5_UKWN_OPCODE 0x20

Definition at line 412 of file enc28j60_regs.h.

◆ FRAME_5_VLAN

#define FRAME_5_VLAN 0x40

Definition at line 411 of file enc28j60_regs.h.

◆ MABBIPG_FD

#define MABBIPG_FD 0x15

Definition at line 294 of file enc28j60_regs.h.

◆ MABBIPG_HD

#define MABBIPG_HD 0x12

Definition at line 295 of file enc28j60_regs.h.

◆ MACON1_MARXEN

#define MACON1_MARXEN 0x01

Definition at line 264 of file enc28j60_regs.h.

◆ MACON1_PASSALL

#define MACON1_PASSALL 0x02

Definition at line 263 of file enc28j60_regs.h.

◆ MACON1_RXPAUS

#define MACON1_RXPAUS 0x04

Definition at line 262 of file enc28j60_regs.h.

◆ MACON1_TXPAUS

#define MACON1_TXPAUS 0x08

Definition at line 261 of file enc28j60_regs.h.

◆ MACON3_FRMLNEN

#define MACON3_FRMLNEN 0x02

Definition at line 277 of file enc28j60_regs.h.

◆ MACON3_FULDPX

#define MACON3_FULDPX 0x01

Definition at line 278 of file enc28j60_regs.h.

◆ MACON3_HFRMEN

#define MACON3_HFRMEN 0x04

Definition at line 276 of file enc28j60_regs.h.

◆ MACON3_PADCFG0

#define MACON3_PADCFG0 0x20

Definition at line 273 of file enc28j60_regs.h.

◆ MACON3_PADCFG1

#define MACON3_PADCFG1 0x40

Definition at line 272 of file enc28j60_regs.h.

◆ MACON3_PADCFG2

#define MACON3_PADCFG2 0x80

Definition at line 271 of file enc28j60_regs.h.

◆ MACON3_PHDREN

#define MACON3_PHDREN 0x08

Definition at line 275 of file enc28j60_regs.h.

◆ MACON3_TXCRCEN

#define MACON3_TXCRCEN 0x10

Definition at line 274 of file enc28j60_regs.h.

◆ MACON4_BPEN

#define MACON4_BPEN 0x20

Definition at line 286 of file enc28j60_regs.h.

◆ MACON4_DEFER

#define MACON4_DEFER 0x40

Definition at line 285 of file enc28j60_regs.h.

◆ MACON4_NOBKOFF

#define MACON4_NOBKOFF 0x10

Definition at line 287 of file enc28j60_regs.h.

◆ MAIPGL_FD

#define MAIPGL_FD 0x12

Definition at line 302 of file enc28j60_regs.h.

◆ MICMD_MIIRD

#define MICMD_MIIRD 0x01

Definition at line 310 of file enc28j60_regs.h.

◆ MICMD_MIISCAN

#define MICMD_MIISCAN 0x02

Definition at line 309 of file enc28j60_regs.h.

◆ MISTAT_BUSY

#define MISTAT_BUSY 0x01

Definition at line 319 of file enc28j60_regs.h.

◆ MISTAT_NVALID

#define MISTAT_NVALID 0x04

Definition at line 317 of file enc28j60_regs.h.

◆ MISTAT_SCAN

#define MISTAT_SCAN 0x02

Definition at line 318 of file enc28j60_regs.h.

◆ PHCON1_PDPXMD

#define PHCON1_PDPXMD 0x0100

Definition at line 339 of file enc28j60_regs.h.

◆ PHCON1_PLOOPBK

#define PHCON1_PLOOPBK 0x4000

Definition at line 337 of file enc28j60_regs.h.

◆ PHCON1_PPWRSV

#define PHCON1_PPWRSV 0x0800

Definition at line 338 of file enc28j60_regs.h.

◆ PHCON1_PRST

#define PHCON1_PRST 0x8000

Definition at line 336 of file enc28j60_regs.h.

◆ PHCON2_FRCLNK

#define PHCON2_FRCLNK 0x4000

Definition at line 356 of file enc28j60_regs.h.

◆ PHCON2_HDLDIS

#define PHCON2_HDLDIS 0x0100

Definition at line 359 of file enc28j60_regs.h.

◆ PHCON2_JABBER

#define PHCON2_JABBER 0x0400

Definition at line 358 of file enc28j60_regs.h.

◆ PHCON2_TXDIS

#define PHCON2_TXDIS 0x2000

Definition at line 357 of file enc28j60_regs.h.

◆ PHIE_PGEIE

#define PHIE_PGEIE 0x0002

Definition at line 379 of file enc28j60_regs.h.

◆ PHIE_PLNKIE

#define PHIE_PLNKIE 0x0010

Definition at line 378 of file enc28j60_regs.h.

◆ PHIR_PGIF

#define PHIR_PGIF 0x0004

Definition at line 387 of file enc28j60_regs.h.

◆ PHIR_PLNKIF

#define PHIR_PLNKIF 0x0010

Definition at line 386 of file enc28j60_regs.h.

◆ PHLCON_LACFG

#define PHLCON_LACFG ( x ) ((x & 0xf) << 8)

Definition at line 394 of file enc28j60_regs.h.

◆ PHLCON_LBCFG

#define PHLCON_LBCFG ( x ) ((x & 0xf) << 4)

Definition at line 395 of file enc28j60_regs.h.

◆ PHLCON_LFRQ

#define PHLCON_LFRQ ( x ) ((x & 0x3) << 2)

Definition at line 396 of file enc28j60_regs.h.

◆ PHLCON_STRCH

#define PHLCON_STRCH 0x0002

Definition at line 397 of file enc28j60_regs.h.

◆ PHSTAT1_JBSTAT

#define PHSTAT1_JBSTAT 0x0002

Definition at line 349 of file enc28j60_regs.h.

◆ PHSTAT1_LLSTAT

#define PHSTAT1_LLSTAT 0x0004

Definition at line 348 of file enc28j60_regs.h.

◆ PHSTAT1_PFDPX

#define PHSTAT1_PFDPX 0x1000

Definition at line 346 of file enc28j60_regs.h.

◆ PHSTAT1_PHDPX

#define PHSTAT1_PHDPX 0x0800

Definition at line 347 of file enc28j60_regs.h.

◆ PHSTAT2_COLSTAT

#define PHSTAT2_COLSTAT 0x0800

Definition at line 368 of file enc28j60_regs.h.

◆ PHSTAT2_DPXSTAT

#define PHSTAT2_DPXSTAT 0x0200

Definition at line 370 of file enc28j60_regs.h.

◆ PHSTAT2_LSTAT

#define PHSTAT2_LSTAT 0x0400

Definition at line 369 of file enc28j60_regs.h.

◆ PHSTAT2_PLRITY

#define PHSTAT2_PLRITY 0x0020

Definition at line 371 of file enc28j60_regs.h.

◆ PHSTAT2_RXSTAT

#define PHSTAT2_RXSTAT 0x1000

Definition at line 367 of file enc28j60_regs.h.

◆ PHSTAT2_TXSTAT

#define PHSTAT2_TXSTAT 0x2000

Definition at line 366 of file enc28j60_regs.h.

◆ REG_B0_EDMACSH

#define REG_B0_EDMACSH 0x17 /* DMA checksum - high byte */

Definition at line 91 of file enc28j60_regs.h.

◆ REG_B0_EDMACSL

#define REG_B0_EDMACSL 0x16 /* DMA checksum - low byte */

Definition at line 90 of file enc28j60_regs.h.

◆ REG_B0_EDMADSTH

#define REG_B0_EDMADSTH 0x15 /* DMA destination pointer - high byte */

Definition at line 89 of file enc28j60_regs.h.

◆ REG_B0_EDMADSTL

#define REG_B0_EDMADSTL 0x14 /* DMA destination pointer - low byte */

Definition at line 88 of file enc28j60_regs.h.

◆ REG_B0_EDMANDH

#define REG_B0_EDMANDH 0x13 /* DMA end pointer - high byte */

Definition at line 87 of file enc28j60_regs.h.

◆ REG_B0_EDMANDL

#define REG_B0_EDMANDL 0x12 /* DMA end pointer - low byte */

Definition at line 86 of file enc28j60_regs.h.

◆ REG_B0_EDMASTH

#define REG_B0_EDMASTH 0x11 /* DMA start pointer - high byte */

Definition at line 85 of file enc28j60_regs.h.

◆ REG_B0_EDMASTL

#define REG_B0_EDMASTL 0x10 /* DMA start pointer - low byte */

Definition at line 84 of file enc28j60_regs.h.

◆ REG_B0_ERDPTH

#define REG_B0_ERDPTH 0x01 /* read data pointer - high byte */

Definition at line 69 of file enc28j60_regs.h.

◆ REG_B0_ERDPTL

#define REG_B0_ERDPTL 0x00 /* read data pointer - low byte */

Definition at line 68 of file enc28j60_regs.h.

◆ REG_B0_ERXNDH

#define REG_B0_ERXNDH 0x0b /* RX end pointer - high byte */

Definition at line 79 of file enc28j60_regs.h.

◆ REG_B0_ERXNDL

#define REG_B0_ERXNDL 0x0a /* RX end pointer - low byte */

Definition at line 78 of file enc28j60_regs.h.

◆ REG_B0_ERXRDPTH

#define REG_B0_ERXRDPTH 0x0d /* RX read pointer - high byte */

Definition at line 81 of file enc28j60_regs.h.

◆ REG_B0_ERXRDPTL

#define REG_B0_ERXRDPTL 0x0c /* RX read pointer - low byte */

Definition at line 80 of file enc28j60_regs.h.

◆ REG_B0_ERXSTH

#define REG_B0_ERXSTH 0x09 /* RX start pointer - high byte */

Definition at line 77 of file enc28j60_regs.h.

◆ REG_B0_ERXSTL

#define REG_B0_ERXSTL 0x08 /* RX start pointer - low byte */

Definition at line 76 of file enc28j60_regs.h.

◆ REG_B0_ERXWRPTH

#define REG_B0_ERXWRPTH 0x0f /* RX write pointer - high byte */

Definition at line 83 of file enc28j60_regs.h.

◆ REG_B0_ERXWRPTL

#define REG_B0_ERXWRPTL 0x0e /* RX write pointer - low byte */

Definition at line 82 of file enc28j60_regs.h.

◆ REG_B0_ETXNDH

#define REG_B0_ETXNDH 0x07 /* TX end pointer - high byte */

Definition at line 75 of file enc28j60_regs.h.

◆ REG_B0_ETXNDL

#define REG_B0_ETXNDL 0x06 /* TX end pointer - low byte */

Definition at line 74 of file enc28j60_regs.h.

◆ REG_B0_ETXSTH

#define REG_B0_ETXSTH 0x05 /* TX start pointer - high byte */

Definition at line 73 of file enc28j60_regs.h.

◆ REG_B0_ETXSTL

#define REG_B0_ETXSTL 0x04 /* TX start pointer - low byte */

Definition at line 72 of file enc28j60_regs.h.

◆ REG_B0_EWRPTH

#define REG_B0_EWRPTH 0x03 /* write data pointer - high byte */

Definition at line 71 of file enc28j60_regs.h.

◆ REG_B0_EWRPTL

#define REG_B0_EWRPTL 0x02 /* write data pointer - low byte */

Definition at line 70 of file enc28j60_regs.h.

◆ REG_B1_EHT0

#define REG_B1_EHT0 0x00 /* hash table - byte 0 */

Definition at line 98 of file enc28j60_regs.h.

◆ REG_B1_EHT1

#define REG_B1_EHT1 0x01 /* hash table - byte 1 */

Definition at line 99 of file enc28j60_regs.h.

◆ REG_B1_EHT2

#define REG_B1_EHT2 0x02 /* hash table - byte 2 */

Definition at line 100 of file enc28j60_regs.h.

◆ REG_B1_EHT3

#define REG_B1_EHT3 0x03 /* hash table - byte 3 */

Definition at line 101 of file enc28j60_regs.h.

◆ REG_B1_EHT4

#define REG_B1_EHT4 0x04 /* hash table - byte 4 */

Definition at line 102 of file enc28j60_regs.h.

◆ REG_B1_EHT5

#define REG_B1_EHT5 0x05 /* hash table - byte 5 */

Definition at line 103 of file enc28j60_regs.h.

◆ REG_B1_EHT6

#define REG_B1_EHT6 0x06 /* hash table - byte 6 */

Definition at line 104 of file enc28j60_regs.h.

◆ REG_B1_EHT7

#define REG_B1_EHT7 0x07 /* hash table - byte 7 */

Definition at line 105 of file enc28j60_regs.h.

◆ REG_B1_EPKTCNT

#define REG_B1_EPKTCNT 0x19 /* packet count */

Definition at line 119 of file enc28j60_regs.h.

◆ REG_B1_EPMCSH

#define REG_B1_EPMCSH 0x11 /* pattern match checksum - high byte */

Definition at line 115 of file enc28j60_regs.h.

◆ REG_B1_EPMCSL

#define REG_B1_EPMCSL 0x10 /* pattern match checksum - low byte */

Definition at line 114 of file enc28j60_regs.h.

◆ REG_B1_EPMM0

#define REG_B1_EPMM0 0x08 /* pattern match mask - byte 0 */

Definition at line 106 of file enc28j60_regs.h.

◆ REG_B1_EPMM1

#define REG_B1_EPMM1 0x09 /* pattern match mask - byte 1 */

Definition at line 107 of file enc28j60_regs.h.

◆ REG_B1_EPMM2

#define REG_B1_EPMM2 0x0a /* pattern match mask - byte 2 */

Definition at line 108 of file enc28j60_regs.h.

◆ REG_B1_EPMM3

#define REG_B1_EPMM3 0x0b /* pattern match mask - byte 3 */

Definition at line 109 of file enc28j60_regs.h.

◆ REG_B1_EPMM4

#define REG_B1_EPMM4 0x0c /* pattern match mask - byte 4 */

Definition at line 110 of file enc28j60_regs.h.

◆ REG_B1_EPMM5

#define REG_B1_EPMM5 0x0d /* pattern match mask - byte 5 */

Definition at line 111 of file enc28j60_regs.h.

◆ REG_B1_EPMM6

#define REG_B1_EPMM6 0x0e /* pattern match mask - byte 6 */

Definition at line 112 of file enc28j60_regs.h.

◆ REG_B1_EPMM7

#define REG_B1_EPMM7 0x0f /* pattern match mask - byte 7 */

Definition at line 113 of file enc28j60_regs.h.

◆ REG_B1_EPMOH

#define REG_B1_EPMOH 0x15 /* pattern match offset - high byte */

Definition at line 117 of file enc28j60_regs.h.

◆ REG_B1_EPMOL

#define REG_B1_EPMOL 0x14 /* pattern match offset - low byte */

Definition at line 116 of file enc28j60_regs.h.

◆ REG_B1_ERXFCON

#define REG_B1_ERXFCON 0x18 /* receive filter control register */

Definition at line 118 of file enc28j60_regs.h.

◆ REG_B2_MABBIPG

#define REG_B2_MABBIPG 0x04 /* back-to-back inter-packet gap */

Definition at line 129 of file enc28j60_regs.h.

◆ REG_B2_MACLCON1

#define REG_B2_MACLCON1 0x08 /* retransmission maximum */

Definition at line 132 of file enc28j60_regs.h.

◆ REG_B2_MACLCON2

#define REG_B2_MACLCON2 0x09 /* collision window */

Definition at line 133 of file enc28j60_regs.h.

◆ REG_B2_MACON1

#define REG_B2_MACON1 0x00 /* MAC control register 1 */

Definition at line 126 of file enc28j60_regs.h.

◆ REG_B2_MACON3

#define REG_B2_MACON3 0x02 /* MAC control register 3 */

Definition at line 127 of file enc28j60_regs.h.

◆ REG_B2_MACON4

#define REG_B2_MACON4 0x03 /* MAC control register 4 */

Definition at line 128 of file enc28j60_regs.h.

◆ REG_B2_MAIPGH

#define REG_B2_MAIPGH 0x07 /* non-back-to-back inter-packet gap - high byte */

Definition at line 131 of file enc28j60_regs.h.

◆ REG_B2_MAIPGL

#define REG_B2_MAIPGL 0x06 /* non-back-to-back inter-packet gap - low byte */

Definition at line 130 of file enc28j60_regs.h.

◆ REG_B2_MAMXFLH

#define REG_B2_MAMXFLH 0x0b /* maximum frame length - high byte */

Definition at line 135 of file enc28j60_regs.h.

◆ REG_B2_MAMXFLL

#define REG_B2_MAMXFLL 0x0a /* maximum frame length - low byte */

Definition at line 134 of file enc28j60_regs.h.

◆ REG_B2_MICMD

#define REG_B2_MICMD 0x12 /* MIIM command */

Definition at line 136 of file enc28j60_regs.h.

◆ REG_B2_MIRDH

#define REG_B2_MIRDH 0x19 /* MIIM read data register - high byte */

Definition at line 141 of file enc28j60_regs.h.

◆ REG_B2_MIRDL

#define REG_B2_MIRDL 0x18 /* MIIM read data register - low byte */

Definition at line 140 of file enc28j60_regs.h.

◆ REG_B2_MIREGADR

#define REG_B2_MIREGADR 0x14 /* MIIM register address */

Definition at line 137 of file enc28j60_regs.h.

◆ REG_B2_MIWRH

#define REG_B2_MIWRH 0x17 /* MIIM write data register - high byte */

Definition at line 139 of file enc28j60_regs.h.

◆ REG_B2_MIWRL

#define REG_B2_MIWRL 0x16 /* MIIM write data register - low byte */

Definition at line 138 of file enc28j60_regs.h.

◆ REG_B3_EBSTCON

#define REG_B3_EBSTCON 0x07 /* built-in self-test control register */

Definition at line 155 of file enc28j60_regs.h.

◆ REG_B3_EBSTCSH

#define REG_B3_EBSTCSH 0x09 /* built-in self-test checksum - high byte */

Definition at line 157 of file enc28j60_regs.h.

◆ REG_B3_EBSTCSL

#define REG_B3_EBSTCSL 0x08 /* built-in self-test checksum - low byte */

Definition at line 156 of file enc28j60_regs.h.

◆ REG_B3_EBSTSD

#define REG_B3_EBSTSD 0x06 /* built-in self-test fill seed */

Definition at line 154 of file enc28j60_regs.h.

◆ REG_B3_ECOCON

#define REG_B3_ECOCON 0x15 /* clock output control */

Definition at line 160 of file enc28j60_regs.h.

◆ REG_B3_EFLOCON

#define REG_B3_EFLOCON 0x17 /* Ethernet flow control */

Definition at line 161 of file enc28j60_regs.h.

◆ REG_B3_EPAUSH

#define REG_B3_EPAUSH 0x19 /* pause timer value - high byte */

Definition at line 163 of file enc28j60_regs.h.

◆ REG_B3_EPAUSL

#define REG_B3_EPAUSL 0x18 /* pause timer value - low byte */

Definition at line 162 of file enc28j60_regs.h.

◆ REG_B3_EREVID

#define REG_B3_EREVID 0x12 /* Ethernet revision ID */

Definition at line 159 of file enc28j60_regs.h.

◆ REG_B3_MAADR1

#define REG_B3_MAADR1 0x04 /* MAC address - byte 1 */

Definition at line 152 of file enc28j60_regs.h.

◆ REG_B3_MAADR2

#define REG_B3_MAADR2 0x05 /* MAC address - byte 2 */

Definition at line 153 of file enc28j60_regs.h.

◆ REG_B3_MAADR3

#define REG_B3_MAADR3 0x02 /* MAC address - byte 3 */

Definition at line 150 of file enc28j60_regs.h.

◆ REG_B3_MAADR4

#define REG_B3_MAADR4 0x03 /* MAC address - byte 4 */

Definition at line 151 of file enc28j60_regs.h.

◆ REG_B3_MAADR5

#define REG_B3_MAADR5 0x00 /* MAC address - byte 5 */

Definition at line 148 of file enc28j60_regs.h.

◆ REG_B3_MAADR6

#define REG_B3_MAADR6 0x01 /* MAC address - byte 6 */

Definition at line 149 of file enc28j60_regs.h.

◆ REG_B3_MISTAT

#define REG_B3_MISTAT 0x0a /* MIIM status register */

Definition at line 158 of file enc28j60_regs.h.

◆ REG_ECON1

#define REG_ECON1 0x1f

configuration 2

Definition at line 61 of file enc28j60_regs.h.

◆ REG_ECON2

#define REG_ECON2 0x1e

configuration 1

Definition at line 60 of file enc28j60_regs.h.

◆ REG_EIE

#define REG_EIE 0x1b

interrupt enable

Definition at line 57 of file enc28j60_regs.h.

◆ REG_EIR

#define REG_EIR 0x1c

interrupt flags

Definition at line 58 of file enc28j60_regs.h.

◆ REG_ESTAT

#define REG_ESTAT 0x1d

status

Definition at line 59 of file enc28j60_regs.h.

◆ REG_PHY_PHCON1

#define REG_PHY_PHCON1 0x00

Definition at line 170 of file enc28j60_regs.h.

◆ REG_PHY_PHCON2

#define REG_PHY_PHCON2 0x10

Definition at line 174 of file enc28j60_regs.h.

◆ REG_PHY_PHID1

#define REG_PHY_PHID1 0x02

Definition at line 172 of file enc28j60_regs.h.

◆ REG_PHY_PHID2

#define REG_PHY_PHID2 0x03

Definition at line 173 of file enc28j60_regs.h.

◆ REG_PHY_PHIE

#define REG_PHY_PHIE 0x12

Definition at line 176 of file enc28j60_regs.h.

◆ REG_PHY_PHIR

#define REG_PHY_PHIR 0x13

Definition at line 177 of file enc28j60_regs.h.

◆ REG_PHY_PHLCON

#define REG_PHY_PHLCON 0x14

Definition at line 178 of file enc28j60_regs.h.

◆ REG_PHY_PHSTAT1

#define REG_PHY_PHSTAT1 0x01

Definition at line 171 of file enc28j60_regs.h.

◆ REG_PHY_PHSTAT2

#define REG_PHY_PHSTAT2 0x11

Definition at line 175 of file enc28j60_regs.h.

◆ TX_PCRCEN

#define TX_PCRCEN 0x02

Definition at line 426 of file enc28j60_regs.h.

◆ TX_PHUGEEN

#define TX_PHUGEEN 0x08

Definition at line 424 of file enc28j60_regs.h.

◆ TX_POVERRIDE

#define TX_POVERRIDE 0x01

Definition at line 427 of file enc28j60_regs.h.

◆ TX_PPADEN

#define TX_PPADEN 0x04

Definition at line 425 of file enc28j60_regs.h.

Detailed Description

SPI instruction set

Available address pointers

Shared registers (accessible on each bank)

Register in bank 0 - Ethernet registers

Registers in bank 1 - Ethernet registers

Registers in bank 2 - MAC registers

Registers in bank 3 - MIXED registers

PHY Registers

EIE bitfields

EIR bitfields

ESTAT bitfields

ECON1 bitfields

ECON2 bitfields

ERXFCON bitfields

MACON1 bitfields

MACON3 bitfields

MACON4 bitfields

MABBIPG bitfields

MAIPGL bitfields

MICMD bitfields

MISTAT bitfields

EFLOCON bitfields

PHCON1 bitfields

PHSTAT1 bitfields

PHCON2 bitfields

PHSTAT2 bitfields

PHIE bitfields

PHIR bitfields

PHLCON bitfields

Frame status bitfields

TX control byte bitfields