Imagination Technologies MIPS32R2 Common implementation. More...
Imagination Technologies MIPS32R2 Common implementation.
|API for supporting External Interrupt Controllers (EIC mode) |
|void||eic_irq_configure (int irq_num)|
|Configure and route the interrupt. |
|void||eic_irq_enable (int irq_num)|
|Enable an interrupt. |
|void||eic_irq_disable (int irq_num)|
|Disable an interrupt. |
|void||eic_irq_ack (int irq_num)|
|Acknowledge an interrupt. |
|@ brief Internal Interrupt numbers More...|
|#define EIC_IRQ_TIMER (-1)|
@ brief Internal Interrupt numbers
MIPS cores have a few internally generated interrupts from the Timer, Performance Counters and Fast Debug Channel hardware, in EIC mode these become outputs from the core and are connected to the external controller, the external control then loops these back at whichever IPL it decides
We use negative numbers to represent these, leaving positive numbers free for the SoC specific interrupts