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Data Structures | Macros | Variables
periph_cpu.h File Reference
CPU » Microchip SAMD5x/SAME5x

CPU specific definitions for internal peripheral handling. More...

Detailed Description

CPU specific definitions for internal peripheral handling.

CPU specific definitions for internal peripheral handling

Author
Benjamin Valentin benja.nosp@m.min..nosp@m.valen.nosp@m.tin@.nosp@m.ml-pa.nosp@m..com

Definition in file periph_cpu.h.

#include <limits.h>
#include "macros/units.h"
#include "periph_cpu_common.h"
#include "candev_samd5x.h"
+ Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Data Structures

struct  sam0_aux_cfg_mapping
 NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on. More...
 

Macros

#define SPI_HWCS(x)   (UINT_MAX - 1)
 Override SPI hardware chip select macro.
 
#define DAC_RES_BITS   (12)
 The MCU has a 12 bit DAC.
 
#define DAC_NUMOF   (2)
 The MCU has two DAC outputs.
 

Variables

static const gpio_t sam0_adc_pins [2][16]
 Pins that can be used for ADC input.
 
static const gpio_t rtc_tamper_pins [RTC_NUM_OF_TAMPERS]
 RTC input pins that can be used for tamper detection and wake from Deep Sleep.
 
static const gpio_t gclk_io_pins []
 Pins that have peripheral function GCLK.
 
static const uint8_t gclk_io_ids []
 GCLK IDs of pins that have peripheral function GCLK - This maps directly to gclk_io_pins.
 
#define SAM0_DFLL_FREQ_HZ   MHZ(48)
 DFLL runs at at fixed frequency of 48 MHz.
 
#define SAM0_XOSC_FREQ_HZ   (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)
  *
 
#define SAM0_DPLL_FREQ_MIN_HZ   MHZ(96)
 DPLL must run with at least 96 MHz.
 
#define SAM0_DPLL_FREQ_MAX_HZ   MHZ(200)
 DPLL frequency must not exceed 200 MHz.
 

Power mode configuration

#define PM_NUM_MODES   (4)
 Backup, Hibernate, Standby, Idle.
 
enum  { SAM0_PM_BACKUP = 0 , SAM0_PM_HIBERNATE = 1 , SAM0_PM_STANDBY = 2 , SAM0_PM_IDLE = 3 }
 Power modes. More...
 

SAMD5x GCLK definitions

#define SAM0_GCLK_MAIN   0
 120 MHz main clock

 
#define SAM0_GCLK_32KHZ   1
 32 kHz clock

 
#define SAM0_GCLK_TIMER   2
 4-8 MHz clock for xTimer
 
#define SAM0_GCLK_PERIPH   3
 12-48 MHz (DFLL) clock

 
#define SAM0_GCLK_100MHZ   4
 100MHz FDPLL clock

 

GCLK compatibility definitions

#define SAM0_GCLK_8MHZ   SAM0_GCLK_TIMER
 
#define SAM0_GCLK_48MHZ   SAM0_GCLK_PERIPH
 
#define ADC0_INPUTCTRL_MUXPOS_PA02   ADC_INPUTCTRL_MUXPOS_AIN0
 ADC pin aliases.
 
#define ADC0_INPUTCTRL_MUXPOS_PA03   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC0_INPUTCTRL_MUXPOS_PB08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC0_INPUTCTRL_MUXPOS_PB09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC0_INPUTCTRL_MUXPOS_PA04   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC0_INPUTCTRL_MUXPOS_PA05   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC0_INPUTCTRL_MUXPOS_PA06   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC0_INPUTCTRL_MUXPOS_PA07   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 
#define ADC0_INPUTCTRL_MUXPOS_PA08   ADC_INPUTCTRL_MUXPOS_AIN8
 Alias for AIN8.
 
#define ADC0_INPUTCTRL_MUXPOS_PA09   ADC_INPUTCTRL_MUXPOS_AIN9
 Alias for AIN9.
 
#define ADC0_INPUTCTRL_MUXPOS_PA10   ADC_INPUTCTRL_MUXPOS_AIN10
 Alias for AIN10.
 
#define ADC0_INPUTCTRL_MUXPOS_PA11   ADC_INPUTCTRL_MUXPOS_AIN11
 Alias for AIN11.
 
#define ADC0_INPUTCTRL_MUXPOS_PB00   ADC_INPUTCTRL_MUXPOS_AIN12
 Alias for AIN12.
 
#define ADC0_INPUTCTRL_MUXPOS_PB01   ADC_INPUTCTRL_MUXPOS_AIN13
 Alias for AIN13.
 
#define ADC0_INPUTCTRL_MUXPOS_PB02   ADC_INPUTCTRL_MUXPOS_AIN14
 Alias for AIN14.
 
#define ADC0_INPUTCTRL_MUXPOS_PB03   ADC_INPUTCTRL_MUXPOS_AIN15
 Alias for AIN15.
 
#define ADC1_INPUTCTRL_MUXPOS_PB08   ADC_INPUTCTRL_MUXPOS_AIN0
 Alias for AIN0.
 
#define ADC1_INPUTCTRL_MUXPOS_PB09   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC1_INPUTCTRL_MUXPOS_PA08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC1_INPUTCTRL_MUXPOS_PA09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC1_INPUTCTRL_MUXPOS_PC02   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC1_INPUTCTRL_MUXPOS_PC03   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC1_INPUTCTRL_MUXPOS_PB04   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC1_INPUTCTRL_MUXPOS_PB05   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 
#define ADC1_INPUTCTRL_MUXPOS_PB06   ADC_INPUTCTRL_MUXPOS_AIN8
 Alias for AIN8.
 
#define ADC1_INPUTCTRL_MUXPOS_PB07   ADC_INPUTCTRL_MUXPOS_AIN9
 Alias for AIN9.
 
#define ADC1_INPUTCTRL_MUXPOS_PC00   ADC_INPUTCTRL_MUXPOS_AIN10
 Alias for AIN10.
 
#define ADC1_INPUTCTRL_MUXPOS_PC01   ADC_INPUTCTRL_MUXPOS_AIN11
 Alias for AIN11.
 
#define ADC1_INPUTCTRL_MUXPOS_PC30   ADC_INPUTCTRL_MUXPOS_AIN12
 Alias for AIN12.
 
#define ADC1_INPUTCTRL_MUXPOS_PC31   ADC_INPUTCTRL_MUXPOS_AIN13
 Alias for AIN13.
 
#define ADC1_INPUTCTRL_MUXPOS_PD00   ADC_INPUTCTRL_MUXPOS_AIN14
 Alias for AIN14.
 
#define ADC1_INPUTCTRL_MUXPOS_PD01   ADC_INPUTCTRL_MUXPOS_AIN15
 Alias for AIN15.
 
#define ADC0_INPUTCTRL_MUXNEG_PA02   ADC_INPUTCTRL_MUXPOS_AIN0
 Alias for AIN0.
 
#define ADC0_INPUTCTRL_MUXNEG_PA03   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC0_INPUTCTRL_MUXNEG_PB08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC0_INPUTCTRL_MUXNEG_PB09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC0_INPUTCTRL_MUXNEG_PA04   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC0_INPUTCTRL_MUXNEG_PA05   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC0_INPUTCTRL_MUXNEG_PA06   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC0_INPUTCTRL_MUXNEG_PA07   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 
#define ADC1_INPUTCTRL_MUXNEG_PB08   ADC_INPUTCTRL_MUXPOS_AIN0
 Alias for AIN0.
 
#define ADC1_INPUTCTRL_MUXNEG_PB09   ADC_INPUTCTRL_MUXPOS_AIN1
 Alias for AIN1.
 
#define ADC1_INPUTCTRL_MUXNEG_PA08   ADC_INPUTCTRL_MUXPOS_AIN2
 Alias for AIN2.
 
#define ADC1_INPUTCTRL_MUXNEG_PA09   ADC_INPUTCTRL_MUXPOS_AIN3
 Alias for AIN3.
 
#define ADC1_INPUTCTRL_MUXNEG_PC02   ADC_INPUTCTRL_MUXPOS_AIN4
 Alias for AIN4.
 
#define ADC1_INPUTCTRL_MUXNEG_PC03   ADC_INPUTCTRL_MUXPOS_AIN5
 Alias for AIN5.
 
#define ADC1_INPUTCTRL_MUXNEG_PB04   ADC_INPUTCTRL_MUXPOS_AIN6
 Alias for AIN6.
 
#define ADC1_INPUTCTRL_MUXNEG_PB05   ADC_INPUTCTRL_MUXPOS_AIN7
 Alias for AIN7.
 

Real time counter configuration

#define RTT_MAX_VALUE   (0xffffffff)
 
#define RTT_CLOCK_FREQUENCY   (32768U) /* in Hz */
 
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
 
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY) /* in Hz */
 

QSPI pins are fixed

#define SAM0_QSPI_PIN_CLK   GPIO_PIN(PB, 10)
 Clock

 
#define SAM0_QSPI_PIN_CS   GPIO_PIN(PB, 11)
 Chip Select

 
#define SAM0_QSPI_PIN_DATA_0   GPIO_PIN(PA, 8)
 D0 / MOSI

 
#define SAM0_QSPI_PIN_DATA_1   GPIO_PIN(PA, 9)
 D1 / MISO

 
#define SAM0_QSPI_PIN_DATA_2   GPIO_PIN(PA, 10)
 D2 / WP

 
#define SAM0_QSPI_PIN_DATA_3   GPIO_PIN(PA, 11)
 D3 / HOLD

 
#define SAM0_QSPI_MUX   GPIO_MUX_H
 QSPI mux

 

SDHC pins are fixed

#define SAM0_SDHC_MUX   GPIO_MUX_I
 SDHC function

 
#define SAM0_SDHC0_PIN_SDCMD   GPIO_PIN(PA, 8)
 Command

 
#define SAM0_SDHC0_PIN_SDDAT0   GPIO_PIN(PA, 9)
 DATA0

 
#define SAM0_SDHC0_PIN_SDDAT1   GPIO_PIN(PA, 10)
 DATA1

 
#define SAM0_SDHC0_PIN_SDDAT2   GPIO_PIN(PA, 11)
 DATA2

 
#define SAM0_SDHC0_PIN_SDDAT3   GPIO_PIN(PB, 10)
 DATA3

 
#define SAM0_SDHC0_PIN_SDCK   GPIO_PIN(PB, 11)
 Clock

 
#define SAM0_SDHC1_PIN_SDCMD   GPIO_PIN(PA, 20)
 Command

 
#define SAM0_SDHC1_PIN_SDDAT0   GPIO_PIN(PB, 18)
 DATA0

 
#define SAM0_SDHC1_PIN_SDDAT1   GPIO_PIN(PB, 19)
 DATA1

 
#define SAM0_SDHC1_PIN_SDDAT2   GPIO_PIN(PB, 20)
 DATA2

 
#define SAM0_SDHC1_PIN_SDDAT3   GPIO_PIN(PB, 21)
 DATA3

 
#define SAM0_SDHC1_PIN_SDCK   GPIO_PIN(PA, 21)
 Clock

 

Macro Definition Documentation

◆ ADC0_INPUTCTRL_MUXNEG_PA02

#define ADC0_INPUTCTRL_MUXNEG_PA02   ADC_INPUTCTRL_MUXPOS_AIN0

Alias for AIN0.

Definition at line 160 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PA03

#define ADC0_INPUTCTRL_MUXNEG_PA03   ADC_INPUTCTRL_MUXPOS_AIN1

Alias for AIN1.

Definition at line 161 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PA04

#define ADC0_INPUTCTRL_MUXNEG_PA04   ADC_INPUTCTRL_MUXPOS_AIN4

Alias for AIN4.

Definition at line 164 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PA05

#define ADC0_INPUTCTRL_MUXNEG_PA05   ADC_INPUTCTRL_MUXPOS_AIN5

Alias for AIN5.

Definition at line 165 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PA06

#define ADC0_INPUTCTRL_MUXNEG_PA06   ADC_INPUTCTRL_MUXPOS_AIN6

Alias for AIN6.

Definition at line 166 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PA07

#define ADC0_INPUTCTRL_MUXNEG_PA07   ADC_INPUTCTRL_MUXPOS_AIN7

Alias for AIN7.

Definition at line 167 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PB08

#define ADC0_INPUTCTRL_MUXNEG_PB08   ADC_INPUTCTRL_MUXPOS_AIN2

Alias for AIN2.

Definition at line 162 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXNEG_PB09

#define ADC0_INPUTCTRL_MUXNEG_PB09   ADC_INPUTCTRL_MUXPOS_AIN3

Alias for AIN3.

Definition at line 163 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA02

#define ADC0_INPUTCTRL_MUXPOS_PA02   ADC_INPUTCTRL_MUXPOS_AIN0

ADC pin aliases.

Alias for AIN0

Definition at line 126 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA03

#define ADC0_INPUTCTRL_MUXPOS_PA03   ADC_INPUTCTRL_MUXPOS_AIN1

Alias for AIN1.

Definition at line 127 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA04

#define ADC0_INPUTCTRL_MUXPOS_PA04   ADC_INPUTCTRL_MUXPOS_AIN4

Alias for AIN4.

Definition at line 130 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA05

#define ADC0_INPUTCTRL_MUXPOS_PA05   ADC_INPUTCTRL_MUXPOS_AIN5

Alias for AIN5.

Definition at line 131 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA06

#define ADC0_INPUTCTRL_MUXPOS_PA06   ADC_INPUTCTRL_MUXPOS_AIN6

Alias for AIN6.

Definition at line 132 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA07

#define ADC0_INPUTCTRL_MUXPOS_PA07   ADC_INPUTCTRL_MUXPOS_AIN7

Alias for AIN7.

Definition at line 133 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA08

#define ADC0_INPUTCTRL_MUXPOS_PA08   ADC_INPUTCTRL_MUXPOS_AIN8

Alias for AIN8.

Definition at line 134 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA09

#define ADC0_INPUTCTRL_MUXPOS_PA09   ADC_INPUTCTRL_MUXPOS_AIN9

Alias for AIN9.

Definition at line 135 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA10

#define ADC0_INPUTCTRL_MUXPOS_PA10   ADC_INPUTCTRL_MUXPOS_AIN10

Alias for AIN10.

Definition at line 136 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PA11

#define ADC0_INPUTCTRL_MUXPOS_PA11   ADC_INPUTCTRL_MUXPOS_AIN11

Alias for AIN11.

Definition at line 137 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB00

#define ADC0_INPUTCTRL_MUXPOS_PB00   ADC_INPUTCTRL_MUXPOS_AIN12

Alias for AIN12.

Definition at line 138 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB01

#define ADC0_INPUTCTRL_MUXPOS_PB01   ADC_INPUTCTRL_MUXPOS_AIN13

Alias for AIN13.

Definition at line 139 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB02

#define ADC0_INPUTCTRL_MUXPOS_PB02   ADC_INPUTCTRL_MUXPOS_AIN14

Alias for AIN14.

Definition at line 140 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB03

#define ADC0_INPUTCTRL_MUXPOS_PB03   ADC_INPUTCTRL_MUXPOS_AIN15

Alias for AIN15.

Definition at line 141 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB08

#define ADC0_INPUTCTRL_MUXPOS_PB08   ADC_INPUTCTRL_MUXPOS_AIN2

Alias for AIN2.

Definition at line 128 of file periph_cpu.h.

◆ ADC0_INPUTCTRL_MUXPOS_PB09

#define ADC0_INPUTCTRL_MUXPOS_PB09   ADC_INPUTCTRL_MUXPOS_AIN3

Alias for AIN3.

Definition at line 129 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PA08

#define ADC1_INPUTCTRL_MUXNEG_PA08   ADC_INPUTCTRL_MUXPOS_AIN2

Alias for AIN2.

Definition at line 171 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PA09

#define ADC1_INPUTCTRL_MUXNEG_PA09   ADC_INPUTCTRL_MUXPOS_AIN3

Alias for AIN3.

Definition at line 172 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PB04

#define ADC1_INPUTCTRL_MUXNEG_PB04   ADC_INPUTCTRL_MUXPOS_AIN6

Alias for AIN6.

Definition at line 175 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PB05

#define ADC1_INPUTCTRL_MUXNEG_PB05   ADC_INPUTCTRL_MUXPOS_AIN7

Alias for AIN7.

Definition at line 176 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PB08

#define ADC1_INPUTCTRL_MUXNEG_PB08   ADC_INPUTCTRL_MUXPOS_AIN0

Alias for AIN0.

Definition at line 169 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PB09

#define ADC1_INPUTCTRL_MUXNEG_PB09   ADC_INPUTCTRL_MUXPOS_AIN1

Alias for AIN1.

Definition at line 170 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PC02

#define ADC1_INPUTCTRL_MUXNEG_PC02   ADC_INPUTCTRL_MUXPOS_AIN4

Alias for AIN4.

Definition at line 173 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXNEG_PC03

#define ADC1_INPUTCTRL_MUXNEG_PC03   ADC_INPUTCTRL_MUXPOS_AIN5

Alias for AIN5.

Definition at line 174 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PA08

#define ADC1_INPUTCTRL_MUXPOS_PA08   ADC_INPUTCTRL_MUXPOS_AIN2

Alias for AIN2.

Definition at line 145 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PA09

#define ADC1_INPUTCTRL_MUXPOS_PA09   ADC_INPUTCTRL_MUXPOS_AIN3

Alias for AIN3.

Definition at line 146 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB04

#define ADC1_INPUTCTRL_MUXPOS_PB04   ADC_INPUTCTRL_MUXPOS_AIN6

Alias for AIN6.

Definition at line 149 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB05

#define ADC1_INPUTCTRL_MUXPOS_PB05   ADC_INPUTCTRL_MUXPOS_AIN7

Alias for AIN7.

Definition at line 150 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB06

#define ADC1_INPUTCTRL_MUXPOS_PB06   ADC_INPUTCTRL_MUXPOS_AIN8

Alias for AIN8.

Definition at line 151 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB07

#define ADC1_INPUTCTRL_MUXPOS_PB07   ADC_INPUTCTRL_MUXPOS_AIN9

Alias for AIN9.

Definition at line 152 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB08

#define ADC1_INPUTCTRL_MUXPOS_PB08   ADC_INPUTCTRL_MUXPOS_AIN0

Alias for AIN0.

Definition at line 143 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PB09

#define ADC1_INPUTCTRL_MUXPOS_PB09   ADC_INPUTCTRL_MUXPOS_AIN1

Alias for AIN1.

Definition at line 144 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC00

#define ADC1_INPUTCTRL_MUXPOS_PC00   ADC_INPUTCTRL_MUXPOS_AIN10

Alias for AIN10.

Definition at line 153 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC01

#define ADC1_INPUTCTRL_MUXPOS_PC01   ADC_INPUTCTRL_MUXPOS_AIN11

Alias for AIN11.

Definition at line 154 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC02

#define ADC1_INPUTCTRL_MUXPOS_PC02   ADC_INPUTCTRL_MUXPOS_AIN4

Alias for AIN4.

Definition at line 147 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC03

#define ADC1_INPUTCTRL_MUXPOS_PC03   ADC_INPUTCTRL_MUXPOS_AIN5

Alias for AIN5.

Definition at line 148 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC30

#define ADC1_INPUTCTRL_MUXPOS_PC30   ADC_INPUTCTRL_MUXPOS_AIN12

Alias for AIN12.

Definition at line 155 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PC31

#define ADC1_INPUTCTRL_MUXPOS_PC31   ADC_INPUTCTRL_MUXPOS_AIN13

Alias for AIN13.

Definition at line 156 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PD00

#define ADC1_INPUTCTRL_MUXPOS_PD00   ADC_INPUTCTRL_MUXPOS_AIN14

Alias for AIN14.

Definition at line 157 of file periph_cpu.h.

◆ ADC1_INPUTCTRL_MUXPOS_PD01

#define ADC1_INPUTCTRL_MUXPOS_PD01   ADC_INPUTCTRL_MUXPOS_AIN15

Alias for AIN15.

Definition at line 158 of file periph_cpu.h.

◆ DAC_NUMOF

#define DAC_NUMOF   (2)

The MCU has two DAC outputs.

Definition at line 187 of file periph_cpu.h.

◆ DAC_RES_BITS

#define DAC_RES_BITS   (12)

The MCU has a 12 bit DAC.

Definition at line 182 of file periph_cpu.h.

◆ PM_NUM_MODES

#define PM_NUM_MODES   (4)

Backup, Hibernate, Standby, Idle.

Definition at line 57 of file periph_cpu.h.

◆ RTT_CLOCK_FREQUENCY

#define RTT_CLOCK_FREQUENCY   (32768U) /* in Hz */

Definition at line 194 of file periph_cpu.h.

◆ RTT_MAX_FREQUENCY

#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY) /* in Hz */

Definition at line 196 of file periph_cpu.h.

◆ RTT_MAX_VALUE

#define RTT_MAX_VALUE   (0xffffffff)

Definition at line 193 of file periph_cpu.h.

◆ RTT_MIN_FREQUENCY

#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */

Definition at line 195 of file periph_cpu.h.

◆ SAM0_DFLL_FREQ_HZ

#define SAM0_DFLL_FREQ_HZ   MHZ(48)

DFLL runs at at fixed frequency of 48 MHz.

Definition at line 36 of file periph_cpu.h.

◆ SAM0_DPLL_FREQ_MAX_HZ

#define SAM0_DPLL_FREQ_MAX_HZ   MHZ(200)

DPLL frequency must not exceed 200 MHz.

Definition at line 51 of file periph_cpu.h.

◆ SAM0_DPLL_FREQ_MIN_HZ

#define SAM0_DPLL_FREQ_MIN_HZ   MHZ(96)

DPLL must run with at least 96 MHz.

Definition at line 46 of file periph_cpu.h.

◆ SAM0_GCLK_100MHZ

#define SAM0_GCLK_100MHZ   4

100MHz FDPLL clock

Definition at line 85 of file periph_cpu.h.

◆ SAM0_GCLK_32KHZ

#define SAM0_GCLK_32KHZ   1

32 kHz clock

Definition at line 76 of file periph_cpu.h.

◆ SAM0_GCLK_48MHZ

#define SAM0_GCLK_48MHZ   SAM0_GCLK_PERIPH

Definition at line 94 of file periph_cpu.h.

◆ SAM0_GCLK_8MHZ

#define SAM0_GCLK_8MHZ   SAM0_GCLK_TIMER

Definition at line 93 of file periph_cpu.h.

◆ SAM0_GCLK_MAIN

#define SAM0_GCLK_MAIN   0

120 MHz main clock

Definition at line 74 of file periph_cpu.h.

◆ SAM0_GCLK_PERIPH

#define SAM0_GCLK_PERIPH   3

12-48 MHz (DFLL) clock

Definition at line 82 of file periph_cpu.h.

◆ SAM0_GCLK_TIMER

#define SAM0_GCLK_TIMER   2

4-8 MHz clock for xTimer

Definition at line 79 of file periph_cpu.h.

◆ SAM0_QSPI_MUX

#define SAM0_QSPI_MUX   GPIO_MUX_H

QSPI mux

Definition at line 275 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_CLK

#define SAM0_QSPI_PIN_CLK   GPIO_PIN(PB, 10)

Clock

Definition at line 269 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_CS

#define SAM0_QSPI_PIN_CS   GPIO_PIN(PB, 11)

Chip Select

Definition at line 270 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_DATA_0

#define SAM0_QSPI_PIN_DATA_0   GPIO_PIN(PA, 8)

D0 / MOSI

Definition at line 271 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_DATA_1

#define SAM0_QSPI_PIN_DATA_1   GPIO_PIN(PA, 9)

D1 / MISO

Definition at line 272 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_DATA_2

#define SAM0_QSPI_PIN_DATA_2   GPIO_PIN(PA, 10)

D2 / WP

Definition at line 273 of file periph_cpu.h.

◆ SAM0_QSPI_PIN_DATA_3

#define SAM0_QSPI_PIN_DATA_3   GPIO_PIN(PA, 11)

D3 / HOLD

Definition at line 274 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDCK

#define SAM0_SDHC0_PIN_SDCK   GPIO_PIN(PB, 11)

Clock

Definition at line 289 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDCMD

#define SAM0_SDHC0_PIN_SDCMD   GPIO_PIN(PA, 8)

Command

Definition at line 284 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDDAT0

#define SAM0_SDHC0_PIN_SDDAT0   GPIO_PIN(PA, 9)

DATA0

Definition at line 285 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDDAT1

#define SAM0_SDHC0_PIN_SDDAT1   GPIO_PIN(PA, 10)

DATA1

Definition at line 286 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDDAT2

#define SAM0_SDHC0_PIN_SDDAT2   GPIO_PIN(PA, 11)

DATA2

Definition at line 287 of file periph_cpu.h.

◆ SAM0_SDHC0_PIN_SDDAT3

#define SAM0_SDHC0_PIN_SDDAT3   GPIO_PIN(PB, 10)

DATA3

Definition at line 288 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDCK

#define SAM0_SDHC1_PIN_SDCK   GPIO_PIN(PA, 21)

Clock

Definition at line 296 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDCMD

#define SAM0_SDHC1_PIN_SDCMD   GPIO_PIN(PA, 20)

Command

Definition at line 291 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDDAT0

#define SAM0_SDHC1_PIN_SDDAT0   GPIO_PIN(PB, 18)

DATA0

Definition at line 292 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDDAT1

#define SAM0_SDHC1_PIN_SDDAT1   GPIO_PIN(PB, 19)

DATA1

Definition at line 293 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDDAT2

#define SAM0_SDHC1_PIN_SDDAT2   GPIO_PIN(PB, 20)

DATA2

Definition at line 294 of file periph_cpu.h.

◆ SAM0_SDHC1_PIN_SDDAT3

#define SAM0_SDHC1_PIN_SDDAT3   GPIO_PIN(PB, 21)

DATA3

Definition at line 295 of file periph_cpu.h.

◆ SAM0_SDHC_MUX

#define SAM0_SDHC_MUX   GPIO_MUX_I

SDHC function

Definition at line 282 of file periph_cpu.h.

◆ SAM0_XOSC_FREQ_HZ

#define SAM0_XOSC_FREQ_HZ   (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)

 *

XOSC is used to generate a fixed frequency of 48 MHz 

Definition at line 41 of file periph_cpu.h.

◆ SPI_HWCS

#define SPI_HWCS (   x)    (UINT_MAX - 1)

Override SPI hardware chip select macro.

As of now, we do not support HW CS, so we always set it to a fixed value

Definition at line 102 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Power modes.

Definition at line 62 of file periph_cpu.h.

Variable Documentation

◆ gclk_io_ids

const uint8_t gclk_io_ids[]
static
Initial value:
= {
4, 5, 0, 1, 2, 3, 1, 0, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1
}

GCLK IDs of pins that have peripheral function GCLK - This maps directly to gclk_io_pins.

Definition at line 226 of file periph_cpu.h.

◆ gclk_io_pins

const gpio_t gclk_io_pins[]
static
Initial value:
= {
GPIO_PIN(PA, 10), GPIO_PIN(PA, 11), GPIO_PIN(PA, 14),
GPIO_PIN(PA, 15), GPIO_PIN(PA, 16), GPIO_PIN(PA, 17),
GPIO_PIN(PA, 27), GPIO_PIN(PA, 30), GPIO_PIN(PB, 10),
GPIO_PIN(PB, 11), GPIO_PIN(PB, 12), GPIO_PIN(PB, 13),
GPIO_PIN(PB, 14), GPIO_PIN(PB, 15), GPIO_PIN(PB, 16),
GPIO_PIN(PB, 17), GPIO_PIN(PB, 18), GPIO_PIN(PB, 19),
GPIO_PIN(PB, 20), GPIO_PIN(PB, 21), GPIO_PIN(PB, 22),
}
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
PB
@ PB
port B
Definition periph_cpu_common.h:100
PA
@ PA
port A
Definition periph_cpu_common.h:99

Pins that have peripheral function GCLK.

Definition at line 211 of file periph_cpu.h.

◆ rtc_tamper_pins

const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS]
static
Initial value:
= {
GPIO_PIN(PB, 0), GPIO_PIN(PB, 2), GPIO_PIN(PA, 2),
GPIO_PIN(PC, 0), GPIO_PIN(PC, 1)
}
PC
@ PC
port C
Definition periph_cpu_common.h:101

RTC input pins that can be used for tamper detection and wake from Deep Sleep.

Definition at line 203 of file periph_cpu.h.

◆ sam0_adc_pins

const gpio_t sam0_adc_pins[2][16]
static
Initial value:
= {
{
GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8), GPIO_PIN(PB, 9),
GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6), GPIO_PIN(PA, 7),
GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2), GPIO_PIN(PB, 3)
},
{
GPIO_PIN(PB, 8), GPIO_PIN(PB, 9), GPIO_PIN(PA, 8), GPIO_PIN(PA, 9),
GPIO_PIN(PC, 2), GPIO_PIN(PC, 3), GPIO_PIN(PB, 4), GPIO_PIN(PB, 5),
GPIO_PIN(PB, 6), GPIO_PIN(PB, 7), GPIO_PIN(PC, 0), GPIO_PIN(PC, 1),
GPIO_PIN(PC, 30), GPIO_PIN(PC, 31), GPIO_PIN(PD, 0), GPIO_PIN(PD, 1)
}
}
PD
@ PD
port D
Definition periph_cpu_common.h:102

Pins that can be used for ADC input.

Definition at line 107 of file periph_cpu.h.