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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Ken Rabold
3 * SPDX-FileCopyrightText: 2019 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
18
19#include "periph_cpu.h"
20#include "clk_conf.h"
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
31#define TIMER_NUMOF (1)
33
38static const uart_conf_t uart_config[] = {
39 {
40 .addr = UART0_CTRL_ADDR,
41 .rx = GPIO_PIN(0, 16),
42 .tx = GPIO_PIN(0, 17),
43 .isr_num = INT_UART0_BASE,
44 },
45 {
46 .addr = UART1_CTRL_ADDR,
47 .rx = GPIO_PIN(0, 18),
48 .tx = GPIO_PIN(0, 23),
49 .isr_num = INT_UART1_BASE,
50 },
51};
52
53#define UART_NUMOF ARRAY_SIZE(uart_config)
55
61static const spi_conf_t spi_config[] = {
62 {
63 .addr = SPI1_CTRL_ADDR,
64 .mosi = GPIO_PIN(0, 3), /* D11 */
65 .miso = GPIO_PIN(0, 4), /* D12 */
66 .sclk = GPIO_PIN(0, 5), /* D13 */
67 },
68};
69
70#define SPI_NUMOF ARRAY_SIZE(spi_config)
72
78#define PWM_NUMOF (3)
80
81#ifdef __cplusplus
82}
83#endif
84
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217