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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2014 INRIA
3 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include "periph_cpu.h"
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#define CLOCK_CORECLOCK (7372800U)
28
33 .xt2_frequency = CLOCK_CORECLOCK,
34 .lfxt1_frequency = 32768,
35 .main_clock_source = MAIN_CLOCK_SOURCE_XT2CLK,
36 .submain_clock_source = SUBMAIN_CLOCK_SOURCE_XT2CLK,
37 .main_clock_divier = MAIN_CLOCK_DIVIDE_BY_1,
38 .submain_clock_divier = SUBMAIN_CLOCK_DIVIDE_BY_1,
39 .auxiliary_clock_divier = AUXILIARY_CLOCK_DIVIDE_BY_1,
40 .has_r_osc = true,
41};
42
47static const uart_conf_t uart_config[] = {
48 {
49 .uart = &usart1_as_uart,
50 },
51};
52
53#define UART0_RX_ISR (USART1RX_VECTOR)
54#define UART0_TX_ISR (USART1TX_VECTOR)
55
56#define UART_NUMOF ARRAY_SIZE(uart_config)
58
63static const spi_conf_t spi_config[] = {
64 {
65 .spi = &usart0_as_spi,
66 },
67};
68
69#define SPI_NUMOF ARRAY_SIZE(spi_config)
71
72#ifdef __cplusplus
73}
74#endif
75
#define CLOCK_CORECLOCK
Clock configuration.
Definition periph_cpu.h:31
static const msp430_clock_params_t clock_params
Clock configuration.
Definition periph_conf.h:33
Common timer configuration for TIMER_A clocked by SMCLK and TIMER_B clocked by ACLK.
@ MAIN_CLOCK_SOURCE_XT2CLK
High frequency crystal between 450 kHz and 8 MHz.
@ SUBMAIN_CLOCK_SOURCE_XT2CLK
High frequency crystal between 450 kHz and 8 MHz.
@ SUBMAIN_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
@ AUXILIARY_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
@ MAIN_CLOCK_DIVIDE_BY_1
Divide the main clock by 1.
const msp430_usart_uart_params_t usart1_as_uart
MSP430 x1xx USART1 in UART configuration.
const msp430_usart_spi_params_t usart0_as_spi
MSP430 x1xx USART0 in SPI configuration.
MSP430Fxzy Basic Clock System Parameters.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217