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cfg_clock_16_1.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19
20#ifdef __cplusplus
21 extern "C" {
22#endif
23
31#define CLOCK_HFCLK (16U) /* set to 0: internal RC oscillator
32 16: 16MHz crystal
33 32: 32MHz crystal */
34/* LFCLK Source clock selection:*/
35/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
36 * - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
37 * - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
38#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_Xtal)
40
41#ifdef __cplusplus
42} /* end extern "C" */
43#endif
44