clock_conf.h

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/*
 * SPDX-FileCopyrightText: 2025 Tom Hert <git@annsann.eu>
 * SPDX-FileCopyrightText: 2025 HAW Hamburg
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include <stdint.h>
#include "macros/units.h"

#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0u
#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ 0xaa1u
#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ 0xaa2u
#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ 0xaa3u
#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1eu
#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfabu
#define XOSC_CTRL_ENABLE_LSB 12u
#define XOSC_STATUS_STABLE_BITS 0x80000000u
#define XOSC_HZ MHZ(12u)
#define PLL_REF_DIV 1u
#define PLL_VCO_FREQ ((XOSC_HZ / PLL_REF_DIV) * PLL_FEEDBACK_DIVIDER_VALUE)
#define PLL_PD1 6u
#define PLL_PD2 2u
#define PLL_PWR_PD_BITS 0x00000001u
#define PLL_PWR_VCOPD_BITS 0x00000020u
#define PLL_CS_LOCK_BITS 0x80000000u
#define PLL_PRIM_POSTDIV1_LSB 16u
#define PLL_PRIM_POSTDIV2_LSB 12u
#define PLL_PWR_POSTDIVPD_BITS 0x00000008u
#define CLK_PERI_CTRL_ENABLE_BIT (1u << 11u)
#define CPUFREQ CLOCK_CORECLOCK
#define CLOCK_XOSC_MAX MHZ(15u)
#define CLOCK_XOSC_MIN MHZ(5u)
#define CLOCK_XOSC (XOSC_HZ)
#define PLL_POSTDIV_MIN 1u
#define PLL_POSTDIV_MAX 7u
#define PLL_VCO_FEEDBACK_SCALE_MIN 16u
#define PLL_VCO_FEEDBACK_SCALE_MAX 320u
#define PLL_REF_DIV_MIN 1u
#define PLL_REF_DIV_MAX 63u
#define PLL_FEEDBACK_DIVIDER_VALUE 125u
#define CLK_SYS_PERI_CTRL_ENABLE_BIT (1u << 0u)
#define CLK_SYS_SELECTED_PERI_FIELD_VALUE 2u
#define PLL_VCO_FREQ_MIN MHZ(750u)
#define PLL_VCO_FREQ_MAX MHZ(1600u)
#define CLOCK_CORECLOCK (PLL_VCO_FREQ / (PLL_PD1 * PLL_PD2))
#define CLK_REF_DIV_VALUE 1u
#define CLOCK_REF (CLOCK_XOSC / CLK_REF_DIV_VALUE)
#define TICK_CYCLES (CLOCK_REF / MHZ(1u))
 
#if (PLL_FEEDBACK_DIVIDER_VALUE < PLL_VCO_FEEDBACK_SCALE_MIN) || \
    (PLL_FEEDBACK_DIVIDER_VALUE > PLL_VCO_FEEDBACK_SCALE_MAX)
#  error "Value for PLL_FEEDBACK_DIVIDER_VALUE out of range, check config"
#endif
#if (PLL_REF_DIV < PLL_REF_DIV_MIN) || (PLL_REF_DIV > PLL_REF_DIV_MAX)
#  error "Value for PLL_REF_DIV out of range, check config"
#endif
#if (PLL_PD1 < PLL_POSTDIV_MIN) || (PLL_PD1 > PLL_POSTDIV_MAX)
#  error "Value for PLL_PD1 out of range, check config"
#endif
#if (PLL_PD2 < PLL_POSTDIV_MIN) || (PLL_PD2 > PLL_POSTDIV_MAX)
#  error "Value for PLL_PD2 out of range, check config"
#endif
#if ((CLOCK_XOSC > CLOCK_XOSC_MAX) || (CLOCK_XOSC < CLOCK_XOSC_MIN))
#  error "Value for CLOCK_XOSC out of range, check config"
#endif
#if ((PLL_VCO_FREQ > PLL_VCO_FREQ_MAX) || (PLL_VCO_FREQ < PLL_VCO_FREQ_MIN))
#  error "Value for PLL_VCO_FREQ out of range, check config"
#endif
#if (CLOCK_REF % MHZ(1u))
#  error "CLOCK_REF must be a multiple of 1 MHz for 1 µs ticks"
#endif

#define PDIV ((PLL_PD1 << PLL_PRIM_POSTDIV1_LSB) | (PLL_PD2 << PLL_PRIM_POSTDIV2_LSB))
 
#ifdef __cplusplus
extern "C" {
#endif

void xosc_start(void);

void xosc_stop(void);

void xosc_sleep(uint32_t milliseconds);

void clock_reset(void);

void cpu_clock_init(void);
 
#ifdef __cplusplus
}
#endif