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context_frame.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2017, 2019 JP Bonn, Ken Rabold
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#if !defined(__ASSEMBLER__)
19#include <stdint.h>
20#endif /* __ASSEMBLER__ */
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#if !defined(__ASSEMBLER__)
27
37 /* Callee saved registers */
38 uint32_t s0;
39 uint32_t s1;
40 uint32_t s2;
41 uint32_t s3;
42 uint32_t s4;
43 uint32_t s5;
44 uint32_t s6;
45 uint32_t s7;
46 uint32_t s8;
47 uint32_t s9;
48 uint32_t s10;
49 uint32_t s11;
50 /* Caller saved registers */
51 uint32_t ra;
52 uint32_t t0;
53 uint32_t t1;
54 uint32_t t2;
55 uint32_t t3;
56 uint32_t t4;
57 uint32_t t5;
58 uint32_t t6;
59 uint32_t a0;
60 uint32_t a1;
61 uint32_t a2;
62 uint32_t a3;
63 uint32_t a4;
64 uint32_t a5;
65 uint32_t a6;
66 uint32_t a7;
67 /* Saved PC for return from ISR */
68 uint32_t pc;
69 uint32_t pad[3];
70};
71
72#endif /* __ASSEMBLER__ */
73
78/* These values are checked for correctness in context_frame.c */
79#define s0_OFFSET 0
80#define s1_OFFSET 4
81#define s2_OFFSET 8
82#define s3_OFFSET 12
83#define s4_OFFSET 16
84#define s5_OFFSET 20
85#define s6_OFFSET 24
86#define s7_OFFSET 28
87#define s8_OFFSET 32
88#define s9_OFFSET 36
89#define s10_OFFSET 40
90#define s11_OFFSET 44
91#define ra_OFFSET 48
92#define t0_OFFSET 52
93#define t1_OFFSET 56
94#define t2_OFFSET 60
95#define t3_OFFSET 64
96#define t4_OFFSET 68
97#define t5_OFFSET 72
98#define t6_OFFSET 76
99#define a0_OFFSET 80
100#define a1_OFFSET 84
101#define a2_OFFSET 88
102#define a3_OFFSET 92
103#define a4_OFFSET 96
104#define a5_OFFSET 100
105#define a6_OFFSET 104
106#define a7_OFFSET 108
107#define pc_OFFSET 112
108#define pad_OFFSET 116
110
114#define CONTEXT_FRAME_SIZE (pad_OFFSET + 12)
115
119#define SP_OFFSET_IN_THREAD 0
120
121#ifdef __cplusplus
122}
123#endif
124
Stores the registers and PC for a context switch.
uint32_t s9
s9 register
uint32_t s6
s6 register
uint32_t t6
t6 register
uint32_t a2
a2 register
uint32_t s5
s5 register
uint32_t s1
s1 register
uint32_t s11
s11 register
uint32_t s2
s2 register
uint32_t t5
t5 register
uint32_t a0
a0 register
uint32_t a3
a3 register
uint32_t s3
s3 register
uint32_t s7
s7 register
uint32_t t0
t0 register
uint32_t pc
program counter
uint32_t t4
t4 register
uint32_t t2
t2 register
uint32_t ra
ra register
uint32_t a6
a6 register
uint32_t s0
s0 register
uint32_t a5
a5 register
uint32_t a4
a4 register
uint32_t a7
a7 register
uint32_t s10
s10 register
uint32_t t3
t3 register
uint32_t pad[3]
padding to maintain 16 byte alignment
uint32_t s8
s8 register
uint32_t s4
s4 register
uint32_t a1
a1 register
uint32_t t1
t1 register