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context_frame.h
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1/*
2 * SPDX-FileCopyrightText: 2017, 2019 JP Bonn, Ken Rabold
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#if !defined(__ASSEMBLER__)
19#include <stdint.h>
20#endif /* __ASSEMBLER__ */
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#define REGSZ (__riscv_xlen / 8)
27
28#if __riscv_xlen == 64
32# define REG_L ld
36# define REG_S sd
37#else
41# define REG_L lw
45# define REG_S sw
46#endif
47
48#if !defined(__ASSEMBLER__)
49
59 /* Callee saved registers */
60 uintptr_t s0;
61 uintptr_t s1;
62 uintptr_t s2;
63 uintptr_t s3;
64 uintptr_t s4;
65 uintptr_t s5;
66 uintptr_t s6;
67 uintptr_t s7;
68 uintptr_t s8;
69 uintptr_t s9;
70 uintptr_t s10;
71 uintptr_t s11;
72 /* Caller saved registers */
73 uintptr_t ra;
74 uintptr_t t0;
75 uintptr_t t1;
76 uintptr_t t2;
77 uintptr_t t3;
78 uintptr_t t4;
79 uintptr_t t5;
80 uintptr_t t6;
81 uintptr_t a0;
82 uintptr_t a1;
83 uintptr_t a2;
84 uintptr_t a3;
85 uintptr_t a4;
86 uintptr_t a5;
87 uintptr_t a6;
88 uintptr_t a7;
89 /* Saved PC for return from ISR */
90 uintptr_t pc;
91 uintptr_t pad[3];
92};
93
94#endif /* __ASSEMBLER__ */
95
100/* These values are checked for correctness in context_frame.c */
101#define s0_OFFSET (0 * REGSZ)
102#define s1_OFFSET (1 * REGSZ)
103#define s2_OFFSET (2 * REGSZ)
104#define s3_OFFSET (3 * REGSZ)
105#define s4_OFFSET (4 * REGSZ)
106#define s5_OFFSET (5 * REGSZ)
107#define s6_OFFSET (6 * REGSZ)
108#define s7_OFFSET (7 * REGSZ)
109#define s8_OFFSET (8 * REGSZ)
110#define s9_OFFSET (9 * REGSZ)
111#define s10_OFFSET (10 * REGSZ)
112#define s11_OFFSET (11 * REGSZ)
113#define ra_OFFSET (12 * REGSZ)
114#define t0_OFFSET (13 * REGSZ)
115#define t1_OFFSET (14 * REGSZ)
116#define t2_OFFSET (15 * REGSZ)
117#define t3_OFFSET (16 * REGSZ)
118#define t4_OFFSET (17 * REGSZ)
119#define t5_OFFSET (18 * REGSZ)
120#define t6_OFFSET (19 * REGSZ)
121#define a0_OFFSET (20 * REGSZ)
122#define a1_OFFSET (21 * REGSZ)
123#define a2_OFFSET (22 * REGSZ)
124#define a3_OFFSET (23 * REGSZ)
125#define a4_OFFSET (24 * REGSZ)
126#define a5_OFFSET (25 * REGSZ)
127#define a6_OFFSET (26 * REGSZ)
128#define a7_OFFSET (27 * REGSZ)
129#define pc_OFFSET (28 * REGSZ)
130#define pad_OFFSET (29 * REGSZ)
132
136#define CONTEXT_FRAME_SIZE (pad_OFFSET + 3 * REGSZ)
137
141#define SP_OFFSET_IN_THREAD 0
142
143#ifdef __cplusplus
144}
145#endif
146
Stores the registers and PC for a context switch.
uintptr_t ra
ra register
uintptr_t t2
t2 register
uintptr_t s2
s2 register
uintptr_t s3
s3 register
uintptr_t s10
s10 register
uintptr_t s5
s5 register
uintptr_t s7
s7 register
uintptr_t a6
a6 register
uintptr_t t1
t1 register
uintptr_t a7
a7 register
uintptr_t t5
t5 register
uintptr_t s1
s1 register
uintptr_t t0
t0 register
uintptr_t a4
a4 register
uintptr_t a5
a5 register
uintptr_t s11
s11 register
uintptr_t pad[3]
padding to maintain 16 byte alignment
uintptr_t a2
a2 register
uintptr_t s6
s6 register
uintptr_t a3
a3 register
uintptr_t a0
a0 register
uintptr_t a1
a1 register
uintptr_t t4
t4 register
uintptr_t t6
t6 register
uintptr_t s4
s4 register
uintptr_t s8
s8 register
uintptr_t t3
t3 register
uintptr_t s9
s9 register
uintptr_t s0
s0 register
uintptr_t pc
program counter