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cpu_conf_kinetis_k.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Eistec AB
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
19
20#if (KINETIS_FAMILY == 2)
21#if (KINETIS_SUBFAMILY == 2)
22/* Kinetis K22 */
23#if defined(CPU_MODEL_MK22FX512VLH12) || \
24 defined(CPU_MODEL_MK22FN1M0VLH12) || \
25 defined(CPU_MODEL_MK22FX512VLK12) || \
26 defined(CPU_MODEL_MK22FN1M0VLK12) || \
27 defined(CPU_MODEL_MK22FX512VLL12) || \
28 defined(CPU_MODEL_MK22FN1M0VLL12) || \
29 defined(CPU_MODEL_MK22FX512VLQ12) || \
30 defined(CPU_MODEL_MK22FN1M0VLQ12) || \
31 defined(CPU_MODEL_MK22FX512VMC12) || \
32 defined(CPU_MODEL_MK22FN1M0VMC12) || \
33 defined(CPU_MODEL_MK22FX512VMD12) || \
34 defined(CPU_MODEL_MK22FN1M0VMD12)
35#include "vendor/MK22F12.h"
36#elif defined(CPU_MODEL_MK22FN128VDC10) || \
37 defined(CPU_MODEL_MK22FN128VLH10) || \
38 defined(CPU_MODEL_MK22FN128VLL10) || \
39 defined(CPU_MODEL_MK22FN128VMP10)
40#include "vendor/MK22F12810.h"
41#elif defined(CPU_MODEL_MK22FN128CAH12) || \
42 defined(CPU_MODEL_MK22FN256CAH12) || \
43 defined(CPU_MODEL_MK22FN256VDC12) || \
44 defined(CPU_MODEL_MK22FN256VLH12) || \
45 defined(CPU_MODEL_MK22FN256VLL12) || \
46 defined(CPU_MODEL_MK22FN256VMP12)
47#include "vendor/MK22F25612.h"
48#elif defined(CPU_MODEL_MK22FN512CAP12) || \
49 defined(CPU_MODEL_MK22FN512VDC12) || \
50 defined(CPU_MODEL_MK22FN512VFX12) || \
51 defined(CPU_MODEL_MK22FN512VLH12) || \
52 defined(CPU_MODEL_MK22FN512VLL12) || \
53 defined(CPU_MODEL_MK22FN512VMP12)
54#include "vendor/MK22F51212.h"
55#elif defined(CPU_MODEL_MK22FN1M0AVLH12) || \
56 defined(CPU_MODEL_MK22FN1M0AVLK12) || \
57 defined(CPU_MODEL_MK22FN1M0AVLL12) || \
58 defined(CPU_MODEL_MK22FN1M0AVLQ12) || \
59 defined(CPU_MODEL_MK22FN1M0AVMC12) || \
60 defined(CPU_MODEL_MK22FN1M0AVMD12) || \
61 defined(CPU_MODEL_MK22FX512AVLH12) || \
62 defined(CPU_MODEL_MK22FX512AVLK12) || \
63 defined(CPU_MODEL_MK22FX512AVLL12) || \
64 defined(CPU_MODEL_MK22FX512AVLQ12) || \
65 defined(CPU_MODEL_MK22FX512AVMC12) || \
66 defined(CPU_MODEL_MK22FX512AVMD12)
67#include "vendor/MK22FA12.h"
68#endif
69#elif (KINETIS_SUBFAMILY == 0)
70#if defined(CPU_MODEL_MK20DX64VLH7) || \
71 defined(CPU_MODEL_MK20DX128VLH7) || \
72 defined(CPU_MODEL_MK20DX256VLH7) || \
73 defined(CPU_MODEL_MK20DX64VLK7) || \
74 defined(CPU_MODEL_MK20DX128VLK7) || \
75 defined(CPU_MODEL_MK20DX256VLK7) || \
76 defined(CPU_MODEL_MK20DX128VLL7) || \
77 defined(CPU_MODEL_MK20DX256VLL7) || \
78 defined(CPU_MODEL_MK20DX64VMB7) || \
79 defined(CPU_MODEL_MK20DX128VMB7) || \
80 defined(CPU_MODEL_MK20DX256VMB7) || \
81 defined(CPU_MODEL_MK20DX128VML7) || \
82 defined(CPU_MODEL_MK20DX256VML7)
83#include "vendor/MK20D7.h"
84#endif
85#endif /* (KINETIS_SUBFAMILY == y) */
86#elif (KINETIS_FAMILY == 6)
87#if (KINETIS_SUBFAMILY == 0)
88#if defined(CPU_MODEL_MK60DN256VLL10) || \
89 defined(CPU_MODEL_MK60DN256VLQ10) || \
90 defined(CPU_MODEL_MK60DN256VMC10) || \
91 defined(CPU_MODEL_MK60DN256VMD10) || \
92 defined(CPU_MODEL_MK60DN512VLL10) || \
93 defined(CPU_MODEL_MK60DN512VLQ10) || \
94 defined(CPU_MODEL_MK60DN512VMC10) || \
95 defined(CPU_MODEL_MK60DN512VMD10) || \
96 defined(CPU_MODEL_MK60DX256VLL10) || \
97 defined(CPU_MODEL_MK60DX256VLQ10) || \
98 defined(CPU_MODEL_MK60DX256VMC10) || \
99 defined(CPU_MODEL_MK60DX256VMD10)
100#include "vendor/MK60D10.h"
101#endif
105#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
106
107#elif (KINETIS_SUBFAMILY == 4)
108#if defined(CPU_MODEL_MK64FN1M0CAJ12) || \
109 defined(CPU_MODEL_MK64FN1M0VDC12) || \
110 defined(CPU_MODEL_MK64FN1M0VLL12) || \
111 defined(CPU_MODEL_MK64FN1M0VLQ12) || \
112 defined(CPU_MODEL_MK64FN1M0VMD12) || \
113 defined(CPU_MODEL_MK64FX512VDC12) || \
114 defined(CPU_MODEL_MK64FX512VLL12) || \
115 defined(CPU_MODEL_MK64FX512VLQ12) || \
116 defined(CPU_MODEL_MK64FX512VMD12)
117#include "vendor/MK64F12.h"
118
127#define HWRNG_CLK_REG (SIM->SCGC6)
128#define HWRNG_CLK_REG_SHIFT (SIM_SCGC6_RNGA_SHIFT)
130
131#endif
132#endif /* (KINETIS_SUBFAMILY == y) */
133#endif /* (KINETIS_FAMILY == x) */
134
139#define FLASHPAGE_SIZE (4096U)
140#define FLASHPAGE_NUMOF ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)
141
142/* The minimum block size which can be written is 8B (Phrase). However, the
143 * erase block is always FLASHPAGE_SIZE.
144 */
145#define FLASHPAGE_BLOCK_PHRASE (8U)
146#define FLASHPAGE_WRITE_BLOCK_SIZE FLASHPAGE_BLOCK_PHRASE
147/* Writing should be always 8 bytes aligned */
148#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT FLASHPAGE_BLOCK_PHRASE
149/* Section erase and programming must be 16 bytes aligned */
150#define FLASHPAGE_BLOCK_SECTION_ALIGNMENT (16U)
152
153#ifdef __cplusplus
154extern "C"
155{
156#endif
157
158#ifdef __cplusplus
159}
160#endif
161