21#ifndef PERIPH_CPU_ETH_H
22#define PERIPH_CPU_ETH_H
89#define RX_DESC_STAT_LS (BIT8)
90#define RX_DESC_STAT_FS (BIT9)
97#define RX_DESC_STAT_FL (0x3FFF0000)
98#define RX_DESC_STAT_DE (BIT14)
99#define RX_DESC_STAT_ES (BIT15)
100#define RX_DESC_STAT_OWN (BIT31)
113#define RX_DESC_CTRL_RCH (BIT14)
119#define TX_DESC_STAT_UF (BIT1)
120#define TX_DESC_STAT_EC (BIT8)
121#define TX_DESC_STAT_NC (BIT10)
122#define TX_DESC_STAT_ES (BIT15)
123#define TX_DESC_STAT_TTSS (BIT17)
131#define TX_DESC_STAT_TCH (BIT20)
132#define TX_DESC_STAT_TER (BIT21)
143#define TX_DESC_STAT_CIC (BIT22 | BIT23)
144#define TX_DESC_STAT_CIC_NO_HW_CHECKSUM (0)
145#define TX_DESC_STAT_CIC_HW_CHECKSUM_IPV4 (BIT22)
146#define TX_DESC_STAT_CIC_HW_CHECKSUM_BOTH (BIT22 | BIT32)
148#define TX_DESC_STAT_TTSE (BIT25)
149#define TX_DESC_STAT_FS (BIT28)
150#define TX_DESC_STAT_LS (BIT29)
151#define TX_DESC_STAT_IC (BIT30)
152#define TX_DESC_STAT_OWN (BIT31)
155#ifdef MODULE_PERIPH_ETH_COMMON
160void stm32_eth_common_init(
void);
eth_mode_t
STM32 Ethernet configuration mode.
@ SMI
Configuration for SMI.
@ MII
Configuration for MII.
@ RMII
Configuration for RMII.
struct eth_dma_desc edma_desc_t
Layout of enhanced RX/TX DMA descriptor.
GPIO CPU definitions for the STM32 family.
Ethernet Peripheral configuration.
uint8_t dma_chan
DMA channel used for TX.
uint8_t dma
Locical CMA Descriptor used for TX.
uint8_t phy_addr
PHY address.
eth_mode_t mode
Select configuration mode.
uint16_t speed
Speed selection.
Layout of enhanced RX/TX DMA descriptor.
volatile uint32_t reserved1_ext
RX: Extended status, TX: reserved.
volatile uint32_t ts_low
Sub-second part of PTP timestamp of transmitted / sent frame.
volatile uint32_t reserved2
Reserved for future use.
char *volatile buffer_addr
RX/TX buffer.
volatile uint32_t control
Control bits.
volatile uint32_t status
Mostly status bits, some control bits.
struct eth_dma_desc *volatile desc_next
Address of next DMA descriptor.
volatile uint32_t ts_high
Second part of PTP timestamp.