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enc28j60_regs.h
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1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
29#define CMD_RCR 0x00 /* read control register */
30#define CMD_RBM 0x3a /* read buffer memory */
31#define CMD_WCR 0x40 /* write control register */
32#define CMD_WBM 0x7a /* write buffer memory */
33#define CMD_BFS 0x80 /* bit field set */
34#define CMD_BFC 0xa0 /* bit field clear */
35#define CMD_SRC 0xff /* system reset command (soft reset) */
37
42#define ADDR_READ_PTR 0x00
43#define ADDR_WRITE_PTR 0x02
44#define ADDR_TX_START 0x04
45#define ADDR_TX_END 0x06
46#define ADDR_RX_START 0x08
47#define ADDR_RX_END 0x0a
48#define ADDR_RX_READ 0x0c
49#define ADDR_RX_WRITE 0x0e
51
56#define REG_EIE 0x1b
57#define REG_EIR 0x1c
58#define REG_ESTAT 0x1d
59#define REG_ECON2 0x1e
60#define REG_ECON1 0x1f
62
67#define REG_B0_ERDPTL 0x00 /* read data pointer - low byte */
68#define REG_B0_ERDPTH 0x01 /* read data pointer - high byte */
69#define REG_B0_EWRPTL 0x02 /* write data pointer - low byte */
70#define REG_B0_EWRPTH 0x03 /* write data pointer - high byte */
71#define REG_B0_ETXSTL 0x04 /* TX start pointer - low byte */
72#define REG_B0_ETXSTH 0x05 /* TX start pointer - high byte */
73#define REG_B0_ETXNDL 0x06 /* TX end pointer - low byte */
74#define REG_B0_ETXNDH 0x07 /* TX end pointer - high byte */
75#define REG_B0_ERXSTL 0x08 /* RX start pointer - low byte */
76#define REG_B0_ERXSTH 0x09 /* RX start pointer - high byte */
77#define REG_B0_ERXNDL 0x0a /* RX end pointer - low byte */
78#define REG_B0_ERXNDH 0x0b /* RX end pointer - high byte */
79#define REG_B0_ERXRDPTL 0x0c /* RX read pointer - low byte */
80#define REG_B0_ERXRDPTH 0x0d /* RX read pointer - high byte */
81#define REG_B0_ERXWRPTL 0x0e /* RX write pointer - low byte */
82#define REG_B0_ERXWRPTH 0x0f /* RX write pointer - high byte */
83#define REG_B0_EDMASTL 0x10 /* DMA start pointer - low byte */
84#define REG_B0_EDMASTH 0x11 /* DMA start pointer - high byte */
85#define REG_B0_EDMANDL 0x12 /* DMA end pointer - low byte */
86#define REG_B0_EDMANDH 0x13 /* DMA end pointer - high byte */
87#define REG_B0_EDMADSTL 0x14 /* DMA destination pointer - low byte */
88#define REG_B0_EDMADSTH 0x15 /* DMA destination pointer - high byte */
89#define REG_B0_EDMACSL 0x16 /* DMA checksum - low byte */
90#define REG_B0_EDMACSH 0x17 /* DMA checksum - high byte */
92
97#define REG_B1_EHT0 0x00 /* hash table - byte 0 */
98#define REG_B1_EHT1 0x01 /* hash table - byte 1 */
99#define REG_B1_EHT2 0x02 /* hash table - byte 2 */
100#define REG_B1_EHT3 0x03 /* hash table - byte 3 */
101#define REG_B1_EHT4 0x04 /* hash table - byte 4 */
102#define REG_B1_EHT5 0x05 /* hash table - byte 5 */
103#define REG_B1_EHT6 0x06 /* hash table - byte 6 */
104#define REG_B1_EHT7 0x07 /* hash table - byte 7 */
105#define REG_B1_EPMM0 0x08 /* pattern match mask - byte 0 */
106#define REG_B1_EPMM1 0x09 /* pattern match mask - byte 1 */
107#define REG_B1_EPMM2 0x0a /* pattern match mask - byte 2 */
108#define REG_B1_EPMM3 0x0b /* pattern match mask - byte 3 */
109#define REG_B1_EPMM4 0x0c /* pattern match mask - byte 4 */
110#define REG_B1_EPMM5 0x0d /* pattern match mask - byte 5 */
111#define REG_B1_EPMM6 0x0e /* pattern match mask - byte 6 */
112#define REG_B1_EPMM7 0x0f /* pattern match mask - byte 7 */
113#define REG_B1_EPMCSL 0x10 /* pattern match checksum - low byte */
114#define REG_B1_EPMCSH 0x11 /* pattern match checksum - high byte */
115#define REG_B1_EPMOL 0x14 /* pattern match offset - low byte */
116#define REG_B1_EPMOH 0x15 /* pattern match offset - high byte */
117#define REG_B1_ERXFCON 0x18 /* receive filter control register */
118#define REG_B1_EPKTCNT 0x19 /* packet count */
120
125#define REG_B2_MACON1 0x00 /* MAC control register 1 */
126#define REG_B2_MACON3 0x02 /* MAC control register 3 */
127#define REG_B2_MACON4 0x03 /* MAC control register 4 */
128#define REG_B2_MABBIPG 0x04 /* back-to-back inter-packet gap */
129#define REG_B2_MAIPGL 0x06 /* non-back-to-back inter-packet gap - low byte */
130#define REG_B2_MAIPGH 0x07 /* non-back-to-back inter-packet gap - high byte */
131#define REG_B2_MACLCON1 0x08 /* retransmission maximum */
132#define REG_B2_MACLCON2 0x09 /* collision window */
133#define REG_B2_MAMXFLL 0x0a /* maximum frame length - low byte */
134#define REG_B2_MAMXFLH 0x0b /* maximum frame length - high byte */
135#define REG_B2_MICMD 0x12 /* MIIM command */
136#define REG_B2_MIREGADR 0x14 /* MIIM register address */
137#define REG_B2_MIWRL 0x16 /* MIIM write data register - low byte */
138#define REG_B2_MIWRH 0x17 /* MIIM write data register - high byte */
139#define REG_B2_MIRDL 0x18 /* MIIM read data register - low byte */
140#define REG_B2_MIRDH 0x19 /* MIIM read data register - high byte */
142
147#define REG_B3_MAADR5 0x00 /* MAC address - byte 5 */
148#define REG_B3_MAADR6 0x01 /* MAC address - byte 6 */
149#define REG_B3_MAADR3 0x02 /* MAC address - byte 3 */
150#define REG_B3_MAADR4 0x03 /* MAC address - byte 4 */
151#define REG_B3_MAADR1 0x04 /* MAC address - byte 1 */
152#define REG_B3_MAADR2 0x05 /* MAC address - byte 2 */
153#define REG_B3_EBSTSD 0x06 /* built-in self-test fill seed */
154#define REG_B3_EBSTCON 0x07 /* built-in self-test control register */
155#define REG_B3_EBSTCSL 0x08 /* built-in self-test checksum - low byte */
156#define REG_B3_EBSTCSH 0x09 /* built-in self-test checksum - high byte */
157#define REG_B3_MISTAT 0x0a /* MIIM status register */
158#define REG_B3_EREVID 0x12 /* Ethernet revision ID */
159#define REG_B3_ECOCON 0x15 /* clock output control */
160#define REG_B3_EFLOCON 0x17 /* Ethernet flow control */
161#define REG_B3_EPAUSL 0x18 /* pause timer value - low byte */
162#define REG_B3_EPAUSH 0x19 /* pause timer value - high byte */
164
169#define REG_PHY_PHCON1 0x00
170#define REG_PHY_PHSTAT1 0x01
171#define REG_PHY_PHID1 0x02
172#define REG_PHY_PHID2 0x03
173#define REG_PHY_PHCON2 0x10
174#define REG_PHY_PHSTAT2 0x11
175#define REG_PHY_PHIE 0x12
176#define REG_PHY_PHIR 0x13
177#define REG_PHY_PHLCON 0x14
179
184#define EIE_INTIE 0x80
185#define EIE_PKTIE 0x40
186#define EIE_DMAIE 0x20
187#define EIE_LINKIE 0x10
188#define EIE_TXIE 0x08
189#define EIE_TXERIE 0x02
190#define EIE_RXERIE 0x01
192
197#define EIR_PKTIF 0x40
198#define EIR_DMAIF 0x20
199#define EIR_LINKIF 0x10
200#define EIR_TXIF 0x08
201#define EIR_TXERIF 0x02
202#define EIR_RXERIF 0x01
204
209#define ESTAT_INT 0x80
210#define ESTAT_BUFFER 0x40
211#define ESTAT_LATECOL 0x10
212#define ESTAT_RXBUSY 0x40
213#define ESTAT_TXABRT 0x20
214#define ESTAT_CLKRDY 0x01
216
221#define ECON1_TXRST 0x80
222#define ECON1_RXRST 0x40
223#define ECON1_DMAST 0x20
224#define ECON1_CSUMEN 0x10
225#define ECON1_TXRTS 0x08
226#define ECON1_RXEN 0x04
227#define ECON1_BSEL1 0x02
228#define ECON1_BSEL0 0x01
229#define ECON1_BSEL_MASK 0x03
231
236#define ECON2_AUTOINC 0x80
237#define ECON2_PKTDEC 0x40
238#define ECON2_PWRSV 0x20
239#define ECON2_VRPS 0x40
241
246#define ERXFCON_UCEN 0x80
247#define ERXFCON_ANDOR 0x40
248#define ERXFCON_CRCEN 0x20
249#define ERXFCON_PMEN 0x10
250#define ERXFCON_MPEN 0x08
251#define ERXFCON_HTEN 0x04
252#define ERXFCON_MCEN 0x02
253#define ERXFCON_BCEN 0x01
255
260#define MACON1_TXPAUS 0x08
261#define MACON1_RXPAUS 0x04
262#define MACON1_PASSALL 0x02
263#define MACON1_MARXEN 0x01
265
270#define MACON3_PADCFG2 0x80
271#define MACON3_PADCFG1 0x40
272#define MACON3_PADCFG0 0x20
273#define MACON3_TXCRCEN 0x10
274#define MACON3_PHDREN 0x08
275#define MACON3_HFRMEN 0x04
276#define MACON3_FRMLNEN 0x02
277#define MACON3_FULDPX 0x01
279
284#define MACON4_DEFER 0x40
285#define MACON4_BPEN 0x20
286#define MACON4_NOBKOFF 0x10
288
293#define MABBIPG_FD 0x15
294#define MABBIPG_HD 0x12
296
301#define MAIPGL_FD 0x12
303
308#define MICMD_MIISCAN 0x02
309#define MICMD_MIIRD 0x01
311
316#define MISTAT_NVALID 0x04
317#define MISTAT_SCAN 0x02
318#define MISTAT_BUSY 0x01
320
325#define EFLOCON_FULDPXS 0x04
326#define EFLOCON_FCEN1 0x02
327#define EFLOCON_FCEN0 0x01
328#define EFLOCON_FCEN_MASK 0x03
330
335#define PHCON1_PRST 0x8000
336#define PHCON1_PLOOPBK 0x4000
337#define PHCON1_PPWRSV 0x0800
338#define PHCON1_PDPXMD 0x0100
340
345#define PHSTAT1_PFDPX 0x1000
346#define PHSTAT1_PHDPX 0x0800
347#define PHSTAT1_LLSTAT 0x0004
348#define PHSTAT1_JBSTAT 0x0002
350
355#define PHCON2_FRCLNK 0x4000
356#define PHCON2_TXDIS 0x2000
357#define PHCON2_JABBER 0x0400
358#define PHCON2_HDLDIS 0x0100
360
365#define PHSTAT2_TXSTAT 0x2000
366#define PHSTAT2_RXSTAT 0x1000
367#define PHSTAT2_COLSTAT 0x0800
368#define PHSTAT2_LSTAT 0x0400
369#define PHSTAT2_DPXSTAT 0x0200
370#define PHSTAT2_PLRITY 0x0020
372
377#define PHIE_PLNKIE 0x0010
378#define PHIE_PGEIE 0x0002
380
385#define PHIR_PLNKIF 0x0010
386#define PHIR_PGIF 0x0004
388
393#define PHLCON_LACFG(x) ((x & 0xf) << 8)
394#define PHLCON_LBCFG(x) ((x & 0xf) << 4)
395#define PHLCON_LFRQ(x) ((x & 0x3) << 2)
396#define PHLCON_STRCH 0x0002
398
403#define FRAME_4_RECV_OK 0x80
404#define FRAME_4_LENGTH_OOR 0x40
405#define FRAME_4_LENGTH_ERR 0x20
406#define FRAME_4_CRC_ERR 0x10
407#define FRAME_4_CARRIER_EVT 0x04
408#define FRAME_4_LONG_EVT 0x01
409
410#define FRAME_5_VLAN 0x40
411#define FRAME_5_UKWN_OPCODE 0x20
412#define FRAME_5_PAUSE 0x10
413#define FRAME_5_RCV_CTRL 0x08
414#define FRAME_5_DRIPPLE 0x04
415#define FRAME_5_BCAST 0x02
416#define FRAME_5_MCAST 0x01
418
423#define TX_PHUGEEN 0x08
424#define TX_PPADEN 0x04
425#define TX_PCRCEN 0x02
426#define TX_POVERRIDE 0x01
428
429#ifdef __cplusplus
430}
431#endif
432