irq_arch.h File Reference

Implementation of the kernels irq interface. More...

Detailed Description

Implementation of the kernels irq interface.

Author
Gunar Schorcht gunar.nosp@m.@sch.nosp@m.orcht.nosp@m..net

Definition in file irq_arch.h.

#include "irq_arch_common.h"
+ Include dependency graph for irq_arch.h:

Go to the source code of this file.

Functions

void esp_irq_init (void)
 Initialize architecture specific interrupt handling.
 

CPU interrupt numbers

All interrupts that are used for RIOT-OS are preallocated and fix.

The allocated interrupts are all level interrupts, most of them with low priority.

#define CPU_INUM_RMT   1
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_GPIO   2
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_CAN   3
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_UART   4
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_USB   8
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_RTT   9
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_SERIAL_JTAG   10
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_I2C   12
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_WDT   13
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_SOFTWARE   17
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_ETH   18
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_LCD   18
 Level interrupt with low priority 1. More...
 
#define CPU_INUM_TIMER   19
 Level interrupt with medium priority 2. More...
 
#define CPU_INUM_FRC2   20
 Level interrupt with medium priority 2. More...
 
#define CPU_INUM_SYSTIMER   20
 Level interrupt with medium priority 2. More...
 
#define CPU_INUM_BLE   21
 Level interrupt with medium priority 2. More...
 
#define CPU_INUM_SDMMC   23
 Level interrupt with medium priority 2. More...
 
#define CPU_INUM_CACHEERR   25
 Level interrupt with high priority 4
More...
 

Macro Definition Documentation

◆ CPU_INUM_BLE

#define CPU_INUM_BLE   21

Level interrupt with medium priority 2.

Definition at line 54 of file irq_arch.h.

◆ CPU_INUM_CACHEERR

#define CPU_INUM_CACHEERR   25

Level interrupt with high priority 4

Definition at line 56 of file irq_arch.h.

◆ CPU_INUM_CAN

#define CPU_INUM_CAN   3

Level interrupt with low priority 1.

Definition at line 41 of file irq_arch.h.

◆ CPU_INUM_ETH

#define CPU_INUM_ETH   18

Level interrupt with low priority 1.

Definition at line 49 of file irq_arch.h.

◆ CPU_INUM_FRC2

#define CPU_INUM_FRC2   20

Level interrupt with medium priority 2.

Definition at line 52 of file irq_arch.h.

◆ CPU_INUM_GPIO

#define CPU_INUM_GPIO   2

Level interrupt with low priority 1.

Definition at line 40 of file irq_arch.h.

◆ CPU_INUM_I2C

#define CPU_INUM_I2C   12

Level interrupt with low priority 1.

Definition at line 46 of file irq_arch.h.

◆ CPU_INUM_LCD

#define CPU_INUM_LCD   18

Level interrupt with low priority 1.

Definition at line 50 of file irq_arch.h.

◆ CPU_INUM_RMT

#define CPU_INUM_RMT   1

Level interrupt with low priority 1.

Definition at line 39 of file irq_arch.h.

◆ CPU_INUM_RTT

#define CPU_INUM_RTT   9

Level interrupt with low priority 1.

Definition at line 44 of file irq_arch.h.

◆ CPU_INUM_SDMMC

#define CPU_INUM_SDMMC   23

Level interrupt with medium priority 2.

Definition at line 55 of file irq_arch.h.

◆ CPU_INUM_SERIAL_JTAG

#define CPU_INUM_SERIAL_JTAG   10

Level interrupt with low priority 1.

Definition at line 45 of file irq_arch.h.

◆ CPU_INUM_SOFTWARE

#define CPU_INUM_SOFTWARE   17

Level interrupt with low priority 1.

Definition at line 48 of file irq_arch.h.

◆ CPU_INUM_SYSTIMER

#define CPU_INUM_SYSTIMER   20

Level interrupt with medium priority 2.

Definition at line 53 of file irq_arch.h.

◆ CPU_INUM_TIMER

#define CPU_INUM_TIMER   19

Level interrupt with medium priority 2.

Definition at line 51 of file irq_arch.h.

◆ CPU_INUM_UART

#define CPU_INUM_UART   4

Level interrupt with low priority 1.

Definition at line 42 of file irq_arch.h.

◆ CPU_INUM_USB

#define CPU_INUM_USB   8

Level interrupt with low priority 1.

Definition at line 43 of file irq_arch.h.

◆ CPU_INUM_WDT

#define CPU_INUM_WDT   13

Level interrupt with low priority 1.

Definition at line 47 of file irq_arch.h.