Macros for PIO (Programmable I/O) instructions. More...
Macros for PIO (Programmable I/O) instructions.
Macros | |
| #define | PIO_JMP(cond, addr) |
| JMP instruction encoding. | |
| #define | PIO_JMP_ALWAYS(addr) |
| JMP - unconditional jump. | |
| #define | PIO_JMP_X_ZERO(addr) |
| JMP !X - jump if X is zero. | |
| #define | PIO_JMP_X_DEC(addr) |
| JMP X– - jump if X non-zero, then decrement X. | |
| #define | PIO_JMP_Y_ZERO(addr) |
| JMP !Y - jump if Y is zero. | |
| #define | PIO_JMP_Y_DEC(addr) |
| JMP Y– - jump if Y non-zero, then decrement Y. | |
| #define | PIO_JMP_X_NE_Y(addr) |
| JMP X!=Y - jump if X not equal to Y. | |
| #define | PIO_JMP_PIN(addr) |
| JMP PIN - jump if input pin is high. | |
| #define | PIO_JMP_OSRE_NOT_EMPTY(addr) |
| JMP !OSRE - jump if OSR not empty. | |
| #define | PIO_WAIT(pol, src, index) |
| WAIT instruction encoding. | |
| #define | PIO_WAIT_GPIO(pol, gpio) |
| WAIT GPIO - wait on absolute GPIO pin. | |
| #define | PIO_WAIT_PIN(pol, pin) |
| WAIT PIN - wait on mapped input pin. | |
| #define | PIO_WAIT_IRQ(pol, idxmode, irq) |
| WAIT IRQ - wait on IRQ flag. | |
| #define | PIO_WAIT_IRQ_REL(pol, irq) |
| WAIT IRQ with relative addressing. | |
| #define | PIO_WAIT_IRQ_PREV(pol, irq) |
| WAIT IRQ on previous PIO block. | |
| #define | PIO_WAIT_IRQ_NEXT(pol, irq) |
| WAIT IRQ on next PIO block. | |
| #define | PIO_WAIT_JMPPIN(pol, offset) |
| WAIT JMPPIN - wait on jump pin. | |
| #define | PIO_IN(src, bitcount) |
| IN instruction encoding. | |
| #define | PIO_IN_PINS(bits) |
| IN PINS - shift bits from pins into ISR. | |
| #define | PIO_IN_X(bits) |
| IN X - shift bits from X into ISR. | |
| #define | PIO_IN_Y(bits) |
| IN Y - shift bits from Y into ISR. | |
| #define | PIO_IN_NULL(bits) |
| IN NULL - shift zero bits into ISR. | |
| #define | PIO_IN_ISR(bits) |
| IN ISR - shift bits from ISR into ISR. | |
| #define | PIO_IN_OSR(bits) |
| IN OSR - shift bits from OSR into ISR. | |
| #define | PIO_OUT(dest, bitcount) |
| OUT instruction encoding. | |
| #define | PIO_OUT_PINS(bits) |
| OUT PINS - shift bits from OSR to pins. | |
| #define | PIO_OUT_X(bits) |
| OUT X - shift bits from OSR to X. | |
| #define | PIO_OUT_Y(bits) |
| OUT Y - shift bits from OSR to Y. | |
| #define | PIO_OUT_NULL(bits) |
| OUT NULL - discard bits from OSR. | |
| #define | PIO_OUT_PINDIRS(bits) |
| OUT PINDIRS - shift bits from OSR to pin directions. | |
| #define | PIO_OUT_PC(bits) |
| OUT PC - shift bits from OSR to program counter (jump) | |
| #define | PIO_OUT_ISR(bits) |
| OUT ISR - shift bits from OSR to ISR. | |
| #define | PIO_OUT_EXEC(bits) |
| OUT EXEC - execute bits from OSR as instruction. | |
| #define | PIO_PUSH(iffull, block) |
| PUSH instruction encoding. | |
| #define | PIO_PUSH_BLOCK() |
| PUSH instruction - block by default. | |
| #define | PIO_PUSH_NOBLOCK() |
| PUSH instruction - non-blocking. | |
| #define | PIO_PUSH_IFFULL() |
| PUSH instruction - if full, blocking. | |
| #define | PIO_PUSH_IFFULL_NOBLOCK() |
| PUSH instruction - if full, non-blocking. | |
| #define | PIO_PULL(ifempty, block) |
| PULL instruction encoding. | |
| #define | PIO_PULL_BLOCK() |
| PULL instruction - block by default. | |
| #define | PIO_PULL_NOBLOCK() |
| PULL instruction - non-blocking. | |
| #define | PIO_PULL_IFEMPTY() |
| PULL instruction - if empty, blocking. | |
| #define | PIO_PULL_IFEMPTY_NOBLOCK() |
| PULL instruction - if empty, non-blocking. | |
| #define | PIO_MOV_RXFIFO_ISR(idxi, index) |
| MOV to RX FIFO instruction encoding. | |
| #define | PIO_MOV_RXFIFO_Y_ISR() |
| MOV rxfifo[y], isr - index by Y register. | |
| #define | PIO_MOV_RXFIFO_IDX_ISR(idx) |
| MOV rxfifo[index], isr - index by immediate value. | |
| #define | PIO_MOV_OSR_RXFIFO(idxi, index) |
| MOV from RX FIFO instruction encoding. | |
| #define | PIO_MOV_OSR_RXFIFO_Y() |
| MOV osr, rxfifo[y] - index by Y register. | |
| #define | PIO_MOV_OSR_RXFIFO_IDX(idx) |
| MOV osr, rxfifo[index] - index by immediate value. | |
| #define | PIO_MOV(dest, op, src) |
| MOV instruction encoding. | |
| #define | PIO_IRQ(clr, wait, idxmode, index) |
| IRQ instruction encoding. | |
| #define | PIO_IRQ_SET(num) |
| IRQ set - raise IRQ without waiting. | |
| #define | PIO_IRQ_NOWAIT(num) |
| IRQ nowait - raise IRQ without waiting (same as SET) | |
| #define | PIO_IRQ_WAIT(num) |
| IRQ wait - raise IRQ and wait for it to be cleared. | |
| #define | PIO_IRQ_CLEAR(num) |
| IRQ clear - clear IRQ flag. | |
| #define | PIO_IRQ_SET_REL(num) |
| IRQ set with relative addressing. | |
| #define | PIO_IRQ_WAIT_REL(num) |
| IRQ wait with relative addressing. | |
| #define | PIO_IRQ_SET_PREV(num) |
| IRQ set targeting previous PIO block. | |
| #define | PIO_IRQ_SET_NEXT(num) |
| IRQ set targeting next PIO block. | |
| #define | PIO_SET(dest, data) |
| SET instruction encoding. | |
| #define | PIO_SET_PINS(val) |
| SET pins - set pin values. | |
| #define | PIO_SET_X(val) |
| SET x - set scratch register X. | |
| #define | PIO_SET_Y(val) |
| SET y - set scratch register Y. | |
| #define | PIO_SET_PINDIRS(val) |
| SET pindirs - set pin directions. | |
JMP instruction conditions | |
| #define | PIO_JMP_COND_ALWAYS (0) |
| Always jump. | |
| #define | PIO_JMP_COND_X_ZERO (1) |
| Jump if X is zero (!X) | |
| #define | PIO_JMP_COND_X_DEC (2) |
| Jump if X non-zero pre-decrement (X–) | |
| #define | PIO_JMP_COND_Y_ZERO (3) |
| Jump if Y is zero (!Y) | |
| #define | PIO_JMP_COND_Y_DEC (4) |
| Jump if Y non-zero pre-decrement (Y–) | |
| #define | PIO_JMP_COND_X_NE_Y (5) |
| Jump if X not equal Y. | |
| #define | PIO_JMP_COND_PIN (6) |
| Jump if input pin is high. | |
| #define | PIO_JMP_COND_OSRE_NOT_EMPTY (7) |
| Jump if OSR not empty (!OSRE) | |
WAIT instruction sources | |
| #define | PIO_WAIT_SRC_GPIO (0) |
| Wait on GPIO (absolute) | |
| #define | PIO_WAIT_SRC_PIN (1) |
| Wait on PIN (mapped) | |
| #define | PIO_WAIT_SRC_IRQ (2) |
| Wait on IRQ flag. | |
| #define | PIO_WAIT_SRC_JMPPIN (3) |
| Wait on JMPPIN. | |
WAIT IRQ index modes (decoded from 2 MSBs of index) | |
| #define | PIO_WAIT_IRQ_IDXMODE_DIRECT (0) |
| Direct indexing (0-7) | |
| #define | PIO_WAIT_IRQ_IDXMODE_PREV (1) |
| Previous PIO block. | |
| #define | PIO_WAIT_IRQ_IDXMODE_REL (2) |
| Relative (add state machine ID) | |
| #define | PIO_WAIT_IRQ_IDXMODE_NEXT (3) |
| Next PIO block. | |
IN instruction sources | |
| #define | PIO_IN_SRC_PINS (0) |
| PINS. | |
| #define | PIO_IN_SRC_X (1) |
| Scratch register X. | |
| #define | PIO_IN_SRC_Y (2) |
| Scratch register Y. | |
| #define | PIO_IN_SRC_NULL (3) |
| NULL (all zeroes) | |
| #define | PIO_IN_SRC_ISR (6) |
| Input shift register. | |
| #define | PIO_IN_SRC_OSR (7) |
| Output shift register. | |
OUT instruction destinations | |
| #define | PIO_OUT_DEST_PINS (0) |
| PINS. | |
| #define | PIO_OUT_DEST_X (1) |
| Scratch register X. | |
| #define | PIO_OUT_DEST_Y (2) |
| Scratch register Y. | |
| #define | PIO_OUT_DEST_NULL (3) |
| NULL (discard data) | |
| #define | PIO_OUT_DEST_PINDIRS (4) |
| PINDIRS. | |
| #define | PIO_OUT_DEST_PC (5) |
| Program counter. | |
| #define | PIO_OUT_DEST_ISR (6) |
| Input shift register. | |
| #define | PIO_OUT_DEST_EXEC (7) |
| Execute as instruction. | |
MOV instruction destinations | |
| #define | PIO_MOV_DEST_PINS (0) |
| PINS (uses same pin mapping as OUT) | |
| #define | PIO_MOV_DEST_X (1) |
| Scratch register X. | |
| #define | PIO_MOV_DEST_Y (2) |
| Scratch register Y. | |
| #define | PIO_MOV_DEST_PINDIRS (3) |
| PINDIRS (uses same pin mapping as OUT) | |
| #define | PIO_MOV_DEST_EXEC (4) |
| Execute data as instruction. | |
| #define | PIO_MOV_DEST_PC (5) |
| Program counter. | |
| #define | PIO_MOV_DEST_ISR (6) |
| Input shift register. | |
| #define | PIO_MOV_DEST_OSR (7) |
| Output shift register. | |
MOV instruction operations | |
| #define | PIO_MOV_OP_NONE (0) |
| No operation. | |
| #define | PIO_MOV_OP_INVERT (1) |
| Bitwise complement. | |
| #define | PIO_MOV_OP_BITREV (2) |
| Bit-reverse. | |
MOV instruction sources | |
| #define | PIO_MOV_SRC_PINS (0) |
| PINS (uses same pin mapping as IN) | |
| #define | PIO_MOV_SRC_X (1) |
| Scratch register X. | |
| #define | PIO_MOV_SRC_Y (2) |
| Scratch register Y. | |
| #define | PIO_MOV_SRC_NULL (3) |
| NULL (all zeroes) | |
| #define | PIO_MOV_SRC_STATUS (5) |
| STATUS (configured by EXECCTRL_STATUS_SEL) | |
| #define | PIO_MOV_SRC_ISR (6) |
| Input shift register. | |
| #define | PIO_MOV_SRC_OSR (7) |
| Output shift register. | |
IRQ instruction index modes | |
| #define | PIO_IRQ_IDXMODE_DIRECT (0) |
| Direct indexing (0-7) | |
| #define | PIO_IRQ_IDXMODE_PREV (1) |
| Previous PIO block. | |
| #define | PIO_IRQ_IDXMODE_REL (2) |
| Relative (add state machine ID) | |
| #define | PIO_IRQ_IDXMODE_NEXT (3) |
| Next PIO block. | |
SET instruction destinations | |
| #define | PIO_SET_DEST_PINS (0) |
| PINS. | |
| #define | PIO_SET_DEST_X (1) |
| Scratch register X. | |
| #define | PIO_SET_DEST_Y (2) |
| Scratch register Y. | |
| #define | PIO_SET_DEST_PINDIRS (4) |
| PINDIRS. | |
| #define PIO_IN | ( | src, | |
| bitcount ) |
| #define PIO_IN_ISR | ( | bits | ) |
IN ISR - shift bits from ISR into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IN_NULL | ( | bits | ) |
IN NULL - shift zero bits into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IN_OSR | ( | bits | ) |
IN OSR - shift bits from OSR into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IN_PINS | ( | bits | ) |
IN PINS - shift bits from pins into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IN_X | ( | bits | ) |
IN X - shift bits from X into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IN_Y | ( | bits | ) |
IN Y - shift bits from Y into ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_IRQ | ( | clr, | |
| wait, | |||
| idxmode, | |||
| index ) |
IRQ instruction encoding.
Set or clear the IRQ flag selected by index.
| [in] | clr | If 1, clear the flag instead of raising it |
| [in] | wait | If 1, halt until the raised flag is lowered again |
| [in] | idxmode | Index mode (PIO_IRQ_IDXMODE_*) |
| [in] | index | IRQ index (0-7) |
| #define PIO_IRQ_CLEAR | ( | num | ) |
IRQ clear - clear IRQ flag.
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_IDXMODE_REL (2) |
| #define PIO_IRQ_NOWAIT | ( | num | ) |
IRQ nowait - raise IRQ without waiting (same as SET)
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_SET | ( | num | ) |
IRQ set - raise IRQ without waiting.
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_SET_NEXT | ( | num | ) |
IRQ set targeting next PIO block.
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_SET_PREV | ( | num | ) |
IRQ set targeting previous PIO block.
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_SET_REL | ( | num | ) |
IRQ set with relative addressing.
| [in] | num | IRQ number (0-7), low 2 bits added to state machine ID |
| #define PIO_IRQ_WAIT | ( | num | ) |
IRQ wait - raise IRQ and wait for it to be cleared.
| [in] | num | IRQ number (0-7) |
| #define PIO_IRQ_WAIT_REL | ( | num | ) |
IRQ wait with relative addressing.
| [in] | num | IRQ number (0-7), low 2 bits added to state machine ID |
| #define PIO_JMP | ( | cond, | |
| addr ) |
| #define PIO_JMP_ALWAYS | ( | addr | ) |
JMP - unconditional jump.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_COND_OSRE_NOT_EMPTY (7) |
| #define PIO_JMP_COND_X_DEC (2) |
| #define PIO_JMP_COND_Y_DEC (4) |
| #define PIO_JMP_OSRE_NOT_EMPTY | ( | addr | ) |
JMP !OSRE - jump if OSR not empty.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_PIN | ( | addr | ) |
JMP PIN - jump if input pin is high.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_X_DEC | ( | addr | ) |
JMP X– - jump if X non-zero, then decrement X.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_X_NE_Y | ( | addr | ) |
JMP X!=Y - jump if X not equal to Y.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_X_ZERO | ( | addr | ) |
JMP !X - jump if X is zero.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_Y_DEC | ( | addr | ) |
JMP Y– - jump if Y non-zero, then decrement Y.
| [in] | addr | Target address (0-31) |
| #define PIO_JMP_Y_ZERO | ( | addr | ) |
JMP !Y - jump if Y is zero.
| [in] | addr | Target address (0-31) |
| #define PIO_MOV | ( | dest, | |
| op, | |||
| src ) |
MOV instruction encoding.
Copy data from Source to Destination.
| [in] | dest | Destination (PIO_MOV_DEST_*) |
| [in] | op | Operation (PIO_MOV_OP_*) |
| [in] | src | Source (PIO_MOV_SRC_*) |
| #define PIO_MOV_DEST_PINDIRS (3) |
| #define PIO_MOV_DEST_PINS (0) |
| #define PIO_MOV_OSR_RXFIFO | ( | idxi, | |
| index ) |
MOV from RX FIFO instruction encoding.
Read the selected RX FIFO entry into the OSR (indexed access). Requires SHIFTCTRL_FJOIN_RX_GET configuration.
| [in] | idxi | If 1, index by immediate. If 0, index by Y register |
| [in] | index | RX FIFO entry index (0-3) or 0 when indexing by Y |
| #define PIO_MOV_OSR_RXFIFO_IDX | ( | idx | ) |
MOV osr, rxfifo[index] - index by immediate value.
| [in] | idx | RX FIFO entry index (0-3) |
| #define PIO_MOV_OSR_RXFIFO_Y | ( | ) |
MOV osr, rxfifo[y] - index by Y register.
| #define PIO_MOV_RXFIFO_IDX_ISR | ( | idx | ) |
MOV rxfifo[index], isr - index by immediate value.
| [in] | idx | RX FIFO entry index (0-3) |
| #define PIO_MOV_RXFIFO_ISR | ( | idxi, | |
| index ) |
MOV to RX FIFO instruction encoding.
Write the ISR to a selected RX FIFO entry (indexed access). Requires SHIFTCTRL_FJOIN_RX_PUT configuration.
| [in] | idxi | If 1, index by immediate. If 0, index by Y register |
| [in] | index | RX FIFO entry index (0-3) or 0 when indexing by Y |
| #define PIO_MOV_RXFIFO_Y_ISR | ( | ) |
MOV rxfifo[y], isr - index by Y register.
| #define PIO_MOV_SRC_PINS (0) |
| #define PIO_MOV_SRC_STATUS (5) |
| #define PIO_OUT | ( | dest, | |
| bitcount ) |
OUT instruction encoding.
Shift bit count bits out of the OSR and write to destination.
| [in] | dest | Destination (PIO_OUT_DEST_*) |
| [in] | bitcount | Number of bits to shift (1-32, 32 encoded as 0) |
| #define PIO_OUT_EXEC | ( | bits | ) |
OUT EXEC - execute bits from OSR as instruction.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_ISR | ( | bits | ) |
OUT ISR - shift bits from OSR to ISR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_NULL | ( | bits | ) |
OUT NULL - discard bits from OSR.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_PC | ( | bits | ) |
OUT PC - shift bits from OSR to program counter (jump)
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_PINDIRS | ( | bits | ) |
OUT PINDIRS - shift bits from OSR to pin directions.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_PINS | ( | bits | ) |
OUT PINS - shift bits from OSR to pins.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_X | ( | bits | ) |
OUT X - shift bits from OSR to X.
| [in] | bits | Number of bits (1-32) |
| #define PIO_OUT_Y | ( | bits | ) |
OUT Y - shift bits from OSR to Y.
| [in] | bits | Number of bits (1-32) |
| #define PIO_PULL | ( | ifempty, | |
| block ) |
PULL instruction encoding.
Load a 32-bit word from the TX FIFO into the OSR.
| [in] | ifempty | If 1, do nothing unless shift count reached threshold |
| [in] | block | If 1, stall if TX FIFO is empty. If 0, copy X to OSR |
| #define PIO_PULL_BLOCK | ( | ) |
| #define PIO_PULL_IFEMPTY | ( | ) |
| #define PIO_PULL_IFEMPTY_NOBLOCK | ( | ) |
| #define PIO_PULL_NOBLOCK | ( | ) |
| #define PIO_PUSH | ( | iffull, | |
| block ) |
PUSH instruction encoding.
Push the contents of the ISR into the RX FIFO as a single 32-bit word. Clear ISR to all-zeroes.
| [in] | iffull | If 1, do nothing unless shift count reached threshold |
| [in] | block | If 1, stall execution if RX FIFO is full |
| #define PIO_PUSH_BLOCK | ( | ) |
| #define PIO_PUSH_IFFULL | ( | ) |
| #define PIO_PUSH_IFFULL_NOBLOCK | ( | ) |
| #define PIO_PUSH_NOBLOCK | ( | ) |
| #define PIO_SET | ( | dest, | |
| data ) |
| #define PIO_SET_PINDIRS | ( | val | ) |
SET pindirs - set pin directions.
| [in] | val | Value to set (0-31) |
| #define PIO_SET_PINS | ( | val | ) |
SET pins - set pin values.
| [in] | val | Value to set (0-31) |
| #define PIO_SET_X | ( | val | ) |
SET x - set scratch register X.
| [in] | val | Value to set (0-31) |
| #define PIO_SET_Y | ( | val | ) |
SET y - set scratch register Y.
| [in] | val | Value to set (0-31) |
| #define PIO_WAIT | ( | pol, | |
| src, | |||
| index ) |
WAIT instruction encoding.
Stall until some condition is met.
| [in] | pol | Polarity: 1 to wait for 1, 0 to wait for 0 |
| [in] | src | Source (PIO_WAIT_SRC_*) |
| [in] | index | Index value (interpretation depends on source) |
| #define PIO_WAIT_GPIO | ( | pol, | |
| gpio ) |
WAIT GPIO - wait on absolute GPIO pin.
| [in] | pol | Polarity (0 or 1) |
| [in] | gpio | GPIO number |
| #define PIO_WAIT_IRQ | ( | pol, | |
| idxmode, | |||
| irq ) |
WAIT IRQ - wait on IRQ flag.
| [in] | pol | Polarity (0 or 1) |
| [in] | idxmode | Index mode (PIO_WAIT_IRQ_IDXMODE_*) |
| [in] | irq | IRQ number (0-7) |
| #define PIO_WAIT_IRQ_IDXMODE_REL (2) |
| #define PIO_WAIT_IRQ_NEXT | ( | pol, | |
| irq ) |
WAIT IRQ on next PIO block.
| [in] | pol | Polarity (0 or 1) |
| [in] | irq | IRQ number (0-7) |
| #define PIO_WAIT_IRQ_PREV | ( | pol, | |
| irq ) |
WAIT IRQ on previous PIO block.
| [in] | pol | Polarity (0 or 1) |
| [in] | irq | IRQ number (0-7) |
| #define PIO_WAIT_IRQ_REL | ( | pol, | |
| irq ) |
WAIT IRQ with relative addressing.
| [in] | pol | Polarity (0 or 1) |
| [in] | irq | IRQ number (0-7), low 2 bits added to state machine ID |
| #define PIO_WAIT_JMPPIN | ( | pol, | |
| offset ) |
WAIT JMPPIN - wait on jump pin.
| [in] | pol | Polarity (0 or 1) |
| [in] | offset | Offset added to PINCTRL_JMP_PIN (0-3) |
| #define PIO_WAIT_PIN | ( | pol, | |
| pin ) |
WAIT PIN - wait on mapped input pin.
| [in] | pol | Polarity (0 or 1) |
| [in] | pin | Pin number (mapped via PINCTRL_IN_BASE) |