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kw2xrf_reg.h
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1/*
2 * Copyright (C) 2016 Phytec Messtechnik GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 *
8 * The description of the registers was extracted from the
9 * Reference Manual MKW2xDxxxRM.pdf. After the release of MCR20A Device,
10 * it was extended by the undocumented registers from the file MCR20reg.h.
11 *
12 * Portions of this file are derived from material that is
13 * Copyright (c) 2015, Freescale Semiconductor, Inc.
14 * All rights reserved.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * o Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * o Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
27 * contributors may be used to endorse or promote products derived from this
28 * software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
34 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43#pragma once
44
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
60#define MKW2XDRF_REG_READ (uint8_t)(1 << 7)
61
63#define MKW2XDRF_REG_WRITE (uint8_t)(0)
64
66#define MKW2XDRF_BUF_READ (uint8_t)(1 << 7 | 1 << 6)
67
69#define MKW2XDRF_BUF_WRITE (uint8_t)(1 << 6)
70
72#define MKW2XDRF_BUF_BYTE_READ (uint8_t)(1 << 7 | 1 << 6 | 1 << 5)
73
75#define MKW2XDRF_BUF_BYTE_WRITE (uint8_t)(1 << 6 | 1 << 5)
76
78typedef enum {
79 XCVSEQ_IDLE = 0,
80 XCVSEQ_RECEIVE,
81 XCVSEQ_TRANSMIT,
82 XCVSEQ_CCA,
83 XCVSEQ_TX_RX,
84 XCVSEQ_CONTINUOUS_CCA,
85}
87
124 MKW2XDM_PA_PWR = 0x23,
128 MKW2XDM_ASM_CTRL1 = 0x28,
129 MKW2XDM_ASM_CTRL2 = 0x29,
130 MKW2XDM_ASM_DATA_0 = 0x2A,
131 MKW2XDM_ASM_DATA_1 = 0x2B,
132 MKW2XDM_ASM_DATA_2 = 0x2C,
133 MKW2XDM_ASM_DATA_3 = 0x2D,
134 MKW2XDM_ASM_DATA_4 = 0x2E,
135 MKW2XDM_ASM_DATA_5 = 0x2F,
136 MKW2XDM_ASM_DATA_6 = 0x30,
137 MKW2XDM_ASM_DATA_7 = 0x31,
138 MKW2XDM_ASM_DATA_8 = 0x32,
139 MKW2XDM_ASM_DATA_9 = 0x33,
140 MKW2XDM_ASM_DATA_A = 0x34,
141 MKW2XDM_ASM_DATA_B = 0x35,
142 MKW2XDM_ASM_DATA_C = 0x36,
143 MKW2XDM_ASM_DATA_D = 0x37,
144 MKW2XDM_ASM_DATA_E = 0x38,
145 MKW2XDM_ASM_DATA_F = 0x39,
151};
152
153#define MKW2XDM_IRQSTS1_RX_FRM_PEND (1 << 7)
154#define MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ (1 << 6)
155#define MKW2XDM_IRQSTS1_FILTERFAIL_IRQ (1 << 5)
156#define MKW2XDM_IRQSTS1_RXWTRMRKIRQ (1 << 4)
157#define MKW2XDM_IRQSTS1_CCAIRQ (1 << 3)
158#define MKW2XDM_IRQSTS1_RXIRQ (1 << 2)
159#define MKW2XDM_IRQSTS1_TXIRQ (1 << 1)
160#define MKW2XDM_IRQSTS1_SEQIRQ (1 << 0)
161
162#define MKW2XDM_IRQSTS2_CRCVALID (1 << 7)
163#define MKW2XDM_IRQSTS2_CCA (1 << 6)
164#define MKW2XDM_IRQSTS2_SRCADDR (1 << 5)
165#define MKW2XDM_IRQSTS2_PI (1 << 4)
166#define MKW2XDM_IRQSTS2_TMRSTATUS (1 << 3)
167#define MKW2XDM_IRQSTS2_PB_ERR_IRQ (1 << 1)
168#define MKW2XDM_IRQSTS2_WAKE_IRQ (1 << 0)
169
170#define MKW2XDM_IRQSTS3_TMR4MSK (1 << 7)
171#define MKW2XDM_IRQSTS3_TMR3MSK (1 << 6)
172#define MKW2XDM_IRQSTS3_TMR2MSK (1 << 5)
173#define MKW2XDM_IRQSTS3_TMR1MSK (1 << 4)
174#define MKW2XDM_IRQSTS3_TMR4IRQ (1 << 3)
175#define MKW2XDM_IRQSTS3_TMR3IRQ (1 << 2)
176#define MKW2XDM_IRQSTS3_TMR2IRQ (1 << 1)
177#define MKW2XDM_IRQSTS3_TMR1IRQ (1 << 0)
178#define MKW2XDM_IRQSTS3_TMR_IRQ_MASK 0xfu
179#define MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT 0x0u
180#define MKW2XDM_IRQSTS3_TMR_IRQ(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT))&MKW2XDM_IRQSTS3_TMR_IRQ_MASK)
181
182#define MKW2XDM_PHY_CTRL1_TMRTRIGEN (1 << 7)
183#define MKW2XDM_PHY_CTRL1_SLOTTED (1 << 6)
184#define MKW2XDM_PHY_CTRL1_CCABFRTX (1 << 5)
185#define MKW2XDM_PHY_CTRL1_RXACKRQD (1 << 4)
186#define MKW2XDM_PHY_CTRL1_AUTOACK (1 << 3)
187#define MKW2XDM_PHY_CTRL1_XCVSEQ_MASK 0x07u
188#define MKW2XDM_PHY_CTRL1_XCVSEQ(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PHY_CTRL1_XCVSEQ_MASK)
189
190#define MKW2XDM_PHY_CTRL2_CRC_MSK (1 << 7)
191#define MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK (1 << 6)
192#define MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK (1 << 5)
193#define MKW2XDM_PHY_CTRL2_RX_WMRK_MSK (1 << 4)
194#define MKW2XDM_PHY_CTRL2_CCAMSK (1 << 3)
195#define MKW2XDM_PHY_CTRL2_RXMSK (1 << 2)
196#define MKW2XDM_PHY_CTRL2_TXMSK (1 << 1)
197#define MKW2XDM_PHY_CTRL2_SEQMSK (1 << 0)
198
199#define MKW2XDM_PHY_CTRL3_TMR4CMP_EN (1 << 7)
200#define MKW2XDM_PHY_CTRL3_TMR3CMP_EN (1 << 6)
201#define MKW2XDM_PHY_CTRL3_TMR2CMP_EN (1 << 5)
202#define MKW2XDM_PHY_CTRL3_TMR1CMP_EN (1 << 4)
203#define MKW2XDM_PHY_CTRL3_PB_ERR_MSK (1 << 1)
204#define MKW2XDM_PHY_CTRL3_WAKE_MSK (1 << 0)
205
206#define MKW2XDM_RX_FRM_LENGTH_MASK 0x7Fu
207
208#define MKW2XDM_PHY_CTRL4_TRCV_MSK (1 << 7)
209#define MKW2XDM_PHY_CTRL4_TC3TMOUT (1 << 6)
210#define MKW2XDM_PHY_CTRL4_PANCORDNTR0 (1 << 5)
211#define MKW2XDM_PHY_CTRL4_CCATYPE_MASK 0x18u
212#define MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT 3
213#define MKW2XDM_PHY_CTRL4_CCATYPE(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT))&MKW2XDM_PHY_CTRL4_CCATYPE_MASK)
214#define MKW2XDM_PHY_CTRL4_TMRLOAD (1 << 2)
215#define MKW2XDM_PHY_CTRL4_PROMISCUOUS (1 << 1)
216#define MKW2XDM_PHY_CTRL4_TC2PRIME_EN (1 << 0)
217
218#define MKW2XDM_SRC_CTRL_INDEX_MASK 0xF0u
219#define MKW2XDM_SRC_CTRL_INDEX_SHIFT 4
220#define MKW2XDM_SRC_CTRL_ACK_FRM_PND (1 << 3)
221#define MKW2XDM_SRC_CTRL_SRCADDR_EN (1 << 2)
222#define MKW2XDM_SRC_CTRL_INDEX_EN (1 << 1)
223#define MKW2XDM_SRC_CTRL_INDEX_DISABLE (1 << 0)
224
225#define MKW2XDM_PLL_INT0_MASK 0x1Fu
226#define MKW2XDM_PLL_INT0_VAL(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PLL_INT0_MASK)
227
228#define MKW2XDM_PA_PWR_MASK 0x1Fu
229#define MKW2XDM_PA_PWR(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PA_PWR_MASK)
230
231#define MKW2XDM_CLK_OUT_EXTEND (1 << 7)
232#define MKW2XDM_CLK_OUT_HIZ (1 << 6)
233#define MKW2XDM_CLK_OUT_SR (1 << 5)
234#define MKW2XDM_CLK_OUT_DS (1 << 4)
235#define MKW2XDM_CLK_OUT_EN (1 << 3)
236#define MKW2XDM_CLK_OUT_DIV_MASK 0x03u
237#define MKW2XDM_CLK_OUT_DIV(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_CLK_OUT_DIV_MASK)
238
239#define MKW2XDM_PWR_MODES_XTAL_READY (1 << 5)
240#define MKW2XDM_PWR_MODES_XTALEN (1 << 4)
241#define MKW2XDM_PWR_MODES_AUTODOZE (1 << 1)
242#define MKW2XDM_PWR_MODES_PMC_MODE (1 << 0)
243
292 MKW2XDMI_BSM_CTRL = 0x32,
293 MKW2XDMI__RNG = 0x34,
294 MKW2XDMI_RX_BYTE_COUNT = 0x35,
295 MKW2XDMI_RX_WTR_MARK = 0x36,
296 MKW2XDMI_SOFT_RESET = 0x37,
297 MKW2XDMI_TXDELAY = 0x38,
298 MKW2XDMI_ACKDELAY = 0x39,
299 MKW2XDMI_SEQ_MGR_CTRL = 0x3A,
300 MKW2XDMI_SEQ_MGR_STS = 0x3B,
301 MKW2XDMI_SEQ_T_STS = 0x3C,
302 MKW2XDMI_ABORT_STS = 0x3D,
303 MKW2XDMI_CCCA_BUSY_CNT = 0x3E,
304 MKW2XDMI_SRC_ADDR_CHECKSUM1 = 0x3F,
305 MKW2XDMI_SRC_ADDR_CHECKSUM2 = 0x40,
306 MKW2XDMI_SRC_TBL_VALID1 = 0x41,
307 MKW2XDMI_SRC_TBL_VALID2 = 0x42,
308 MKW2XDMI_FILTERFAIL_CODE1 = 0x43,
309 MKW2XDMI_FILTERFAIL_CODE2 = 0x44,
310 MKW2XDMI_SLOT_PRELOAD = 0x45,
311 MKW2XDMI_CORR_VT = 0x47,
312 MKW2XDMI_SYNC_CTRL = 0x48,
313 MKW2XDMI_PN_LSB_0 = 0x49,
314 MKW2XDMI_PN_LSB_1 = 0x4A,
315 MKW2XDMI_PN_MSB_0 = 0x4B,
316 MKW2XDMI_PN_MSB_1 = 0x4C,
317 MKW2XDMI_CORR_NVAL = 0x4D,
318 MKW2XDMI_TX_MODE_CTRL = 0x4E,
319 MKW2XDMI_SNF_THR = 0x4F,
320 MKW2XDMI_FAD_THR = 0x50,
322 MKW2XDMI_AGC_THR1 = 0x52,
323 MKW2XDMI_AGC_THR2 = 0x53,
324 MKW2XDMI_AGC_HYS = 0x54,
325 MKW2XDMI_AFC = 0x55,
327 MKW2XDMI_PHY_STS = 0x58,
328 MKW2XDMI_RX_MAX_CORR = 0x59,
329 MKW2XDMI_RX_MAX_PREAMBLE = 0x5A,
330 MKW2XDMI_RSSI = 0x5B,
331 MKW2XDMI_PLL_DIG_CTRL = 0x5E,
332 MKW2XDMI_VCO_CAL = 0x5F,
333 MKW2XDMI_VCO_BEST_DIFF = 0x60,
334 MKW2XDMI_VCO_BIAS = 0x61,
335 MKW2XDMI_KMOD_CTRL = 0x62,
336 MKW2XDMI_KMOD_CAL = 0x63,
337 MKW2XDMI_PA_CAL = 0x64,
338 MKW2XDMI_PA_PWRCAL = 0x65,
339 MKW2XDMI_ATT_RSSI1 = 0x66,
340 MKW2XDMI_ATT_RSSI2 = 0x67,
341 MKW2XDMI_RSSI_OFFSET = 0x68,
342 MKW2XDMI_RSSI_SLOPE = 0x69,
343 MKW2XDMI_RSSI_CAL1 = 0x6A,
344 MKW2XDMI_RSSI_CAL2 = 0x6B,
345 MKW2XDMI_XTAL_CTRL = 0x6E,
346 MKW2XDMI_XTAL_COMP_MIN = 0x6F,
347 MKW2XDMI_XTAL_COMP_MAX = 0x70,
348 MKW2XDMI_XTAL_GM = 0x71,
349 MKW2XDMI_LNA_TUNE = 0x74,
350 MKW2XDMI_LNA_AGCGAIN = 0x75,
351 MKW2XDMI_CHF_PMA_GAIN = 0x78,
352 MKW2XDMI_CHF_IBUF = 0x79,
353 MKW2XDMI_CHF_QBUF = 0x7A,
354 MKW2XDMI_CHF_IRIN = 0x7B,
355 MKW2XDMI_CHF_QRIN = 0x7C,
356 MKW2XDMI_CHF_IL = 0x7D,
357 MKW2XDMI_CHF_QL = 0x7E,
358 MKW2XDMI_CHF_CC1 = 0x7F,
359 MKW2XDMI_CHF_CCL = 0x80,
360 MKW2XDMI_CHF_CC2 = 0x81,
361 MKW2XDMI_CHF_IROUT = 0x82,
362 MKW2XDMI_CHF_QROUT = 0x83,
363 MKW2XDMI_RSSI_CTRL = 0x86,
364 MKW2XDMI_PA_BIAS = 0x89,
365 MKW2XDMI_PA_TUNING = 0x8A,
366 MKW2XDMI_PMC_HP_TRIM = 0x8D,
367 MKW2XDMI_VREGA_TRIM = 0x8E,
368 MKW2XDMI_VCO_CTRL1 = 0x91,
369 MKW2XDMI_VCO_CTRL2 = 0x92,
370 MKW2XDMI_ANA_SPARE_OUT1 = 0x95,
371 MKW2XDMI_ANA_SPARE_OUT2 = 0x96,
372 MKW2XDMI_ANA_SPARE_IN = 0x97,
373 MKW2XDMI_MISCELLANEOUS = 0x98,
374 MKW2XDMI_SEQ_MGR_OVRD0 = 0x9A,
375 MKW2XDMI_SEQ_MGR_OVRD1 = 0x9B,
376 MKW2XDMI_SEQ_MGR_OVRD2 = 0x9C,
377 MKW2XDMI_SEQ_MGR_OVRD3 = 0x9D,
378 MKW2XDMI_SEQ_MGR_OVRD4 = 0x9E,
379 MKW2XDMI_SEQ_MGR_OVRD5 = 0x9F,
380 MKW2XDMI_SEQ_MGR_OVRD6 = 0xA0,
381 MKW2XDMI_SEQ_MGR_OVRD7 = 0xA1,
382 MKW2XDMI_TESTMODE_CTRL = 0xA3,
383 MKW2XDMI_DTM_CTRL1= 0xA4,
384 MKW2XDMI_DTM_CTRL2= 0xA5,
385 MKW2XDMI_ATM_CTRL1= 0xA6,
386 MKW2XDMI_ATM_CTRL2= 0xA7,
387 MKW2XDMI_ATM_CTRL3= 0xA8,
388 MKW2XDMI_LIM_FE_TEST_CTRL = 0xAA,
389 MKW2XDMI_CHF_TEST_CTRL = 0xAB,
390 MKW2XDMI_VCO_TEST_CTRL = 0xAC,
391 MKW2XDMI_PLL_TEST_CTRL = 0xAD,
392 MKW2XDMI_PA_TEST_CTRL = 0xAE,
393 MKW2XDMI_PMC_TEST_CTRL = 0xAF,
394 MKW2XDMI_SCAN_DTM_PROTECT_1 = 0xFE,
395 MKW2XDMI_SCAN_DTM_PROTECT_0 = 0xFF,
396};
397
398#define MKW2XDMI_PART_ID_MANUF_ID_MASK 0x60u
399#define MKW2XDMI_PART_ID_VERSION_MASK 0x1Cu
400#define MKW2XDMI_PART_ID_MASK_SET_MASK 0x07u
401
402#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK 0xC0u
403#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT 6
404#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT))&MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK)
405#define MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS (1 << 5)
406#define MKW2XDMI_RX_FRAME_FILTER_NS_FT (1 << 4)
407#define MKW2XDMI_RX_FRAME_FILTER_CMD_FT (1 << 3)
408#define MKW2XDMI_RX_FRAME_FILTER_ACK_FT (1 << 2)
409#define MKW2XDMI_RX_FRAME_FILTER_DATA_FT (1 << 1)
410#define MKW2XDMI_RX_FRAME_FILTER_BEACON_FT (1 << 0)
411
412#define MKW2XDMI_PLL_INT1_MASK 0x1Fu
413
414#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK 0xF0
415#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT 4
416#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT))&MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK)
417#define MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK (1 << 3)
418#define MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1 (1 << 2)
419#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO (1 << 1)
420#define MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK (1 << 0)
421
422#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1 (1 << 7)
423#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0 (1 << 6)
424#define MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK 0x3Fu
425
426#define MKW2XDMI_CCA_CTRL_AGC_FRZ_EN (1 << 6)
427#define MKW2XDMI_CCA_CTRL_CONT_RSSI_EN (1 << 5)
428#define MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR (1 << 4)
429#define MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR (1 << 3)
430#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI (1 << 2)
431#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED (1 << 1)
432#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1 (1 << 0)
433
434#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK 0x70u
435#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT 4
436#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT))&MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK)
437#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK 0x0Fu
438
439#define MKW2XDMI_TMR_PRESCALE_MASK 0x7u
440#define MKW2XDMI_TMR_PRESCALE_SHIFT 0x0u
441#define MKW2XDMI_TMR_PRESCALE_SET(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_TMR_PRESCALE_SHIFT))&MKW2XDMI_TMR_PRESCALE_MASK)
442
443#define MKW2XDMI_GPIO_DATA8 (1 << 7)
444#define MKW2XDMI_GPIO_DATA7 (1 << 6)
445#define MKW2XDMI_GPIO_DATA6 (1 << 5)
446#define MKW2XDMI_GPIO_DATA5 (1 << 4)
447#define MKW2XDMI_GPIO_DATA4 (1 << 3)
448#define MKW2XDMI_GPIO_DATA3 (1 << 2)
449#define MKW2XDMI_GPIO_DATA2 (1 << 1)
450#define MKW2XDMI_GPIO_DATA1 (1 << 0)
451
452#define MKW2XDMI_GPIO_DIR8 (1 << 7)
453#define MKW2XDMI_GPIO_DIR7 (1 << 6)
454#define MKW2XDMI_GPIO_DIR6 (1 << 5)
455#define MKW2XDMI_GPIO_DIR5 (1 << 4)
456#define MKW2XDMI_GPIO_DIR4 (1 << 3)
457#define MKW2XDMI_GPIO_DIR3 (1 << 2)
458#define MKW2XDMI_GPIO_DIR2 (1 << 1)
459#define MKW2XDMI_GPIO_DIR1 (1 << 0)
460
461#define MKW2XDMI_GPIO_PUL_EN8 (1 << 7)
462#define MKW2XDMI_GPIO_PUL_EN7 (1 << 6)
463#define MKW2XDMI_GPIO_PUL_EN6 (1 << 5)
464#define MKW2XDMI_GPIO_PUL_EN5 (1 << 4)
465#define MKW2XDMI_GPIO_PUL_EN4 (1 << 3)
466#define MKW2XDMI_GPIO_PUL_EN3 (1 << 2)
467#define MKW2XDMI_GPIO_PUL_EN2 (1 << 1)
468#define MKW2XDMI_GPIO_PUL_EN1 (1 << 0)
469
470#define MKW2XDMI_GPIO_PUL_SEL8 (1 << 7)
471#define MKW2XDMI_GPIO_PUL_SEL7 (1 << 6)
472#define MKW2XDMI_GPIO_PUL_SEL6 (1 << 5)
473#define MKW2XDMI_GPIO_PUL_SEL5 (1 << 4)
474#define MKW2XDMI_GPIO_PUL_SEL4 (1 << 3)
475#define MKW2XDMI_GPIO_PUL_SEL3 (1 << 2)
476#define MKW2XDMI_GPIO_PUL_SEL2 (1 << 1)
477#define MKW2XDMI_GPIO_PUL_SEL1 (1 << 0)
478
479#define MKW2XDMI_GPIO_DS8 (1 << 7)
480#define MKW2XDMI_GPIO_DS7 (1 << 6)
481#define MKW2XDMI_GPIO_DS6 (1 << 5)
482#define MKW2XDMI_GPIO_DS5 (1 << 4)
483#define MKW2XDMI_GPIO_DS4 (1 << 3)
484#define MKW2XDMI_GPIO_DS3 (1 << 2)
485#define MKW2XDMI_GPIO_DS2 (1 << 1)
486#define MKW2XDMI_GPIO_DS1 (1 << 0)
487
488#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3 (1 << 7)
489#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL2 (1 << 6)
490#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL1 (1 << 5)
491#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL0 (1 << 4)
492#define MKW2XDMI_ANT_PAD_CTRL_ANTX_CTRLMODE (1 << 3)
493#define MKW2XDMI_ANT_PAD_CTRL_ANTX_HZ (1 << 2)
494#define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK 0x03u
495#define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK)
496
497#define MKW2XDMI_MISC_PAD_CTRL_MISO_HIZ_EN (1 << 3)
498#define MKW2XDMI_MISC_PAD_CTRL_IRQ_B_OD (1 << 2)
499#define MKW2XDMI_MISC_PAD_CTRL_NON_GPIO_DS (1 << 1)
500#define MKW2XDMI_MISC_PAD_CTRL_ANTX_CURR (1 << 0)
501
502#define MKW2XDMI_ANT_AGC_CTRL_SNF_EN (1 << 7)
503#define MKW2XDMI_ANT_AGC_CTRL_AGC_EN (1 << 6)
504#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK 0x30u
505#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT 4
506#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT))&MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK)
507#define MKW2XDMI_ANT_AGC_CTRL_ANTX (1 << 1)
508#define MKW2XDMI_ANT_AGC_CTRL_AD_EN (1 << 0)
509
510#define MKW2XDMI_LPPS_CTRL_LPPS_EN (1 << 0)
511
512#define MKW2XDMI_SOFT_RESET_SOG_RST (1 << 7)
513#define MKW2XDMI_SOFT_RESET_REGS_RST (1 << 4)
514#define MKW2XDMI_SOFT_RESET_PLL_RST (1 << 3)
515#define MKW2XDMI_SOFT_RESET_TX_RST (1 << 2)
516#define MKW2XDMI_SOFT_RESET_RX_RST (1 << 1)
517#define MKW2XDMI_SOFT_RESET_SEQ_MGR_RST (1 << 0)
518
519#define MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK 0x3
520#define MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT 6
521#define MKW2XDMI_SEQ_MGR_CTRL_NO_RX_RECYCLE (1 << 5)
522#define MKW2XDMI_SEQ_MGR_CTRL_LATCH_PREAMBLE (1 << 4)
523#define MKW2XDMI_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1 << 3)
524#define MKW2XDMI_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1 << 2)
525#define MKW2XDMI_SEQ_MGR_CTRL_PSM_LOCK_DIS (1 << 1)
526#define MKW2XDMI_SEQ_MGR_CTRL_PLL_ABORT_OVRD (1 << 0)
527
528#define MKW2XDMI_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1 << 7)
529#define MKW2XDMI_SEQ_MGR_STS_RX_MODE (1 << 6)
530#define MKW2XDMI_SEQ_MGR_STS_RX_TIMEOUT_PENDING (1 << 5)
531#define MKW2XDMI_SEQ_MGR_STS_NEW_SEQ_INHIBIT (1 << 4)
532#define MKW2XDMI_SEQ_MGR_STS_SEQ_IDLE (1 << 3)
533#define MKW2XDMI_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK 7
534
535#define MKW2XDMI_ABORT_STS_PLL_ABORTED (1 << 2)
536#define MKW2XDMI_ABORT_STS_TC3_ABORTED (1 << 1)
537#define MKW2XDMI_ABORT_STS_SW_ABORTED (1 << 0)
538
539#define MKW2XDMI_TESTMODE_CTRL_HOT_ANT (1 << 4)
540#define MKW2XDMI_TESTMODE_CTRL_IDEAL_RSSI_EN (1 << 3)
541#define MKW2XDMI_TESTMODE_CTRL_IDEAL_PFC_EN (1 << 2)
542#define MKW2XDMI_TESTMODE_CTRL_CONTINUOUS_EN (1 << 1)
543#define MKW2XDMI_TESTMODE_CTRL_FPGA_EN (1 << 0)
544
545#define MKW2XDMI_DTM_CTRL1_ATM_LOCKED (1 << 7)
546#define MKW2XDMI_DTM_CTRL1_DTM_EN (1 << 6)
547#define MKW2XDMI_DTM_CTRL1_PAGE5 (1 << 5)
548#define MKW2XDMI_DTM_CTRL1_PAGE4 (1 << 4)
549#define MKW2XDMI_DTM_CTRL1_PAGE3 (1 << 3)
550#define MKW2XDMI_DTM_CTRL1_PAGE2 (1 << 2)
551#define MKW2XDMI_DTM_CTRL1_PAGE1 (1 << 1)
552#define MKW2XDMI_DTM_CTRL1_PAGE0 (1 << 0)
553
554#define MKW2XDMI_TX_MODE_CTRL_TX_INV (1 << 4)
555#define MKW2XDMI_TX_MODE_CTRL_BT_EN (1 << 3)
556#define MKW2XDMI_TX_MODE_CTRL_DTS2 (1 << 2)
557#define MKW2XDMI_TX_MODE_CTRL_DTS1 (1 << 1)
558#define MKW2XDMI_TX_MODE_CTRL_DTS0 (1 << 0)
559#define MKW2XDMI_TX_MODE_CTRL_DTS_MASK 7
560
561#ifdef __cplusplus
562}
563#endif
564
mkw2xdrf_dregister
Definition kw2xrf_reg.h:88
@ MKW2XDM_IAR_INDEX
IAR Index.
Definition kw2xrf_reg.h:149
@ MKW2XDM_TIMESTAMP_LSB
Timestamp LSB.
Definition kw2xrf_reg.h:104
@ MKW2XDM_T4CMP_LSB
Timer 4 Compare Value LSB.
Definition kw2xrf_reg.h:118
@ MKW2XDM_T4CMP_USB
Timer 4 Compare Value USB.
Definition kw2xrf_reg.h:120
@ MKW2XDM_PHY_CTRL4
PHY Control 4.
Definition kw2xrf_reg.h:96
@ MKW2XDM_T1CMP_MSB
Timer 1 Compare Value MSB.
Definition kw2xrf_reg.h:113
@ MKW2XDM_EVENT_TIMER_MSB
Event Timer MSB.
Definition kw2xrf_reg.h:102
@ MKW2XDM_TIMESTAMP_USB
Timestamp USB.
Definition kw2xrf_reg.h:106
@ MKW2XDM_SRC_CTRL
SRC Control.
Definition kw2xrf_reg.h:97
@ MKW2XDM_CCA1_ED_FNL
CCA1 ED FNL.
Definition kw2xrf_reg.h:100
@ MKW2XDM_T2PRIMECMP_LSB
Timer 2-Prime Compare Value LSB.
Definition kw2xrf_reg.h:110
@ MKW2XDM_T4CMP_MSB
Timer 4 Compare Value MSB.
Definition kw2xrf_reg.h:119
@ MKW2XDM_SEQ_STATE
Sequence Manager State.
Definition kw2xrf_reg.h:125
@ MKW2XDM_LQI_VALUE
Link Quality Indicator.
Definition kw2xrf_reg.h:126
@ MKW2XDM_EVENT_TIMER_USB
Event Timer USB.
Definition kw2xrf_reg.h:103
@ MKW2XDM_RX_FRM_LEN
Receive Frame Length.
Definition kw2xrf_reg.h:95
@ MKW2XDM_T3CMP_MSB
Timer 3 Compare Value MSB.
Definition kw2xrf_reg.h:108
@ MKW2XDM_SRC_ADDRS_SUM_LSB
SRC Address SUM LSB.
Definition kw2xrf_reg.h:98
@ MKW2XDM_PWR_MODES
Power Modes.
Definition kw2xrf_reg.h:148
@ MKW2XDM_IRQSTS1
Interrupt Request Status 1.
Definition kw2xrf_reg.h:89
@ MKW2XDM_EVENT_TIMER_LSB
Event Timer LSB.
Definition kw2xrf_reg.h:101
@ MKW2XDM_IRQSTS3
Interrupt Request Status 3.
Definition kw2xrf_reg.h:91
@ MKW2XDM_PLL_INT0
PLL Integer Value for PAN0.
Definition kw2xrf_reg.h:121
@ MKW2XDM_PHY_CTRL3
PHY Control 3.
Definition kw2xrf_reg.h:94
@ MKW2XDM_PLL_FRAC0_LSB
PLL Frequency Fractional Value for PAN0.
Definition kw2xrf_reg.h:122
@ MKW2XDM_T3CMP_LSB
Timer 3 Compare Value LSB.
Definition kw2xrf_reg.h:107
@ MKW2XDM_T1CMP_USB
Timer 1 Compare Value USB.
Definition kw2xrf_reg.h:114
@ MKW2XDM_T3CMP_USB
Timer 3 Compare Value USB.
Definition kw2xrf_reg.h:109
@ MKW2XDM_TIMESTAMP_MSB
Timestamp MSB.
Definition kw2xrf_reg.h:105
@ MKW2XDM_OVERWRITE_VER
Overwrite Version Number.
Definition kw2xrf_reg.h:146
@ MKW2XDM_RSSI_CCA_CNT
RSSI CCA CNT.
Definition kw2xrf_reg.h:127
@ MKW2XDM_PHY_CTRL1
PHY Control 1.
Definition kw2xrf_reg.h:92
@ MKW2XDM_PLL_FRAC0_MSB
PLL Frequency Fractional Value for PAN0.
Definition kw2xrf_reg.h:123
@ MKW2XDM_SRC_ADDRS_SUM_MSB
SRC Address SUM MSB.
Definition kw2xrf_reg.h:99
@ MKW2XDM_T2PRIMECMP_MSB
Timer 2-Prime Compare Value MSB.
Definition kw2xrf_reg.h:111
@ MKW2XDM_T2CMP_USB
Timer 2 Compare Value USB.
Definition kw2xrf_reg.h:117
@ MKW2XDM_IRQSTS2
Interrupt Request Status 2.
Definition kw2xrf_reg.h:90
@ MKW2XDM_T1CMP_LSB
Timer 1 Compare Value LSB.
Definition kw2xrf_reg.h:112
@ MKW2XDM_CLK_OUT_CTRL
CLK_OUT Control.
Definition kw2xrf_reg.h:147
@ MKW2XDM_IAR_DATA
IAR Data.
Definition kw2xrf_reg.h:150
@ MKW2XDM_PHY_CTRL2
PHY Control 2.
Definition kw2xrf_reg.h:93
@ MKW2XDM_T2CMP_LSB
Timer 2 Compare Value LSB.
Definition kw2xrf_reg.h:115
@ MKW2XDM_T2CMP_MSB
Timer 2 Compare Value MSB.
Definition kw2xrf_reg.h:116
kw2xrf_physeq_t
Transceiver Sequence Selector, define Values for XCVSEQ.
Definition kw2xrf_reg.h:78
mkw2xdrf_iregister
Definition kw2xrf_reg.h:244
@ MKW2XDMI_MACLONGADDRS1_6
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:273
@ MKW2XDMI_MACPANID1_LSB
Frequency Fractional Value for PAN1.
Definition kw2xrf_reg.h:263
@ MKW2XDMI_PLL_FRAC1_MSB
Frequency Fractional Value for PAN1.
Definition kw2xrf_reg.h:262
@ MKW2XDMI_MACSHORTADDRS0_MSB
MAC Short Address for PAN0.
Definition kw2xrf_reg.h:250
@ MKW2XDMI_LPPS_CTRL
LPPS_CTRL.
Definition kw2xrf_reg.h:326
@ MKW2XDMI_MACSHORTADDRS0_LSB
MAC Short Address for PAN0.
Definition kw2xrf_reg.h:249
@ MKW2XDMI_MACPANID0_MSB
MAC PAN ID for PAN0.
Definition kw2xrf_reg.h:248
@ MKW2XDMI_CCA1_THRESH
Clear Channel Assessment 1 Threshold.
Definition kw2xrf_reg.h:278
@ MKW2XDMI_MACLONGADDRS0_5
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:256
@ MKW2XDMI_MACLONGADDRS1_7
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:274
@ MKW2XDMI_ANT_AGC_CTRL
Antenna AGC and FAD Control.
Definition kw2xrf_reg.h:321
@ MKW2XDMI_CCA2_CORR_PEAKS
Clear Channel Assessment 2 Threshold Peak Compare.
Definition kw2xrf_reg.h:282
@ MKW2XDMI_PLL_INT1
Frequency Integer for PAN1.
Definition kw2xrf_reg.h:260
@ MKW2XDMI_GPIO_SEL
GPIO Pullup Select.
Definition kw2xrf_reg.h:288
@ MKW2XDMI_MACLONGADDRS0_3
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:254
@ MKW2XDMI_MACLONGADDRS0_6
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:257
@ MKW2XDMI_DUAL_PAN_CTRL
Dual PAN Control.
Definition kw2xrf_reg.h:275
@ MKW2XDMI_DUAL_PAN_DWELL
Channel Frequency Dwell Time.
Definition kw2xrf_reg.h:276
@ MKW2XDMI_MISC_PAD_CTRL
Miscellaneous Pad Control.
Definition kw2xrf_reg.h:291
@ MKW2XDMI_CCA1_ED_OFFSET_COMP
Clear Channel Assessment / ED Offset Computation.
Definition kw2xrf_reg.h:279
@ MKW2XDMI_MACLONGADDRS1_4
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:271
@ MKW2XDMI_CCA2_THRESH
Clear Channel Assessment 2 Threshold.
Definition kw2xrf_reg.h:283
@ MKW2XDMI_MACSHORTADDRS1_MSB
MAC Short Address for PAN1.
Definition kw2xrf_reg.h:266
@ MKW2XDMI_MACLONGADDRS1_5
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:272
@ MKW2XDMI_MACSHORTADDRS1_LSB
MAC Short Address for PAN1.
Definition kw2xrf_reg.h:265
@ MKW2XDMI_MACLONGADDRS1_2
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:269
@ MKW2XDMI_MACLONGADDRS1_3
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:270
@ MKW2XDMI_MACPANID1_MSB
Frequency Fractional Value for PAN1.
Definition kw2xrf_reg.h:264
@ MKW2XDMI_CCA_CTRL
CCA Control.
Definition kw2xrf_reg.h:281
@ MKW2XDMI_PART_ID
Part Identification.
Definition kw2xrf_reg.h:245
@ MKW2XDMI_XTAL_TRIM
XTAL 32 MHz Trim.
Definition kw2xrf_reg.h:246
@ MKW2XDMI_MACLONGADDRS0_1
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:252
@ MKW2XDMI_GPIO_PUL_EN
GPIO Pullup Enable.
Definition kw2xrf_reg.h:287
@ MKW2XDMI_DUAL_PAN_STS
Dual PAN Status.
Definition kw2xrf_reg.h:277
@ MKW2XDMI_TMR_PRESCALE
Event Timer Time Base.
Definition kw2xrf_reg.h:284
@ MKW2XDMI_GPIO_DIR
GPIO Direction Control.
Definition kw2xrf_reg.h:286
@ MKW2XDMI_PLL_FRAC1_LSB
Frequency Fractional Value for PAN1.
Definition kw2xrf_reg.h:261
@ MKW2XDMI_LQI_OFFSET_COMP
LQI Offset Computation.
Definition kw2xrf_reg.h:280
@ MKW2XDMI_MACLONGADDRS0_2
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:253
@ MKW2XDMI_GPIO_DATA
GPIO Data.
Definition kw2xrf_reg.h:285
@ MKW2XDMI_MACLONGADDRS0_7
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:258
@ MKW2XDMI_RX_FRAME_FILTER
Receive Frame Filter.
Definition kw2xrf_reg.h:259
@ MKW2XDMI_MACLONGADDRS1_1
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:268
@ MKW2XDMI_MACLONGADDRS0_4
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:255
@ MKW2XDMI_MACLONGADDRS0_0
MAC Long Address for PAN0.
Definition kw2xrf_reg.h:251
@ MKW2XDMI_ANT_PAD_CTRL
Antenna Control.
Definition kw2xrf_reg.h:290
@ MKW2XDMI_GPIO_DS
GPIO Drive Strength.
Definition kw2xrf_reg.h:289
@ MKW2XDMI_MACLONGADDRS1_0
MAC Long Address for PAN1.
Definition kw2xrf_reg.h:267
@ MKW2XDMI_MACPANID0_LSB
MAC PAN ID for PAN0.
Definition kw2xrf_reg.h:247