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board.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Thomas Stilwell <stilwellt@openlabs.co>
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "cpu.h"
20#include "periph_conf.h"
21
22#ifdef __cplusplus
23extern "C"
24{
25#endif
26
27/*
28 * NMI shares a pin with DAC output and ADC input. Holding the pin low during
29 * reset will cause a hang unless NMI is disabled. It can be enabled in
30 * applications where the pin is not held low during reset.
31 */
32#define KINETIS_FOPT 0xFB /* disable NMI (0xFF to enable) */
33
38#define LED0_PIN GPIO_PIN(PORT_B, 0)
39#define LED0_MASK (1 << 0)
40#define LED0_ON (GPIOB->PCOR = LED0_MASK)
41#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
42#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
44
49#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
50/* PIT xtimer configuration */
51#define XTIMER_DEV (TIMER_PIT_DEV(0))
52#define XTIMER_CHAN (0)
53/* Default xtimer settings should work on the PIT */
54#else
55/* LPTMR xtimer configuration */
56#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
57#define XTIMER_CHAN (0)
58/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
59#define XTIMER_WIDTH (16)
60#define XTIMER_BACKOFF (16)
61#define XTIMER_ISR_BACKOFF (5)
62#define XTIMER_HZ (32768ul)
63#endif
65
71#ifndef PTB3_OUTPUT_OSC32K
72#define PTB3_OUTPUT_OSC32K (0)
73#endif
74
80#ifndef PTB3_OUTPUT_OSCERCLK
81#define PTB3_OUTPUT_OSCERCLK (0)
82#endif
83
84#ifdef __cplusplus
85}
86#endif
87