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cpu_conf.h
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/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#include "vendor/QN908XC.h"
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#include "vendor/QN908XC_features.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (NUMBER_OF_INT_VECTORS - 16)
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#define CPU_FLASH_BASE (QN908X_ROM_START_ADDR)
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#define CPU_HAS_BITBAND 1
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#if !defined(CONFIG_BOARD_HAS_XTAL32K) || DOXYGEN
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#define CONFIG_BOARD_HAS_XTAL32K 0
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#endif
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#ifdef DOXYGEN
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#define CONFIG_CPU_CLK_32K_XTAL
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#define CONFIG_CPU_CLK_32K_RCO
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#endif
/* def DOXYGEN */
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/* Default 32K clock selector config. */
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#if !defined(CONFIG_CPU_CLK_32K_XTAL) && !defined(CONFIG_CPU_CLK_32K_RCO)
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#if CONFIG_BOARD_HAS_XTAL32K
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#define CONFIG_CPU_CLK_32K_XTAL 1
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#else
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#define CONFIG_CPU_CLK_32K_RCO 1
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#endif
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#endif
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#ifndef CONFIG_BOARD_HAS_XTAL
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#define CONFIG_BOARD_HAS_XTAL 0
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#endif
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#ifdef DOXYGEN
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#define CONFIG_CPU_CLK_XTAL_16M
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#define CONFIG_CPU_CLK_XTAL_32M
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#endif
/* def DOXYGEN */
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/* Default XTAL setting. */
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#if CONFIG_BOARD_HAS_XTAL && \
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!defined(CONFIG_BOARD_HAS_XTAL_16M) && !defined(CONFIG_BOARD_HAS_XTAL_32M)
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#define CONFIG_BOARD_HAS_XTAL_32M 1
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#endif
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#ifndef CONFIG_CPU_CLK_OSC32M_DIV
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#define CONFIG_CPU_CLK_OSC32M_DIV 0
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#endif
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#ifndef CONFIG_CPU_CLK_XTAL_DIV
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#define CONFIG_CPU_CLK_XTAL_DIV 0
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#endif
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#ifdef DOXYGEN
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#define CONFIG_CPU_CLK_SYS_XTAL
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#define CONFIG_CPU_CLK_SYS_OSC32M
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#define CONFIG_CPU_CLK_SYS_32K
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#endif
/* def DOXYGEN */
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/* Default system clock configuration selector */
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#if !defined(CONFIG_CPU_CLK_SYS_XTAL) && !defined(CONFIG_CPU_CLK_SYS_OSC32M) && \
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!defined(CONFIG_CPU_CLK_SYS_32K)
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#if CONFIG_BOARD_HAS_XTAL
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#define CONFIG_CPU_CLK_SYS_XTAL 1
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#else
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#define CONFIG_CPU_CLK_SYS_OSC32M 1
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#endif
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#endif
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#ifndef CONFIG_CPU_CLK_AHB_DIV
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#define CONFIG_CPU_CLK_AHB_DIV 1u
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#endif
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#ifndef CONFIG_CPU_CLK_APB_DIV
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#define CONFIG_CPU_CLK_APB_DIV 1u
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#endif
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#define QN908X_CRP_PROTECT_PAGES(X) (255 - (X))
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#define QN908X_CRP_MASS_ERASE_ALLOW (0x800)
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#define QN908X_CRP_MASS_ERASE_DISALLOW (0x400)
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#define QN908X_CRP_PAGE_ERASE_WRITE_ALLOW (0x2000)
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#define QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW (0x1000)
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#define QN908X_CRP_FLASH_READ_ALLOW (0x8000)
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#define QN908X_CRP_FLASH_READ_DISALLOW (0x4000)
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#define QN908X_CRP_ISP_ENTRY_ALLOW (0x20000)
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#define QN908X_CRP_ISP_ENTRY_DISALLOW (0x10000)
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#define QN908X_CRP_EXTERNAL_ACCESS_ALLOW (0x80000)
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#define QN908X_CRP_EXTERNAL_ACCESS_DISALLOW (0x40000)
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#ifndef QN908X_CRP
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#define QN908X_CRP \
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(QN908X_CRP_PROTECT_PAGES(0) \
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| QN908X_CRP_MASS_ERASE_ALLOW \
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| QN908X_CRP_PAGE_ERASE_WRITE_ALLOW \
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| QN908X_CRP_FLASH_READ_ALLOW \
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| QN908X_CRP_ISP_ENTRY_ALLOW \
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| QN908X_CRP_EXTERNAL_ACCESS_ALLOW)
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#endif
/* QN908X_CRP */
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#define CORTEXM_VECTOR_RESERVED_0X20 QN908X_CRP
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/* Safety checks that the QN908X_CRP value is valid. */
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#if !(QN908X_CRP & QN908X_CRP_MASS_ERASE_ALLOW) == \
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!(QN908X_CRP & QN908X_CRP_MASS_ERASE_DISALLOW)
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#error "Must select exactly one of QN908X_CRP_MASS_ERASE_* in the QN908X_CRP"
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#endif
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#if !(QN908X_CRP & QN908X_CRP_PAGE_ERASE_WRITE_ALLOW) == \
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!(QN908X_CRP & QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW)
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#error \
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"Must select exactly one of QN908X_CRP_PAGE_ERASE_WRITE_* in the QN908X_CRP"
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#endif
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#if !(QN908X_CRP & QN908X_CRP_FLASH_READ_ALLOW) == \
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!(QN908X_CRP & QN908X_CRP_FLASH_READ_DISALLOW)
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#error "Must select exactly one of QN908X_CRP_FLASH_READ_* in the QN908X_CRP"
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#endif
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#if !(QN908X_CRP & QN908X_CRP_ISP_ENTRY_ALLOW) == \
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!(QN908X_CRP & QN908X_CRP_ISP_ENTRY_DISALLOW)
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#error "Must select exactly one of QN908X_CRP_ISP_ENTRY_* in the QN908X_CRP"
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#endif
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#if !(QN908X_CRP & QN908X_CRP_EXTERNAL_ACCESS_ALLOW) == \
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!(QN908X_CRP & QN908X_CRP_EXTERNAL_ACCESS_DISALLOW)
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#error \
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"Must select exactly one of QN908X_CRP_EXTERNAL_ACCESS_* in the QN908X_CRP"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
/* CPU_CONF_H */
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