CPU specific definitions for internal peripheral handling. More...

Detailed Description

CPU specific definitions for internal peripheral handling.

Author: iosabi iosab.nosp@m.i@pr.nosp@m.otonm.nosp@m.ail..nosp@m.com

Definition in file periph_cpu.h.

#include <stdint.h>
#include <stdbool.h>
#include "cpu.h"

Include dependency graph for periph_cpu.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	i2c_conf_t
	I2C configuration structure. More...

struct	uart_conf_t
	UART device configuration. More...

Macros
#define	GPIO_UNDEF (0xffff)
	Definition of a fitting UNDEF value.

#define	GPIO_PIN(x, y) (((x) << 12u) \| (y))
	Define a CPU specific GPIO pin generator macro.

#define	CPUID_ADDR (FSL_FEATURE_FLASH_ADDR_OF_VENDOR_BD_ADDR)
	Starting offset of CPU_ID.

#define	CPUID_LEN (6U)
	Length of the CPU_ID in octets.

#define	WDT_HAS_STOP (1)
	Watchdog clock can be stopped independently of other clocks.

#define	GPIO_MODE(open_drain, out_enabled, pull_mode) ((open_drain) \| ((out_enabled) << 1) \| ((pull_mode) << 4))
	Generate GPIO mode bitfields.

#define	QN908X_ADC_CLOCK
	Selected ADC oversample clock.

#define	ADC_VREF_GAIN_X15 (0x100u)
	ADC Vref x1.5 multiplier flag.

#define	ADC_PGA_ENABLE (0x08u)
	ADC PGA Enabled flag.

#define	UART_INVALID_MODE (0x80)
	Invalid UART mode mask.

Typedefs
typedef uint16_t	adc_conf_t
	CPU specific ADC configuration.

Enumerations
enum	{ PORT_A = 0 , PORT_B = 1 , GPIO_PORTS_NUMOF }
	Available ports on the QN908x. More...

enum	qn908x_adc_clock_t { ADC_CLOCK_4M , ADC_CLOCK_2M , ADC_CLOCK_1M , ADC_CLOCK_500K , ADC_CLOCK_250K , ADC_CLOCK_125K , ADC_CLOCK_62K5 , ADC_CLOCK_31K25 , ADC_CLOCK_32K }
	ADC oversample clock configuration. More...

enum	qn908x_adc_channel_t { ADC_CHANNEL_ADC0_ADC1 = 0u << 9u , ADC_CHANNEL_ADC2_ADC3 = 1u << 9u , ADC_CHANNEL_ADC4_ADC5 = 2u << 9u , ADC_CHANNEL_ADC6_ADC7 = 3u << 9u , ADC_CHANNEL_ADC0_VINN = 4u << 9u , ADC_CHANNEL_ADC1_VINN = 5u << 9u , ADC_CHANNEL_ADC2_VINN = 6u << 9u , ADC_CHANNEL_ADC3_VINN = 7u << 9u , ADC_CHANNEL_ADC4_VINN = 8u << 9u , ADC_CHANNEL_ADC5_VINN = 9u << 9u , ADC_CHANNEL_ADC6_VINN = 10u << 9u , ADC_CHANNEL_ADC7_VINN = 11u << 9u , ADC_CHANNEL_TEMP = 13u << 9u , ADC_CHANNEL_VCC4_VINN = 14u << 9u , ADC_CHANNEL_VINN_VINN = 15u << 9u , ADC_CHANNEL_VINN_VSS = 20u << 9u }
	ADC channel pair configuration. More...

enum	qn908x_adc_vref_t { ADC_VREF_1V2 = 0x0000u , ADC_VREF_VREF = 0x4000u , ADC_VREF_VEXT = 0x8000u , ADC_VREF_VCC = 0xC000u }
	ADC Vref configuration. More...

enum	qn908x_adc_vinn_t { ADC_VINN_VREF = 0x30u , ADC_VINN_VREF_3_4 = 0x20u , ADC_VINN_VREF_2 = 0x10u , ADC_VINN_AVSS = 0x00u }
	ADC Vinn configuration. More...

enum	qn908x_adc_gain_t { ADC_GAIN_X05 = 0x40u , ADC_GAIN_X1 = 0x00u , ADC_GAIN_X15 = 0xC0u , ADC_GAIN_X20 = 0x80u }
	ADC SD Gain configuration. More...

CPU specific gpio_t type definition
#define	HAVE_GPIO_T

typedef uint16_t	gpio_t

WDT upper and lower bound times in ms
#define	NWDT_TIME_LOWER_LIMIT (1U)
	The WDT clock can run up to 16MHz (via CLK_APB) and the WDT counter is 32-bit so the maximum value in ms we can wait is ((1 << 32) - 1) / 16000.

#define	NWDT_TIME_UPPER_LIMIT (268435U)

#define	WWDT_TIME_LOWER_LIMIT (1U)

#define	WWDT_TIME_UPPER_LIMIT (268435U)

ADC CPU configuration
#define	BOARD_HAS_ADC_PA06_CAP
	Define if ADC external capacitor is connected to PA06 pin.

#define	TIMER_CHANNEL_NUMOF (4)
	CPU specific timer Counter/Timers (CTIMER) configuration.

#define	TIMER_MAX_VALUE (0xffffffff)

#define	PERIPH_TIMER_PROVIDES_SET 1
	The nRF5x periph_timer implements timer_set()

#define	HAVE_I2C_SPEED_T
	I2C bus speed values in kbit/s.

enum	i2c_speed_t { I2C_SPEED_LOW = 10000u , I2C_SPEED_NORMAL = 100000u , I2C_SPEED_FAST = 400000u , I2C_SPEED_FAST_PLUS = 400000u , I2C_SPEED_HIGH = 400000u }

Define macros for sda and scl pins.
#define	i2c_pin_sda(dev) i2c_config[dev].pin_sda

#define	i2c_pin_scl(dev) i2c_config[dev].pin_scl

#define	PERIPH_SPI_NEEDS_TRANSFER_BYTE
	Use some common SPI functions.

#define	PERIPH_SPI_NEEDS_TRANSFER_REG

#define	PERIPH_SPI_NEEDS_TRANSFER_REGS

#define	HAVE_UART_PARITY_T

enum	uart_parity_t { UART_PARITY_NONE = 0 , UART_PARITY_EVEN = 2 , UART_PARITY_ODD = 3 , UART_PARITY_MARK = 0x10 \| UART_INVALID_MODE , UART_PARITY_SPACE = 0x20 \| UART_INVALID_MODE }
	Definition of possible parity modes. More...

#define	HAVE_UART_DATA_BITS_T

enum	uart_data_bits_t { UART_DATA_BITS_5 = 0x10 \| UART_INVALID_MODE , UART_DATA_BITS_6 = 0x20 \| UART_INVALID_MODE , UART_DATA_BITS_7 = 0 , UART_DATA_BITS_8 = 1 }
	Definition of possible data bits lengths in a UART frame. More...

#define	HAVE_UART_STOP_BITS_T

enum	uart_stop_bits_t { UART_STOP_BITS_1 = 0 , UART_STOP_BITS_2 = 1 }
	Definition of possible stop bits lengths. More...

Macro Definition Documentation

◆ ADC_PGA_ENABLE

#define ADC_PGA_ENABLE (0x08u)

ADC PGA Enabled flag.

Flag to enable the Programmable Gain Amplifier (PGA) with a gain of 1x. This is only useful if the source signal doesn't have any driving capability since the gain is set to 1x. The hardware supports other gain combinations but those are not supported by the driver.

Note: this value is defined as the inverse of ADC_CFG_PGA_BP_MASK which is defined if the PGA is bypassed.

Definition at line 280 of file periph_cpu.h.

◆ ADC_VREF_GAIN_X15

#define ADC_VREF_GAIN_X15 (0x100u)

ADC Vref x1.5 multiplier flag.

Note, this is the same value as ADC_CFG_VREF_GAIN_MASK. When enabled the Vref voltage will be multiplied by 1.5x.

Definition at line 267 of file periph_cpu.h.

◆ BOARD_HAS_ADC_PA06_CAP

#define BOARD_HAS_ADC_PA06_CAP

Define if ADC external capacitor is connected to PA06 pin.

The ADC block can use an external capacitor to better stabilize the reference voltage. This capacitor is optional, but if it is present on the board this macro should be defined by the board to make the ADC block use it.

Definition at line 156 of file periph_cpu.h.

◆ CPUID_ADDR

#define CPUID_ADDR (FSL_FEATURE_FLASH_ADDR_OF_VENDOR_BD_ADDR)

Starting offset of CPU_ID.

Definition at line 61 of file periph_cpu.h.

◆ CPUID_LEN

#define CPUID_LEN (6U)

Length of the CPU_ID in octets.

Definition at line 66 of file periph_cpu.h.

◆ GPIO_MODE

#define GPIO_MODE	(	open_drain,
		out_enabled,
		pull_mode
	)	((open_drain) \| ((out_enabled) << 1) \| ((pull_mode) << 4))

Generate GPIO mode bitfields.

The GPIO_MODE has the following structure:

bit 0: open-drain: 1 for enabled (open-drain mode) and 0 for disabled.
bit 1: output-enabled: 1 output mode, 0 input mode.
bit 4-5: pull_mode: 0 for hi-z (no pull-up or down), 1 for pull-down and 2 for pull-up. These correspond to the IOCON_MODE macros.

Definition at line 99 of file periph_cpu.h.

◆ GPIO_PIN

#define GPIO_PIN	(	x,
		y
	)	(((x) << 12u) \| (y))

Define a CPU specific GPIO pin generator macro.

This generates the GPIO port base address with a mask of the GPIO_PIN value to avoid a memory access. The value 12 here is selected as an optimization to be able to derive the GPIO port address with a simple mask of the GPIO_PIN value.

Definition at line 52 of file periph_cpu.h.

◆ GPIO_UNDEF

#define GPIO_UNDEF (0xffff)

Definition of a fitting UNDEF value.

Definition at line 42 of file periph_cpu.h.

◆ HAVE_GPIO_T

#define HAVE_GPIO_T

Definition at line 35 of file periph_cpu.h.

◆ HAVE_I2C_SPEED_T

#define HAVE_I2C_SPEED_T

I2C bus speed values in kbit/s.

Note: We support arbitrary speed values up to 400 kbit/s.

Definition at line 351 of file periph_cpu.h.

◆ HAVE_UART_DATA_BITS_T

#define HAVE_UART_DATA_BITS_T

Definition at line 525 of file periph_cpu.h.

◆ HAVE_UART_PARITY_T

#define HAVE_UART_PARITY_T

Definition at line 509 of file periph_cpu.h.

◆ HAVE_UART_STOP_BITS_T

#define HAVE_UART_STOP_BITS_T

Definition at line 538 of file periph_cpu.h.

◆ i2c_pin_scl

#define i2c_pin_scl ( dev ) i2c_config[dev].pin_scl

Definition at line 386 of file periph_cpu.h.

◆ i2c_pin_sda

#define i2c_pin_sda ( dev ) i2c_config[dev].pin_sda

Definition at line 385 of file periph_cpu.h.

◆ NWDT_TIME_LOWER_LIMIT

#define NWDT_TIME_LOWER_LIMIT (1U)

The WDT clock can run up to 16MHz (via CLK_APB) and the WDT counter is 32-bit so the maximum value in ms we can wait is ((1 << 32) - 1) / 16000.

TODO: A much larger limit (~1.5 days) can be set if the WDT runs from the 32 KHz clock. However, this is likely decided by the board and depends on the clocks installed on the board. Figure out a way to configure this limit based on the clock used.

Definition at line 84 of file periph_cpu.h.

◆ NWDT_TIME_UPPER_LIMIT

#define NWDT_TIME_UPPER_LIMIT (268435U)

Definition at line 85 of file periph_cpu.h.

◆ PERIPH_I2C_NEED_READ_REG

#define PERIPH_I2C_NEED_READ_REG

Definition at line 375 of file periph_cpu.h.

◆ PERIPH_I2C_NEED_READ_REGS

#define PERIPH_I2C_NEED_READ_REGS

Definition at line 376 of file periph_cpu.h.

◆ PERIPH_I2C_NEED_WRITE_REG

#define PERIPH_I2C_NEED_WRITE_REG

Definition at line 377 of file periph_cpu.h.

◆ PERIPH_I2C_NEED_WRITE_REGS

#define PERIPH_I2C_NEED_WRITE_REGS

Definition at line 378 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_BYTE

#define PERIPH_SPI_NEEDS_TRANSFER_BYTE

Use some common SPI functions.

Definition at line 393 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_REG

#define PERIPH_SPI_NEEDS_TRANSFER_REG

Definition at line 394 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_REGS

#define PERIPH_SPI_NEEDS_TRANSFER_REGS

Definition at line 395 of file periph_cpu.h.

◆ PERIPH_TIMER_PROVIDES_SET

#define PERIPH_TIMER_PROVIDES_SET 1

The nRF5x periph_timer implements timer_set()

Definition at line 341 of file periph_cpu.h.

◆ QN908X_ADC_CLOCK

#define QN908X_ADC_CLOCK

Selected ADC oversample clock.

Define to one of the qn908x_adc_clock_t values.

Definition at line 209 of file periph_cpu.h.

◆ TIMER_CHANNEL_NUMOF

#define TIMER_CHANNEL_NUMOF (4)

CPU specific timer Counter/Timers (CTIMER) configuration.

Definition at line 336 of file periph_cpu.h.

◆ TIMER_MAX_VALUE

#define TIMER_MAX_VALUE (0xffffffff)

Definition at line 337 of file periph_cpu.h.

◆ UART_INVALID_MODE

#define UART_INVALID_MODE (0x80)

Invalid UART mode mask.

Signals that the mode is invalid or not supported by the CPU.

Definition at line 493 of file periph_cpu.h.

◆ WDT_HAS_STOP

#define WDT_HAS_STOP (1)

Watchdog clock can be stopped independently of other clocks.

Definition at line 71 of file periph_cpu.h.

◆ WWDT_TIME_LOWER_LIMIT

#define WWDT_TIME_LOWER_LIMIT (1U)

Definition at line 86 of file periph_cpu.h.

◆ WWDT_TIME_UPPER_LIMIT

#define WWDT_TIME_UPPER_LIMIT (268435U)

Definition at line 87 of file periph_cpu.h.

Typedef Documentation

◆ adc_conf_t

typedef uint16_t adc_conf_t

CPU specific ADC configuration.

ADC Channel, Vinn, Vref and gain configuration.

This value should be set to the logic or between the following values:

bit 3: the optional flag ADC_PGA_ENABLE,
bits 4-5: a qn908x_adc_vinn_t value defining Vinn if needed,
bits 6-7: a qn908x_adc_gain_t optional gain value,
bit 8: the optional flag ADC_VREF_GAIN_X15,
bits 9-13: the selected qn908x_adc_channel_t, and
bits 14-15: the qn908x_adc_vref_t value defining Vref.

The same channels with different settings can be configured as different ADC lines in the board, just using different adc_conf_t entries.

Definition at line 330 of file periph_cpu.h.

◆ gpio_t

typedef uint16_t gpio_t

Definition at line 36 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Available ports on the QN908x.

Enumerator
PORT_A	port A
PORT_B	port B
GPIO_PORTS_NUMOF	overall number of available ports

Definition at line 138 of file periph_cpu.h.

◆ i2c_speed_t

enum i2c_speed_t

Enumerator
I2C_SPEED_LOW	low speed mode: ~10 kbit/s
I2C_SPEED_NORMAL	normal mode: ~100 kbit/s
I2C_SPEED_FAST	fast mode: ~400 kbit/s
I2C_SPEED_FAST_PLUS	not supported, capped at 400 kbit/s
I2C_SPEED_HIGH	not supported, capped at 400 kbit/s

Definition at line 352 of file periph_cpu.h.

◆ qn908x_adc_channel_t

enum qn908x_adc_channel_t

ADC channel pair configuration.

The following are the possible combinations of + and - inputs to the ADC sigma delta. Some of these combinations reference the "Vinn" signal which can be independently selected, see qn908x_adc_vinn_t for details.

The first signal is connected to the positive side while the second one is connected to the negative side. For example, ADC_CHANNEL_ADC0_ADC1 will read a positive value if ADC0 voltage is higher than ADC1.

The ADC_CHANNEL_TEMP uses the internal temperature signal and ADC_CHANNEL_VCC4_VINN connects the + side to Vcc/4, which is useful to measure the battery level when Vcc is directly connected to a battery.

Enumerator
ADC_CHANNEL_ADC0_ADC1	Sample ADC0 / ADC1.
ADC_CHANNEL_ADC2_ADC3	Sample ADC2 / ADC3.
ADC_CHANNEL_ADC4_ADC5	Sample ADC4 / ADC5.
ADC_CHANNEL_ADC6_ADC7	Sample ADC6 / ADC7.
ADC_CHANNEL_ADC0_VINN	Sample ADC0 / Vinn.
ADC_CHANNEL_ADC1_VINN	Sample ADC1 / Vinn.
ADC_CHANNEL_ADC2_VINN	Sample ADC2 / Vinn.
ADC_CHANNEL_ADC3_VINN	Sample ADC3 / Vinn.
ADC_CHANNEL_ADC4_VINN	Sample ADC4 / Vinn.
ADC_CHANNEL_ADC5_VINN	Sample ADC5 / Vinn.
ADC_CHANNEL_ADC6_VINN	Sample ADC6 / Vinn.
ADC_CHANNEL_ADC7_VINN	Sample ADC7 / Vinn.
ADC_CHANNEL_TEMP	Sample internal temperature.
ADC_CHANNEL_VCC4_VINN	Sample 1/4 Vcc / Vinn.
ADC_CHANNEL_VINN_VINN	Sample Vinn / Vinn.
ADC_CHANNEL_VINN_VSS	Sample Vinn / Vss.

Definition at line 227 of file periph_cpu.h.

◆ qn908x_adc_clock_t

enum qn908x_adc_clock_t

ADC oversample clock configuration.

The ADC runs at a given ADC clock frequency which is derived from either the high frequency clock (16 or 32 MHz) or the low frequency one (32 or 32.768 KHz). Running the ADC from the 32 KHz source can be useful in low power applications where the high speed clock is not running.

The ADC sample rate for adc_sample() will be about 128 times slower than the ADC clock, due to the decimation filter, meaning that the maximum sampling rate is 31.25 KHz.

Enumerator
ADC_CLOCK_4M	4 MHz from the high speed clock.
ADC_CLOCK_2M	2 MHz from the high speed clock.
ADC_CLOCK_1M	1 MHz from the high speed clock.
ADC_CLOCK_500K	500 KHz from the high speed clock.
ADC_CLOCK_250K	250 KHz from the high speed clock.
ADC_CLOCK_125K	125 KHz from the high speed clock.
ADC_CLOCK_62K5	62.5 KHz from the high speed clock.
ADC_CLOCK_31K25	31.25 KHz from the high speed clock.
ADC_CLOCK_32K	32 KHz or 32.768 KHz from the low speed clock.

Definition at line 192 of file periph_cpu.h.

◆ qn908x_adc_gain_t

enum qn908x_adc_gain_t

ADC SD Gain configuration.

This multiplies the sampled value (difference between +/- signals) by the given value.

Note: these values logic xor 0x40 match the values for ADC_CFG_ADC_GAIN field. This is selected so that omitting this flag in the config field defaults to x1.0 gain but it can still be converted to the ADC_GAIN field with a simple logic xor.

Enumerator
ADC_GAIN_X05	Use gain := 0.5.
ADC_GAIN_X1	Use gain := 1.
ADC_GAIN_X15	Use gain := 1.5.
ADC_GAIN_X20	Use gain := 2.

Definition at line 307 of file periph_cpu.h.

◆ qn908x_adc_vinn_t

enum qn908x_adc_vinn_t

ADC Vinn configuration.

This value is only relevant for the channels that reference Vinn. The value is the same as the PGA_VINN in ADC CFG register with a logic xor 0x30u to make the default AVSS (analog Vss pad).

Enumerator
ADC_VINN_VREF	Use Vinn := Vref.
ADC_VINN_VREF_3_4	Use Vinn := 3/4 * Vref.
ADC_VINN_VREF_2	Use Vinn := 1/2 * Vref.
ADC_VINN_AVSS	Use Vinn := Vss.

Definition at line 289 of file periph_cpu.h.

◆ qn908x_adc_vref_t

enum qn908x_adc_vref_t

ADC Vref configuration.

This value affects the reference voltage used by the ADC as the full range. It is also used in some cases to generate the Vinn signal are is only relevant for the channels that reference Vinn when it was set by qn908x_adc_vinn_t to use Vref. The actual values match the field VREF_SEL in ADC CTRL register.

Enumerator
ADC_VREF_1V2	Vref := internal 1.2V.
ADC_VREF_VREF	Vref := external ADC_VREFI pin.
ADC_VREF_VEXT	Vref := external ADC_VREFI with the driver.
ADC_VREF_VCC	Vref := Vcc.

Definition at line 254 of file periph_cpu.h.

◆ uart_data_bits_t

enum uart_data_bits_t

Definition of possible data bits lengths in a UART frame.

These are defined to match the values of the USART->CFG : DATALEN bit field.

Enumerator
UART_DATA_BITS_5	5 data bits
UART_DATA_BITS_6	6 data bits
UART_DATA_BITS_7	7 data bits
UART_DATA_BITS_8	8 data bits

Definition at line 518 of file periph_cpu.h.

◆ uart_parity_t

enum uart_parity_t

Definition of possible parity modes.

These are defined to match the values of the USART->CFG : PARITYSEL bit field.

Enumerator
UART_PARITY_NONE	no parity
UART_PARITY_EVEN	even parity
UART_PARITY_ODD	odd parity
UART_PARITY_MARK	mark parity
UART_PARITY_SPACE	space parity

Definition at line 502 of file periph_cpu.h.

◆ uart_stop_bits_t

enum uart_stop_bits_t

Definition of possible stop bits lengths.

These are defined to match the values of the USART->CFG : STOPLEN bit field.

Enumerator
UART_STOP_BITS_1	1 stop bit
UART_STOP_BITS_2	2 stop bits

Definition at line 534 of file periph_cpu.h.