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cfg_spi_default.h
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1/*
2 * SPDX-FileCopyrightText: 2014-2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2015 Zolertia SL
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
20
21#include "periph_cpu.h"
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31static const spi_conf_t spi_config[] = {
32 {
33 .num = 0,
34 .mosi_pin = GPIO_PIN(PORT_B, 1),
35 .miso_pin = GPIO_PIN(PORT_B, 3),
36 .sck_pin = GPIO_PIN(PORT_B, 2),
37 .cs_pin = GPIO_PIN(PORT_B, 5)
38 },
39 {
40 .num = 1,
41 .mosi_pin = GPIO_PIN(PORT_C, 5),
42 .miso_pin = GPIO_PIN(PORT_C, 6),
43 .sck_pin = GPIO_PIN(PORT_C, 4),
44 .cs_pin = GPIO_PIN(PORT_A, 7)
45 }
46};
47
48#define SPI_NUMOF ARRAY_SIZE(spi_config)
50
51#ifdef __cplusplus
52} /* end extern "C" */
53#endif
54
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
SPI device configuration.
Definition periph_cpu.h:336