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sdkconfig_esp32.h
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1/*
2 * SPDX-FileCopyrightText: 2022 Gunar Schorcht
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
20
21#ifndef DOXYGEN
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31
32/* Mapping of Kconfig defines to the respective enumeration values */
33#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
34# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
35#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
36# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
37#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
38# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
39#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
40# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
41#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
42# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
43#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
44# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
45#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
46# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
47#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
48# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
49#endif
50
54#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
55# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
56#endif
57
59
63#define CONFIG_RTC_CLK_CAL_CYCLES 1024
64
65#ifdef MODULE_ESP_RTC_TIMER_32K
66# define CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 1
67# define CONFIG_RTC_XTAL_CAL_RETRY 1
68# define CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 5
69#endif
70
74#define CONFIG_EFUSE_MAX_BLK_LEN 192
75#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
76#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
77#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 99
78
82#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
83#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
84#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
85#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
86#define CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES 4
87
91#define CONFIG_ESP32_REV_MIN 0
92#define CONFIG_ESP32_TRACEMEM_RESERVE_DRAM 0x0
93
94#define CONFIG_ESP_BROWNOUT_DET 1
95#define CONFIG_ESP_BROWNOUT_DET_LVL 0
96#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
97#define CONFIG_ESP_DEBUG_OCDAWARE 1
98#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
99
100#define CONFIG_ULP_COPROC_RESERVE_MEM 0
101
105#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
106#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
107
111#define CONFIG_ADC_CALI_EFUSE_TP_ENABLE 1
112#define CONFIG_ADC_CALI_EFUSE_VREF_ENABLE 1
113#define CONFIG_ADC_CALI_LUT_ENABLE 1
114
118#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
119
126#ifndef CONFIG_XTAL_FREQ
127# define CONFIG_XTAL_FREQ 0
128#endif
129
133#ifdef MODULE_ESP_SPI_RAM
134# define CONFIG_D0WD_PSRAM_CLK_IO 17
135# define CONFIG_D0WD_PSRAM_CS_IO 16
136# define CONFIG_D2WD_PSRAM_CLK_IO 9
137# define CONFIG_D2WD_PSRAM_CS_IO 10
138# define CONFIG_PICO_PSRAM_CS_IO 10
139# define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
140# define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
141# define CONFIG_SPIRAM_CACHE_WORKAROUND 1
142# define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
143# define CONFIG_SPIRAM_MODE_QUAD 1
144# define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
145#endif
146
150#ifdef MODULE_ESP_ETH
151# define CONFIG_ETH_USE_ESP32_EMAC 1
152# define CONFIG_ETH_PHY_INTERFACE_RMII 1
153# define CONFIG_ETH_RMII_CLK_INPUT 1
154# define CONFIG_ETH_RMII_CLK_IN_GPIO 0
155# define CONFIG_ETH_DMA_BUFFER_SIZE 512
156# define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
157# define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
158#endif
159
163#ifdef MODULE_ESP_BLE
164# define CONFIG_BT_ALARM_MAX_NUM 50
165# define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
166# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
167# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
168# define CONFIG_BTDM_BLE_CHAN_ASS_EN 1
169# define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
170# define CONFIG_BTDM_BLE_PING_EN 1
171# define CONFIG_BTDM_BLE_SCAN_DUPL 1
172# define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
173# define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
174# define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
175# define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
176# define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
177# define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
178# define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
179# define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
180# define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
181# define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
182# define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
183# define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
184# define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
185# define CONFIG_BTDM_CTRL_PCM_FSYNCSHP_EFF 1
186# define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
187# define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
188# define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
189# define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
190# define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
191# define CONFIG_BTDM_SCAN_DUPL_CACHE_REFRESH_PERIOD 0
192# define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
193# define CONFIG_BTDM_SCAN_DUPL_TYPE 0
194# define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
195#else
196# define CONFIG_BTDM_RESERVE_DRAM 0
197#endif
198
199#ifdef __cplusplus
200}
201#endif
202
203#endif /* DOXYGEN */