Loading...
Searching...
No Matches
sdkconfig_esp32c3.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2022 Gunar Schorcht
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
20
21#ifndef DOXYGEN
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31
32/* Mapping of Kconfig defines to the respective enumeration values */
33#if CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_2
34# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
35#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_5
36# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
37#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_10
38# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
39#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_20
40# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
41#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_40
42# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
43#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_80
44# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
45#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_160
46# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
47#endif
48
52#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
53# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
54#endif
55
57
61#define CONFIG_RTC_CLK_CAL_CYCLES 1024
62
66#define CONFIG_EFUSE_MAX_BLK_LEN 256
67#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
68#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
69
73#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
74#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
75#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
76#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
77#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4
78
82#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
83
84#define CONFIG_ESP32C3_DEBUG_OCDAWARE 1
85#define CONFIG_ESP32C3_REV_MIN 3
86
87#define CONFIG_ESP32C3_BROWNOUT_DET 1
88#define CONFIG_ESP32C3_BROWNOUT_DET_LVL 7
89
93#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND 1
94#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
95#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
96#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 0 /* we realize it */
97#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
98#define CONFIG_ESP_SLEEP_POWER_DOWN_FLASH 1
99#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
100#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1
101
105#define CONFIG_ESP_PHY_ENABLE_USB 1
106
110#ifdef MODULE_ESP_BLE
111# define CONFIG_BT_ALARM_MAX_NUM 50
112# define CONFIG_BT_BLE_CCA_MODE 0
113# define CONFIG_BT_BLE_CCA_MODE_NONE 1
114# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
115# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
116# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
117# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
118# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
119# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
120# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
121# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
122# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
123# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
124# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
125# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
126# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
127# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
128# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
129# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
130# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
131# define CONFIG_BT_CTRL_HCI_TL 1
132# define CONFIG_BT_CTRL_HCI_TL_EFF 1
133# define CONFIG_BT_CTRL_HW_CCA_EFF 0
134# define CONFIG_BT_CTRL_HW_CCA_VAL 20
135# define CONFIG_BT_CTRL_LE_PING_EN 1
136# define CONFIG_BT_CTRL_MODE_EFF 1
137# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
138# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
139# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
140# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
141# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
142# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
143# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
144# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
145# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
146# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
147# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
148# define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
149#endif
150
151/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
152 * To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
153 * has to be set (default). */
154#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
155# define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
156#endif
157
158/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
159 * To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
160 * has to be set (default). */
161#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
162#define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
163#endif
164
165#ifdef __cplusplus
166}
167#endif
168
169#endif /* DOXYGEN */