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board.h
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1/*
2 * Copyright (C) 2018 HAW Hamburg
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
22#ifndef BOARD_H
23#define BOARD_H
24
25#include "cpu.h"
26#include "periph_conf.h"
27#include "periph_cpu.h"
28#include "periph/gpio.h"
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
38#define LED0_PIN GPIO_PIN(PA, 27)
39
40#define LED_PORT PORT->Group[PA]
41#define LED0_MASK (1 << 27)
42
43#define LED0_ON (LED_PORT.OUTSET.reg = LED0_MASK)
44#define LED0_OFF (LED_PORT.OUTCLR.reg = LED0_MASK)
45#define LED0_TOGGLE (LED_PORT.OUTTGL.reg = LED0_MASK)
46
47#define LED1_PIN GPIO_PIN(PA, 28)
48#define LED1_MASK (1 << 28)
49
50#define LED1_ON (LED_PORT.OUTSET.reg = LED1_MASK)
51#define LED1_OFF (LED_PORT.OUTCLR.reg = LED1_MASK)
52#define LED1_TOGGLE (LED_PORT.OUTTGL.reg = LED1_MASK)
59#define BTN0_PIN GPIO_PIN(PA, 20)
60#define BTN0_MODE GPIO_IN_PU
70#define XBEE1_EN_PORT PORT->Group[PB]
71#define XBEE1_EN_MASK (1 << 3)
72#define XBEE1_EN_MODE GPIO_OUT
73#define XBEE1_EN_PIN GPIO_PIN(PB, 3)
74
75#define XBEE1_ENABLE (XBEE1_EN_PORT.OUTCLR.reg = XBEE1_EN_MASK)
76#define XBEE1_DISABLE (XBEE1_EN_PORT.OUTSET.reg = XBEE1_EN_MASK)
77
78#define XBEE1_CS_PIN GPIO_PIN(PA, 18)
79
80#define XBEE1_INT_PIN GPIO_PIN(PA, 21)
90#define XBEE2_EN_PORT PORT->Group[PB]
91#define XBEE2_EN_MASK (1 << 10)
92#define XBEE2_EN_PIN GPIO_PIN(PB, 10)
93#define XBEE2_EN_MODE GPIO_OUT
94
95#define XBEE2_ENABLE (XBEE2_EN_PORT.OUTCLR.reg = XBEE2_EN_MASK)
96#define XBEE2_DISABLE (XBEE2_EN_PORT.OUTSET.reg = XBEE2_EN_MASK)
97
98#define XBEE2_CS_PIN GPIO_PIN(PA, 14)
99
100#define XBEE2_INT_PIN GPIO_PIN(PA, 15)
110#define I2C_EN_PORT PORT->Group[PB]
111#define I2C_EN_MASK (1 << 11)
112#define I2C_EN_PIN GPIO_PIN(PB, 11)
113#define I2C_EN_MODE GPIO_OUT
114
115#define I2C_ENABLE (I2C_EN_PORT.OUTSET.reg = I2C_EN_MASK)
116#define I2C_DISABLE (I2C_EN_PORT.OUTCLR.reg = I2C_EN_MASK)
128#define SX127X_PARAM_SPI (SPI_DEV(0))
129
130#define SX127X_PARAM_SPI_NSS XBEE1_CS_PIN /* D23 */
131
132#define SX127X_PARAM_RESET GPIO_UNDEF
133
134#define SX127X_PARAM_DIO0 XBEE1_INT_PIN /* D24 */
135
136#define SX127X_PARAM_DIO1 GPIO_UNDEF
137
138#define SX127X_PARAM_DIO2 GPIO_UNDEF
139
140#define SX127X_PARAM_DIO3 GPIO_UNDEF
141
142#define SX127X_PARAM_PASELECT (SX127X_PA_BOOST)
148#define WAIT_FOR_SPI_RESET (3000000UL)
149
153#define HDC1000_PARAM_ADDR (0x40)
154
158#define TSL2561_PARAM_ADDR TSL2561_ADDR_LOW
159
163#define BMX280_PARAM_I2C_ADDR (0x76)
164
165#if defined(MODULE_MTD_SDCARD) || defined(DOXYGEN)
170#define MTD_0 mtd_dev_get(0)
172#endif /* MODULE_MTD_SDCARD || DOXYGEN */
173
174#ifdef __cplusplus
175}
176#endif
177
178#endif /* BOARD_H */
Native CPU peripheral configuration.
Low-level GPIO peripheral driver interface definitions.