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clk_conf.h
1/*
2 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
15
16#include <stdbool.h>
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
26enum fam {
27 STM32F0,
28 STM32F1,
29 STM32F2,
30 STM32F3,
31 STM32F4,
32 STM32F7,
33 STM32MP1,
34 FAM_MAX,
35};
37
42enum {
43 STM32F030,
44 STM32F070,
45 STM32F031,
46 STM32F051,
47 STM32F071,
48 STM32F091,
49 STM32F042,
50 STM32F072,
51 STM32F038,
52 STM32F048,
53 STM32F058,
54 STM32F078,
55 STM32F098,
56
57 STM32F100,
58 STM32F101,
59 STM32F102,
60 STM32F103,
61
62 STM32F205,
63 STM32F207,
64 STM32F215,
65 STM32F217,
66
67 STM32F301,
68 STM32F302,
69 STM32F303,
70 STM32F334,
71 STM32F373,
72 STM32F318,
73 STM32F328,
74 STM32F358,
75 STM32F378,
76 STM32F398,
77
78 STM32F401,
79 STM32F405,
80 STM32F407,
81 STM32F410,
82 STM32F411,
83 STM32F412,
84 STM32F413,
85 STM32F415,
86 STM32F417,
87 STM32F423,
88 STM32F427,
89 STM32F429,
90 STM32F437,
91 STM32F439,
92 STM32F446,
93 STM32F469,
94 STM32F479,
95
96 STM32F722,
97 STM32F732,
98 STM32F746,
99 STM32F756,
100 STM32F767,
101 STM32F769,
102 STM32F777,
103 STM32F779,
104
105 MODEL_F_MAX,
106};
107
108enum {
109 STM32MP157,
110
111 MODEL_MP_MAX,
112};
114
140typedef struct {
141 unsigned min_vco_input;
142 unsigned max_vco_input;
143 unsigned min_vco_output;
144 unsigned max_vco_output;
145
146 unsigned min_n;
147 unsigned max_n;
148 unsigned inc_n;
149
150 unsigned min_m;
151 unsigned max_m;
152 unsigned inc_m;
153
154 unsigned min_p;
155 unsigned max_p;
156 unsigned inc_p;
157
158 unsigned min_q;
159 unsigned max_q;
160 unsigned inc_q;
161} pll_cfg_t;
162
166typedef struct {
167 enum fam family;
168
169 unsigned max_coreclock;
170 unsigned max_apb1;
171 unsigned max_apb2;
172 unsigned max_apb3;
173
174 unsigned hsi;
175
176 pll_cfg_t pll;
177
178 bool has_pll_i2s;
179 bool has_pll_sai;
180 bool has_pll_i2s_m;
181 bool has_pll_sai_m;
182 bool has_pll_i2s_alt_input;
183
184 unsigned hsi_prediv;
185
186 int has_alt_48MHz;
187 bool need_48MHz;
188} clk_cfg_t;
189
194#define ALT_48MHZ_NO 0
195#define ALT_48MHZ_I2S 1
196#define ALT_48MHZ_SAI 2
197
198#define ALT_48MHZ_Q 0
199#define ALT_48MHZ_P 4
201
202#define STM32F(x) [STM32F##x] = x
203#define STM32F0(x) [STM32F0##x] = x
204
206static const unsigned stm32_f_model[] = {
207 STM32F0(30),
208 STM32F0(70),
209 STM32F0(31),
210 STM32F0(51),
211 STM32F0(71),
212 STM32F0(91),
213 STM32F0(42),
214 STM32F0(72),
215 STM32F0(38),
216 STM32F0(48),
217 STM32F0(58),
218 STM32F0(78),
219 STM32F0(98),
220
221 STM32F(100),
222 STM32F(101),
223 STM32F(102),
224 STM32F(103),
225
226 STM32F(205),
227 STM32F(207),
228 STM32F(215),
229 STM32F(217),
230
231 STM32F(301),
232 STM32F(302),
233 STM32F(303),
234 STM32F(334),
235 STM32F(373),
236 STM32F(318),
237 STM32F(328),
238 STM32F(358),
239 STM32F(378),
240 STM32F(398),
241
242 STM32F(401),
243 STM32F(405),
244 STM32F(407),
245 STM32F(410),
246 STM32F(411),
247 STM32F(412),
248 STM32F(413),
249 STM32F(415),
250 STM32F(417),
251 STM32F(423),
252 STM32F(427),
253 STM32F(429),
254 STM32F(437),
255 STM32F(439),
256 STM32F(446),
257 STM32F(469),
258 STM32F(479),
259
260 STM32F(722),
261 STM32F(732),
262 STM32F(746),
263 STM32F(756),
264 STM32F(767),
265 STM32F(769),
266 STM32F(777),
267 STM32F(779),
268};
269
270#define STM32MP(x) [STM32MP##x] = x
271
273static const unsigned stm32_model_mp[] = {
274 STM32MP(157),
275};
276
278#define stm32f2_4_192_pll_cfg { \
279 .min_vco_input = 1000000U, \
280 .max_vco_input = 2000000U, \
281 .min_vco_output = 192000000U, \
282 .max_vco_output = 432000000U, \
283 .min_n = 50, \
284 .max_n = 432, \
285 .inc_n = 1, \
286 .min_m = 2, \
287 .max_m = 63, \
288 .inc_m = 1, \
289 .min_p = 2, \
290 .max_p = 8, \
291 .inc_p = 2, \
292 .min_q = 2, \
293 .max_q = 15, \
294 .inc_q = 1, \
295}
296
298#define stm32f4_7_pll_cfg { \
299 .min_vco_input = 1000000U, \
300 .max_vco_input = 2000000U, \
301 .min_vco_output = 192000000U, \
302 .max_vco_output = 432000000U, \
303 .min_n = 50, \
304 .max_n = 432, \
305 .inc_n = 1, \
306 .min_m = 2, \
307 .max_m = 63, \
308 .inc_m = 1, \
309 .min_p = 2, \
310 .max_p = 8, \
311 .inc_p = 2, \
312 .min_q = 2, \
313 .max_q = 15, \
314 .inc_q = 1, \
315}
316
318#define stm32mp1_pll_cfg { \
319 .min_vco_input = 4000000U, \
320 .max_vco_input = 16000000U, \
321 .min_vco_output = 400000000U, \
322 .max_vco_output = 800000000U, \
323 .min_n = 25, \
324 .max_n = 100, \
325 .inc_n = 1, \
326 .min_m = 2, \
327 .max_m = 63, \
328 .inc_m = 1, \
329 .min_p = 2, \
330 .max_p = 127, \
331 .inc_p = 1, \
332 .min_q = 2, \
333 .max_q = 127, \
334 .inc_q = 1, \
335}
336
340static const clk_cfg_t stm32_f_clk_cfg[] = {
341 [STM32F030 ... STM32F098] = {
342 .family = STM32F0,
343 .max_coreclock = 48000000U,
344 .max_apb1 = 48000000U,
345 .max_apb2 = 0,
346 .hsi = 8000000U,
347 .pll = {
348 .min_vco_input = 1000000U,
349 .max_vco_input = 24000000U,
350 .min_vco_output = 16000000U,
351 .max_vco_output = 48000000U,
352 .min_m = 1,
353 .max_m = 16,
354 .inc_m = 1,
355 .min_n = 2,
356 .max_n = 16,
357 .inc_n = 1,
358 .min_p = 1,
359 .max_p = 1,
360 .inc_p = 1,
361 },
362 .has_pll_i2s = false,
363 .has_pll_sai = false,
364 .has_pll_i2s_alt_input = false,
365 .has_alt_48MHz = 0,
366 .hsi_prediv = 2,
367 .need_48MHz = false,
368 },
369 [STM32F100] = {
370 .family = STM32F1,
371 .max_coreclock = 24000000U,
372 .max_apb1 = 24000000U,
373 .max_apb2 = 24000000U,
374 .hsi = 8000000U,
375 .pll = {
376 .min_vco_input = 1000000U,
377 .max_vco_input = 24000000U,
378 .min_vco_output = 16000000U,
379 .max_vco_output = 24000000U,
380 .min_m = 1,
381 .max_m = 16,
382 .inc_m = 1,
383 .min_n = 2,
384 .max_n = 16,
385 .inc_n = 1,
386 .min_p = 1,
387 .max_p = 1,
388 .inc_p = 1,
389 },
390 .has_pll_i2s = false,
391 .has_pll_sai = false,
392 .has_pll_i2s_alt_input = false,
393 .has_alt_48MHz = 0,
394 .hsi_prediv = 2,
395 .need_48MHz = false,
396 },
397 [STM32F101 ... STM32F103] = {
398 .family = STM32F1,
399 .max_coreclock = 72000000U,
400 .max_apb1 = 36000000U,
401 .max_apb2 = 72000000U,
402 .hsi = 8000000U,
403 .pll = {
404 .min_vco_input = 1000000U,
405 .max_vco_input = 25000000U,
406 .min_vco_output = 1000000U,
407 .max_vco_output = 72000000U,
408 .min_m = 1,
409 .max_m = 16,
410 .inc_m = 1,
411 .min_n = 2,
412 .max_n = 16,
413 .inc_n = 1,
414 .min_p = 1,
415 .max_p = 1,
416 .inc_p = 1,
417 },
418 .has_pll_i2s = false,
419 .has_pll_sai = false,
420 .has_pll_i2s_alt_input = false,
421 .has_alt_48MHz = 0,
422 .hsi_prediv = 2,
423 .need_48MHz = false,
424 },
425 [STM32F205 ... STM32F217] = {
426 .family = STM32F2,
427 .max_coreclock = 120000000U,
428 .max_apb1 = 30000000U,
429 .max_apb2 = 60000000U,
430 .hsi = 16000000U,
431 .pll = stm32f2_4_192_pll_cfg,
432 .has_pll_i2s = true,
433 .has_pll_sai = false,
434 .has_pll_i2s_alt_input = false,
435 .has_alt_48MHz = 0,
436 .need_48MHz = true,
437 },
438 [STM32F301 ... STM32F398] = {
439 .family = STM32F3,
440 .max_coreclock = 72000000U,
441 .max_apb1 = 36000000U,
442 .max_apb2 = 72000000U,
443 .hsi = 8000000U,
444 .pll = {
445 .min_vco_input = 1000000U,
446 .max_vco_input = 25000000U,
447 .min_vco_output = 1000000U,
448 .max_vco_output = 72000000U,
449 .min_m = 1,
450 .max_m = 16,
451 .inc_m = 1,
452 .min_n = 2,
453 .max_n = 16,
454 .inc_n = 1,
455 .min_p = 1,
456 .max_p = 1,
457 .inc_p = 1,
458 },
459 .has_pll_i2s = false,
460 .has_pll_sai = false,
461 .has_pll_i2s_alt_input = false,
462 .has_alt_48MHz = 0,
463 .hsi_prediv = 2,
464 .need_48MHz = false,
465 },
466 [STM32F401] = {
467 .family = STM32F4,
468 .max_coreclock = 84000000U,
469 .max_apb1 = 42000000U,
470 .max_apb2 = 84000000U,
471 .hsi = 16000000U,
472 .pll = stm32f2_4_192_pll_cfg,
473 .has_pll_i2s = true,
474 .has_pll_sai = false,
475 .has_pll_i2s_m = false,
476 .has_pll_i2s_alt_input = false,
477 .has_alt_48MHz = 0,
478 .need_48MHz = true,
479 },
480 [STM32F405 ... STM32F407] = {
481 .family = STM32F4,
482 .max_coreclock = 168000000U,
483 .max_apb1 = 42000000U,
484 .max_apb2 = 84000000U,
485 .hsi = 16000000U,
486 .pll = stm32f4_7_pll_cfg,
487 .has_pll_i2s = true,
488 .has_pll_sai = false,
489 .has_pll_i2s_m = false,
490 .has_pll_i2s_alt_input = false,
491 .has_alt_48MHz = 0,
492 .need_48MHz = true,
493 },
494 [STM32F410] = {
495 .family = STM32F4,
496 .max_coreclock = 100000000U,
497 .max_apb1 = 50000000U,
498 .max_apb2 = 100000000U,
499 .hsi = 16000000U,
500 .pll = stm32f4_7_pll_cfg,
501 .has_pll_i2s = false,
502 .has_pll_sai = false,
503 .has_pll_i2s_m = false,
504 .has_pll_i2s_alt_input = false,
505 .has_alt_48MHz = 0,
506 .need_48MHz = true,
507 },
508 [STM32F411] = {
509 .family = STM32F4,
510 .max_coreclock = 100000000U,
511 .max_apb1 = 50000000U,
512 .max_apb2 = 100000000U,
513 .hsi = 16000000U,
514 .pll = stm32f4_7_pll_cfg,
515 .has_pll_i2s = true,
516 .has_pll_sai = false,
517 .has_pll_i2s_m = true,
518 .has_pll_i2s_alt_input = false,
519 .has_alt_48MHz = 0,
520 .need_48MHz = true,
521 },
522 [STM32F412 ... STM32F413] = {
523 .family = STM32F4,
524 .max_coreclock = 100000000U,
525 .max_apb1 = 50000000U,
526 .max_apb2 = 100000000U,
527 .hsi = 16000000U,
528 .pll = stm32f4_7_pll_cfg,
529 .has_pll_i2s = true,
530 .has_pll_sai = true,
531 .has_pll_i2s_m = true,
532 .has_pll_sai_m = false,
533 .has_pll_i2s_alt_input = true,
534 .has_alt_48MHz = ALT_48MHZ_I2S,
535 .need_48MHz = true,
536 },
537 [STM32F415 ... STM32F417] = {
538 .family = STM32F4,
539 .max_coreclock = 168000000U,
540 .max_apb1 = 42000000U,
541 .max_apb2 = 84000000U,
542 .hsi = 16000000U,
543 .pll = stm32f4_7_pll_cfg,
544 .has_pll_i2s = true,
545 .has_pll_sai = false,
546 .has_pll_i2s_m = false,
547 .has_pll_i2s_alt_input = false,
548 .has_alt_48MHz = 0,
549 .need_48MHz = true,
550 },
551 [STM32F423] = {
552 .family = STM32F4,
553 .max_coreclock = 100000000U,
554 .max_apb1 = 50000000U,
555 .max_apb2 = 100000000U,
556 .hsi = 16000000U,
557 .pll = stm32f4_7_pll_cfg,
558 .has_pll_i2s = true,
559 .has_pll_sai = true,
560 .has_pll_i2s_m = true,
561 .has_pll_sai_m = false,
562 .has_pll_i2s_alt_input = true,
563 .has_alt_48MHz = ALT_48MHZ_I2S,
564 .need_48MHz = true,
565 },
566 [STM32F427 ... STM32F439] = {
567 .family = STM32F4,
568 .max_coreclock = 180000000U,
569 .max_apb1 = 45000000U,
570 .max_apb2 = 90000000U,
571 .hsi = 16000000U,
572 .pll = stm32f4_7_pll_cfg,
573 .has_pll_i2s = true,
574 .has_pll_sai = true,
575 .has_pll_i2s_m = false,
576 .has_pll_sai_m = false,
577 .has_pll_i2s_alt_input = false,
578 .has_alt_48MHz = 0,
579 .need_48MHz = true,
580 },
581 [STM32F446] = {
582 .family = STM32F4,
583 .max_coreclock = 180000000U,
584 .max_apb1 = 45000000U,
585 .max_apb2 = 90000000U,
586 .hsi = 16000000U,
587 .pll = stm32f4_7_pll_cfg,
588 .has_pll_i2s = true,
589 .has_pll_sai = true,
590 .has_pll_i2s_m = true,
591 .has_pll_sai_m = true,
592 .has_pll_i2s_alt_input = false,
593 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
594 .need_48MHz = true,
595 },
596 [STM32F469 ... STM32F479] = {
597 .family = STM32F4,
598 .max_coreclock = 180000000U,
599 .max_apb1 = 45000000U,
600 .max_apb2 = 90000000U,
601 .hsi = 16000000U,
602 .pll = stm32f4_7_pll_cfg,
603 .has_pll_i2s = true,
604 .has_pll_sai = true,
605 .has_pll_i2s_m = false,
606 .has_pll_sai_m = false,
607 .has_pll_i2s_alt_input = false,
608 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
609 .need_48MHz = true,
610 },
611 [STM32F722 ... STM32F779] = {
612 .family = STM32F7,
613 .max_coreclock = 216000000U,
614 .max_apb1 = 54000000U,
615 .max_apb2 = 108000000U,
616 .hsi = 16000000U,
617 .pll = stm32f4_7_pll_cfg,
618 .has_pll_i2s = true,
619 .has_pll_sai = true,
620 .has_pll_i2s_m = false,
621 .has_pll_sai_m = false,
622 .has_pll_i2s_alt_input = false,
623 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
624 .need_48MHz = true,
625 },
626};
627
631static const clk_cfg_t stm32_mp_clk_cfg[] = {
632 [STM32MP157] = {
633 .family = STM32MP1,
634 .max_coreclock = 209000000U,
635 .max_apb1 = 104500000U,
636 .max_apb2 = 104500000U,
637 .max_apb3 = 104500000U,
638 .hsi = 64000000U,
639 .pll = stm32mp1_pll_cfg,
640 .has_pll_i2s = false,
641 .has_pll_sai = false,
642 .has_pll_i2s_m = false,
643 .has_pll_sai_m = false,
644 .has_pll_i2s_alt_input = false,
645 .has_alt_48MHz = 0,
646 .need_48MHz = true,
647 },
648};
649
650#ifdef __cplusplus
651}
652#endif
653
clk_cfg_t
Clock configuration.
Definition clk_conf.h:166
clk_cfg_t::max_apb1
unsigned max_apb1
Max APB1 clock.
Definition clk_conf.h:170
clk_cfg_t::has_pll_i2s_m
bool has_pll_i2s_m
PLL I2S has a M factor.
Definition clk_conf.h:180
clk_cfg_t::max_coreclock
unsigned max_coreclock
Max coreclock.
Definition clk_conf.h:169
clk_cfg_t::hsi
unsigned hsi
HSI frequency.
Definition clk_conf.h:174
clk_cfg_t::has_pll_i2s
bool has_pll_i2s
PLL I2S available.
Definition clk_conf.h:178
clk_cfg_t::family
enum fam family
Family.
Definition clk_conf.h:167
clk_cfg_t::max_apb3
unsigned max_apb3
Max APB3 clock.
Definition clk_conf.h:172
clk_cfg_t::pll
pll_cfg_t pll
PLL configuration.
Definition clk_conf.h:176
clk_cfg_t::has_pll_sai
bool has_pll_sai
PLL SAI available.
Definition clk_conf.h:179
clk_cfg_t::has_pll_i2s_alt_input
bool has_pll_i2s_alt_input
PLL I2S has an external input available.
Definition clk_conf.h:182
clk_cfg_t::has_alt_48MHz
int has_alt_48MHz
48MHz can be generated by an alternate source
Definition clk_conf.h:186
clk_cfg_t::hsi_prediv
unsigned hsi_prediv
Value if HSI has a fixed prediv, 0 otherwise.
Definition clk_conf.h:184
clk_cfg_t::need_48MHz
bool need_48MHz
48MHz is needed
Definition clk_conf.h:187
clk_cfg_t::max_apb2
unsigned max_apb2
Max APB2 clock.
Definition clk_conf.h:171
clk_cfg_t::has_pll_sai_m
bool has_pll_sai_m
PLL SAI has a M factor.
Definition clk_conf.h:181
pll_cfg_t
PLL configuration parameters.
Definition clk_conf.h:140
pll_cfg_t::min_vco_output
unsigned min_vco_output
Min VCO output.
Definition clk_conf.h:143
pll_cfg_t::max_n
unsigned max_n
Max N.
Definition clk_conf.h:147
pll_cfg_t::max_vco_input
unsigned max_vco_input
Max VCO input.
Definition clk_conf.h:142
pll_cfg_t::min_vco_input
unsigned min_vco_input
Min VCO input.
Definition clk_conf.h:141
pll_cfg_t::min_m
unsigned min_m
Min M.
Definition clk_conf.h:150
pll_cfg_t::max_m
unsigned max_m
Max M.
Definition clk_conf.h:151
pll_cfg_t::min_n
unsigned min_n
Min N.
Definition clk_conf.h:146
pll_cfg_t::max_p
unsigned max_p
Max P.
Definition clk_conf.h:155
pll_cfg_t::inc_n
unsigned inc_n
Increment between two values of N.
Definition clk_conf.h:148
pll_cfg_t::inc_m
unsigned inc_m
Increment between two values of M.
Definition clk_conf.h:152
pll_cfg_t::min_p
unsigned min_p
Min P.
Definition clk_conf.h:154
pll_cfg_t::inc_p
unsigned inc_p
Increment between two values of P.
Definition clk_conf.h:156
pll_cfg_t::min_q
unsigned min_q
Min Q.
Definition clk_conf.h:158
pll_cfg_t::max_q
unsigned max_q
Max Q.
Definition clk_conf.h:159
pll_cfg_t::max_vco_output
unsigned max_vco_output
Max VCO output.
Definition clk_conf.h:144
pll_cfg_t::inc_q
unsigned inc_q
Increment between two values of Q.
Definition clk_conf.h:160