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clk_conf.h
1/*
2 * Copyright (C) 2017 OTA keys S.A.
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
18
19#include <stdbool.h>
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
29enum fam {
30 STM32F0,
31 STM32F1,
32 STM32F2,
33 STM32F3,
34 STM32F4,
35 STM32F7,
36 STM32MP1,
37 FAM_MAX,
38};
40
45enum {
46 STM32F030,
47 STM32F070,
48 STM32F031,
49 STM32F051,
50 STM32F071,
51 STM32F091,
52 STM32F042,
53 STM32F072,
54 STM32F038,
55 STM32F048,
56 STM32F058,
57 STM32F078,
58 STM32F098,
59
60 STM32F100,
61 STM32F101,
62 STM32F102,
63 STM32F103,
64
65 STM32F205,
66 STM32F207,
67 STM32F215,
68 STM32F217,
69
70 STM32F301,
71 STM32F302,
72 STM32F303,
73 STM32F334,
74 STM32F373,
75 STM32F318,
76 STM32F328,
77 STM32F358,
78 STM32F378,
79 STM32F398,
80
81 STM32F401,
82 STM32F405,
83 STM32F407,
84 STM32F410,
85 STM32F411,
86 STM32F412,
87 STM32F413,
88 STM32F415,
89 STM32F417,
90 STM32F423,
91 STM32F427,
92 STM32F429,
93 STM32F437,
94 STM32F439,
95 STM32F446,
96 STM32F469,
97 STM32F479,
98
99 STM32F722,
100 STM32F732,
101 STM32F746,
102 STM32F756,
103 STM32F767,
104 STM32F769,
105 STM32F777,
106 STM32F779,
107
108 MODEL_F_MAX,
109};
110
111enum {
112 STM32MP157,
113
114 MODEL_MP_MAX,
115};
117
143typedef struct {
144 unsigned min_vco_input;
145 unsigned max_vco_input;
146 unsigned min_vco_output;
147 unsigned max_vco_output;
148
149 unsigned min_n;
150 unsigned max_n;
151 unsigned inc_n;
152
153 unsigned min_m;
154 unsigned max_m;
155 unsigned inc_m;
156
157 unsigned min_p;
158 unsigned max_p;
159 unsigned inc_p;
160
161 unsigned min_q;
162 unsigned max_q;
163 unsigned inc_q;
164} pll_cfg_t;
165
169typedef struct {
170 enum fam family;
171
172 unsigned max_coreclock;
173 unsigned max_apb1;
174 unsigned max_apb2;
175 unsigned max_apb3;
176
177 unsigned hsi;
178
179 pll_cfg_t pll;
180
181 bool has_pll_i2s;
182 bool has_pll_sai;
183 bool has_pll_i2s_m;
184 bool has_pll_sai_m;
185 bool has_pll_i2s_alt_input;
186
187 unsigned hsi_prediv;
188
189 int has_alt_48MHz;
190 bool need_48MHz;
191} clk_cfg_t;
192
197#define ALT_48MHZ_NO 0
198#define ALT_48MHZ_I2S 1
199#define ALT_48MHZ_SAI 2
200
201#define ALT_48MHZ_Q 0
202#define ALT_48MHZ_P 4
204
205#define STM32F(x) [STM32F##x] = x
206#define STM32F0(x) [STM32F0##x] = x
207
209static const unsigned stm32_f_model[] = {
210 STM32F0(30),
211 STM32F0(70),
212 STM32F0(31),
213 STM32F0(51),
214 STM32F0(71),
215 STM32F0(91),
216 STM32F0(42),
217 STM32F0(72),
218 STM32F0(38),
219 STM32F0(48),
220 STM32F0(58),
221 STM32F0(78),
222 STM32F0(98),
223
224 STM32F(100),
225 STM32F(101),
226 STM32F(102),
227 STM32F(103),
228
229 STM32F(205),
230 STM32F(207),
231 STM32F(215),
232 STM32F(217),
233
234 STM32F(301),
235 STM32F(302),
236 STM32F(303),
237 STM32F(334),
238 STM32F(373),
239 STM32F(318),
240 STM32F(328),
241 STM32F(358),
242 STM32F(378),
243 STM32F(398),
244
245 STM32F(401),
246 STM32F(405),
247 STM32F(407),
248 STM32F(410),
249 STM32F(411),
250 STM32F(412),
251 STM32F(413),
252 STM32F(415),
253 STM32F(417),
254 STM32F(423),
255 STM32F(427),
256 STM32F(429),
257 STM32F(437),
258 STM32F(439),
259 STM32F(446),
260 STM32F(469),
261 STM32F(479),
262
263 STM32F(722),
264 STM32F(732),
265 STM32F(746),
266 STM32F(756),
267 STM32F(767),
268 STM32F(769),
269 STM32F(777),
270 STM32F(779),
271};
272
273#define STM32MP(x) [STM32MP##x] = x
274
276static const unsigned stm32_model_mp[] = {
277 STM32MP(157),
278};
279
281#define stm32f2_4_192_pll_cfg { \
282 .min_vco_input = 1000000U, \
283 .max_vco_input = 2000000U, \
284 .min_vco_output = 192000000U, \
285 .max_vco_output = 432000000U, \
286 .min_n = 50, \
287 .max_n = 432, \
288 .inc_n = 1, \
289 .min_m = 2, \
290 .max_m = 63, \
291 .inc_m = 1, \
292 .min_p = 2, \
293 .max_p = 8, \
294 .inc_p = 2, \
295 .min_q = 2, \
296 .max_q = 15, \
297 .inc_q = 1, \
298}
299
301#define stm32f4_7_pll_cfg { \
302 .min_vco_input = 1000000U, \
303 .max_vco_input = 2000000U, \
304 .min_vco_output = 192000000U, \
305 .max_vco_output = 432000000U, \
306 .min_n = 50, \
307 .max_n = 432, \
308 .inc_n = 1, \
309 .min_m = 2, \
310 .max_m = 63, \
311 .inc_m = 1, \
312 .min_p = 2, \
313 .max_p = 8, \
314 .inc_p = 2, \
315 .min_q = 2, \
316 .max_q = 15, \
317 .inc_q = 1, \
318}
319
321#define stm32mp1_pll_cfg { \
322 .min_vco_input = 4000000U, \
323 .max_vco_input = 16000000U, \
324 .min_vco_output = 400000000U, \
325 .max_vco_output = 800000000U, \
326 .min_n = 25, \
327 .max_n = 100, \
328 .inc_n = 1, \
329 .min_m = 2, \
330 .max_m = 63, \
331 .inc_m = 1, \
332 .min_p = 2, \
333 .max_p = 127, \
334 .inc_p = 1, \
335 .min_q = 2, \
336 .max_q = 127, \
337 .inc_q = 1, \
338}
339
343static const clk_cfg_t stm32_f_clk_cfg[] = {
344 [STM32F030 ... STM32F098] = {
345 .family = STM32F0,
346 .max_coreclock = 48000000U,
347 .max_apb1 = 48000000U,
348 .max_apb2 = 0,
349 .hsi = 8000000U,
350 .pll = {
351 .min_vco_input = 1000000U,
352 .max_vco_input = 24000000U,
353 .min_vco_output = 16000000U,
354 .max_vco_output = 48000000U,
355 .min_m = 1,
356 .max_m = 16,
357 .inc_m = 1,
358 .min_n = 2,
359 .max_n = 16,
360 .inc_n = 1,
361 .min_p = 1,
362 .max_p = 1,
363 .inc_p = 1,
364 },
365 .has_pll_i2s = false,
366 .has_pll_sai = false,
367 .has_pll_i2s_alt_input = false,
368 .has_alt_48MHz = 0,
369 .hsi_prediv = 2,
370 .need_48MHz = false,
371 },
372 [STM32F100] = {
373 .family = STM32F1,
374 .max_coreclock = 24000000U,
375 .max_apb1 = 24000000U,
376 .max_apb2 = 24000000U,
377 .hsi = 8000000U,
378 .pll = {
379 .min_vco_input = 1000000U,
380 .max_vco_input = 24000000U,
381 .min_vco_output = 16000000U,
382 .max_vco_output = 24000000U,
383 .min_m = 1,
384 .max_m = 16,
385 .inc_m = 1,
386 .min_n = 2,
387 .max_n = 16,
388 .inc_n = 1,
389 .min_p = 1,
390 .max_p = 1,
391 .inc_p = 1,
392 },
393 .has_pll_i2s = false,
394 .has_pll_sai = false,
395 .has_pll_i2s_alt_input = false,
396 .has_alt_48MHz = 0,
397 .hsi_prediv = 2,
398 .need_48MHz = false,
399 },
400 [STM32F101 ... STM32F103] = {
401 .family = STM32F1,
402 .max_coreclock = 72000000U,
403 .max_apb1 = 36000000U,
404 .max_apb2 = 72000000U,
405 .hsi = 8000000U,
406 .pll = {
407 .min_vco_input = 1000000U,
408 .max_vco_input = 25000000U,
409 .min_vco_output = 1000000U,
410 .max_vco_output = 72000000U,
411 .min_m = 1,
412 .max_m = 16,
413 .inc_m = 1,
414 .min_n = 2,
415 .max_n = 16,
416 .inc_n = 1,
417 .min_p = 1,
418 .max_p = 1,
419 .inc_p = 1,
420 },
421 .has_pll_i2s = false,
422 .has_pll_sai = false,
423 .has_pll_i2s_alt_input = false,
424 .has_alt_48MHz = 0,
425 .hsi_prediv = 2,
426 .need_48MHz = false,
427 },
428 [STM32F205 ... STM32F217] = {
429 .family = STM32F2,
430 .max_coreclock = 120000000U,
431 .max_apb1 = 30000000U,
432 .max_apb2 = 60000000U,
433 .hsi = 16000000U,
434 .pll = stm32f2_4_192_pll_cfg,
435 .has_pll_i2s = true,
436 .has_pll_sai = false,
437 .has_pll_i2s_alt_input = false,
438 .has_alt_48MHz = 0,
439 .need_48MHz = true,
440 },
441 [STM32F301 ... STM32F398] = {
442 .family = STM32F3,
443 .max_coreclock = 72000000U,
444 .max_apb1 = 36000000U,
445 .max_apb2 = 72000000U,
446 .hsi = 8000000U,
447 .pll = {
448 .min_vco_input = 1000000U,
449 .max_vco_input = 25000000U,
450 .min_vco_output = 1000000U,
451 .max_vco_output = 72000000U,
452 .min_m = 1,
453 .max_m = 16,
454 .inc_m = 1,
455 .min_n = 2,
456 .max_n = 16,
457 .inc_n = 1,
458 .min_p = 1,
459 .max_p = 1,
460 .inc_p = 1,
461 },
462 .has_pll_i2s = false,
463 .has_pll_sai = false,
464 .has_pll_i2s_alt_input = false,
465 .has_alt_48MHz = 0,
466 .hsi_prediv = 2,
467 .need_48MHz = false,
468 },
469 [STM32F401] = {
470 .family = STM32F4,
471 .max_coreclock = 84000000U,
472 .max_apb1 = 42000000U,
473 .max_apb2 = 84000000U,
474 .hsi = 16000000U,
475 .pll = stm32f2_4_192_pll_cfg,
476 .has_pll_i2s = true,
477 .has_pll_sai = false,
478 .has_pll_i2s_m = false,
479 .has_pll_i2s_alt_input = false,
480 .has_alt_48MHz = 0,
481 .need_48MHz = true,
482 },
483 [STM32F405 ... STM32F407] = {
484 .family = STM32F4,
485 .max_coreclock = 168000000U,
486 .max_apb1 = 42000000U,
487 .max_apb2 = 84000000U,
488 .hsi = 16000000U,
489 .pll = stm32f4_7_pll_cfg,
490 .has_pll_i2s = true,
491 .has_pll_sai = false,
492 .has_pll_i2s_m = false,
493 .has_pll_i2s_alt_input = false,
494 .has_alt_48MHz = 0,
495 .need_48MHz = true,
496 },
497 [STM32F410] = {
498 .family = STM32F4,
499 .max_coreclock = 100000000U,
500 .max_apb1 = 50000000U,
501 .max_apb2 = 100000000U,
502 .hsi = 16000000U,
503 .pll = stm32f4_7_pll_cfg,
504 .has_pll_i2s = false,
505 .has_pll_sai = false,
506 .has_pll_i2s_m = false,
507 .has_pll_i2s_alt_input = false,
508 .has_alt_48MHz = 0,
509 .need_48MHz = true,
510 },
511 [STM32F411] = {
512 .family = STM32F4,
513 .max_coreclock = 100000000U,
514 .max_apb1 = 50000000U,
515 .max_apb2 = 100000000U,
516 .hsi = 16000000U,
517 .pll = stm32f4_7_pll_cfg,
518 .has_pll_i2s = true,
519 .has_pll_sai = false,
520 .has_pll_i2s_m = true,
521 .has_pll_i2s_alt_input = false,
522 .has_alt_48MHz = 0,
523 .need_48MHz = true,
524 },
525 [STM32F412 ... STM32F413] = {
526 .family = STM32F4,
527 .max_coreclock = 100000000U,
528 .max_apb1 = 50000000U,
529 .max_apb2 = 100000000U,
530 .hsi = 16000000U,
531 .pll = stm32f4_7_pll_cfg,
532 .has_pll_i2s = true,
533 .has_pll_sai = true,
534 .has_pll_i2s_m = true,
535 .has_pll_sai_m = false,
536 .has_pll_i2s_alt_input = true,
537 .has_alt_48MHz = ALT_48MHZ_I2S,
538 .need_48MHz = true,
539 },
540 [STM32F415 ... STM32F417] = {
541 .family = STM32F4,
542 .max_coreclock = 168000000U,
543 .max_apb1 = 42000000U,
544 .max_apb2 = 84000000U,
545 .hsi = 16000000U,
546 .pll = stm32f4_7_pll_cfg,
547 .has_pll_i2s = true,
548 .has_pll_sai = false,
549 .has_pll_i2s_m = false,
550 .has_pll_i2s_alt_input = false,
551 .has_alt_48MHz = 0,
552 .need_48MHz = true,
553 },
554 [STM32F423] = {
555 .family = STM32F4,
556 .max_coreclock = 100000000U,
557 .max_apb1 = 50000000U,
558 .max_apb2 = 100000000U,
559 .hsi = 16000000U,
560 .pll = stm32f4_7_pll_cfg,
561 .has_pll_i2s = true,
562 .has_pll_sai = true,
563 .has_pll_i2s_m = true,
564 .has_pll_sai_m = false,
565 .has_pll_i2s_alt_input = true,
566 .has_alt_48MHz = ALT_48MHZ_I2S,
567 .need_48MHz = true,
568 },
569 [STM32F427 ... STM32F439] = {
570 .family = STM32F4,
571 .max_coreclock = 180000000U,
572 .max_apb1 = 45000000U,
573 .max_apb2 = 90000000U,
574 .hsi = 16000000U,
575 .pll = stm32f4_7_pll_cfg,
576 .has_pll_i2s = true,
577 .has_pll_sai = true,
578 .has_pll_i2s_m = false,
579 .has_pll_sai_m = false,
580 .has_pll_i2s_alt_input = false,
581 .has_alt_48MHz = 0,
582 .need_48MHz = true,
583 },
584 [STM32F446] = {
585 .family = STM32F4,
586 .max_coreclock = 180000000U,
587 .max_apb1 = 45000000U,
588 .max_apb2 = 90000000U,
589 .hsi = 16000000U,
590 .pll = stm32f4_7_pll_cfg,
591 .has_pll_i2s = true,
592 .has_pll_sai = true,
593 .has_pll_i2s_m = true,
594 .has_pll_sai_m = true,
595 .has_pll_i2s_alt_input = false,
596 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
597 .need_48MHz = true,
598 },
599 [STM32F469 ... STM32F479] = {
600 .family = STM32F4,
601 .max_coreclock = 180000000U,
602 .max_apb1 = 45000000U,
603 .max_apb2 = 90000000U,
604 .hsi = 16000000U,
605 .pll = stm32f4_7_pll_cfg,
606 .has_pll_i2s = true,
607 .has_pll_sai = true,
608 .has_pll_i2s_m = false,
609 .has_pll_sai_m = false,
610 .has_pll_i2s_alt_input = false,
611 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
612 .need_48MHz = true,
613 },
614 [STM32F722 ... STM32F779] = {
615 .family = STM32F7,
616 .max_coreclock = 216000000U,
617 .max_apb1 = 54000000U,
618 .max_apb2 = 108000000U,
619 .hsi = 16000000U,
620 .pll = stm32f4_7_pll_cfg,
621 .has_pll_i2s = true,
622 .has_pll_sai = true,
623 .has_pll_i2s_m = false,
624 .has_pll_sai_m = false,
625 .has_pll_i2s_alt_input = false,
626 .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
627 .need_48MHz = true,
628 },
629};
630
634static const clk_cfg_t stm32_mp_clk_cfg[] = {
635 [STM32MP157] = {
636 .family = STM32MP1,
637 .max_coreclock = 209000000U,
638 .max_apb1 = 104500000U,
639 .max_apb2 = 104500000U,
640 .max_apb3 = 104500000U,
641 .hsi = 64000000U,
642 .pll = stm32mp1_pll_cfg,
643 .has_pll_i2s = false,
644 .has_pll_sai = false,
645 .has_pll_i2s_m = false,
646 .has_pll_sai_m = false,
647 .has_pll_i2s_alt_input = false,
648 .has_alt_48MHz = 0,
649 .need_48MHz = true,
650 },
651};
652
653#ifdef __cplusplus
654}
655#endif
656
clk_cfg_t
Clock configuration.
Definition clk_conf.h:169
clk_cfg_t::max_apb1
unsigned max_apb1
Max APB1 clock.
Definition clk_conf.h:173
clk_cfg_t::has_pll_i2s_m
bool has_pll_i2s_m
PLL I2S has a M factor.
Definition clk_conf.h:183
clk_cfg_t::max_coreclock
unsigned max_coreclock
Max coreclock.
Definition clk_conf.h:172
clk_cfg_t::hsi
unsigned hsi
HSI frequency.
Definition clk_conf.h:177
clk_cfg_t::has_pll_i2s
bool has_pll_i2s
PLL I2S available.
Definition clk_conf.h:181
clk_cfg_t::family
enum fam family
Family.
Definition clk_conf.h:170
clk_cfg_t::max_apb3
unsigned max_apb3
Max APB3 clock.
Definition clk_conf.h:175
clk_cfg_t::pll
pll_cfg_t pll
PLL configuration.
Definition clk_conf.h:179
clk_cfg_t::has_pll_sai
bool has_pll_sai
PLL SAI available.
Definition clk_conf.h:182
clk_cfg_t::has_pll_i2s_alt_input
bool has_pll_i2s_alt_input
PLL I2S has an external input available.
Definition clk_conf.h:185
clk_cfg_t::has_alt_48MHz
int has_alt_48MHz
48MHz can be generated by an alternate source
Definition clk_conf.h:189
clk_cfg_t::hsi_prediv
unsigned hsi_prediv
Value if HSI has a fixed prediv, 0 otherwise.
Definition clk_conf.h:187
clk_cfg_t::need_48MHz
bool need_48MHz
48MHz is needed
Definition clk_conf.h:190
clk_cfg_t::max_apb2
unsigned max_apb2
Max APB2 clock.
Definition clk_conf.h:174
clk_cfg_t::has_pll_sai_m
bool has_pll_sai_m
PLL SAI has a M factor.
Definition clk_conf.h:184
pll_cfg_t
PLL configuration parameters.
Definition clk_conf.h:143
pll_cfg_t::min_vco_output
unsigned min_vco_output
Min VCO output.
Definition clk_conf.h:146
pll_cfg_t::max_n
unsigned max_n
Max N.
Definition clk_conf.h:150
pll_cfg_t::max_vco_input
unsigned max_vco_input
Max VCO input.
Definition clk_conf.h:145
pll_cfg_t::min_vco_input
unsigned min_vco_input
Min VCO input.
Definition clk_conf.h:144
pll_cfg_t::min_m
unsigned min_m
Min M.
Definition clk_conf.h:153
pll_cfg_t::max_m
unsigned max_m
Max M.
Definition clk_conf.h:154
pll_cfg_t::min_n
unsigned min_n
Min N.
Definition clk_conf.h:149
pll_cfg_t::max_p
unsigned max_p
Max P.
Definition clk_conf.h:158
pll_cfg_t::inc_n
unsigned inc_n
Increment between two values of N.
Definition clk_conf.h:151
pll_cfg_t::inc_m
unsigned inc_m
Increment between two values of M.
Definition clk_conf.h:155
pll_cfg_t::min_p
unsigned min_p
Min P.
Definition clk_conf.h:157
pll_cfg_t::inc_p
unsigned inc_p
Increment between two values of P.
Definition clk_conf.h:159
pll_cfg_t::min_q
unsigned min_q
Min Q.
Definition clk_conf.h:161
pll_cfg_t::max_q
unsigned max_q
Max Q.
Definition clk_conf.h:162
pll_cfg_t::max_vco_output
unsigned max_vco_output
Max VCO output.
Definition clk_conf.h:147
pll_cfg_t::inc_q
unsigned inc_q
Increment between two values of Q.
Definition clk_conf.h:163