UART configuration for the RP2350. More...

Detailed Description

UART configuration for the RP2350.

Author: Tom Hert git@a.nosp@m.nnsa.nosp@m.nn.eu

Definition in file uart_conf.h.

#include "RP2350.h"
#include "macros/units.h"
#include "periph_cpu.h"

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Go to the source code of this file.

#define	BAUDRATE 115200u
	UART baud rate in bits per second.

#define	IBRD ((((8u * CPUFREQ) + BAUDRATE) / (2u * BAUDRATE)) / 64u)
	Integer baud rate divisor.

#define	FBRD ((((8u * CPUFREQ) + BAUDRATE) / (2u * BAUDRATE)) % 64u)
	Fractional baud rate divisor.

#define	UART_UARTCR_UARTEN_BITS (1u << 0u)
	UART enable bit in control register.

#define	UART_UARTCR_RXE_BITS (1u << 9u)
	UART receive enable bit in control register.

#define	UART_UARTCR_TXE_BITS (1u << 8u)
	UART transmit enable bit in control register.

#define	UART_UARTFR_RXFF_BITS (1u << 6u)
	UART receive FIFO full flag bit in flag register.

#define	UART_UARTFR_TXFE_BITS (1u << 7u)
	UART transmit FIFO empty flag bit in flag register.

#define	UART0_UARTDR_BE_Msk (0x400UL)
	UART data register break error mask.

#define	UART0_UARTDR_PE_Msk (0x200UL)
	UART data register parity error mask.

#define	UART0_UARTDR_FE_Msk (0x100UL)
	UART data register framing error mask.

#define	UART0_UARTRIS_TXRIS_Msk (0x20UL)
	UART raw interrupt status transmit interrupt mask.

#define	UART0_UARTLCR_H_STP2_Msk (0x8UL)
	UART line control register two stop bits mask.

#define	UART0_UARTLCR_H_EPS_Msk (0x4UL)
	UART line control register even parity select mask.

#define	UART0_UARTLCR_H_PEN_Msk (0x2UL)
	UART line control register parity enable mask.

Macro Definition Documentation

◆ BAUDRATE

#define BAUDRATE 115200u

UART baud rate in bits per second.

Definition at line 24 of file uart_conf.h.

◆ FBRD

#define FBRD ((((8u * CPUFREQ) + BAUDRATE) / (2u * BAUDRATE)) % 64u)

Fractional baud rate divisor.

Definition at line 30 of file uart_conf.h.

◆ IBRD

#define IBRD ((((8u * CPUFREQ) + BAUDRATE) / (2u * BAUDRATE)) / 64u)

Integer baud rate divisor.

Definition at line 27 of file uart_conf.h.

◆ UART0_UARTDR_BE_Msk

#define UART0_UARTDR_BE_Msk (0x400UL)

UART data register break error mask.

Definition at line 48 of file uart_conf.h.

◆ UART0_UARTDR_FE_Msk

#define UART0_UARTDR_FE_Msk (0x100UL)

UART data register framing error mask.

Definition at line 54 of file uart_conf.h.

◆ UART0_UARTDR_PE_Msk

#define UART0_UARTDR_PE_Msk (0x200UL)

UART data register parity error mask.

Definition at line 51 of file uart_conf.h.

◆ UART0_UARTLCR_H_EPS_Msk

#define UART0_UARTLCR_H_EPS_Msk (0x4UL)

UART line control register even parity select mask.

Definition at line 63 of file uart_conf.h.

◆ UART0_UARTLCR_H_PEN_Msk

#define UART0_UARTLCR_H_PEN_Msk (0x2UL)

UART line control register parity enable mask.

Definition at line 66 of file uart_conf.h.

◆ UART0_UARTLCR_H_STP2_Msk

#define UART0_UARTLCR_H_STP2_Msk (0x8UL)

UART line control register two stop bits mask.

Definition at line 60 of file uart_conf.h.

◆ UART0_UARTRIS_TXRIS_Msk

#define UART0_UARTRIS_TXRIS_Msk (0x20UL)

UART raw interrupt status transmit interrupt mask.

Definition at line 57 of file uart_conf.h.

◆ UART_UARTCR_RXE_BITS

#define UART_UARTCR_RXE_BITS (1u << 9u)

UART receive enable bit in control register.

Definition at line 36 of file uart_conf.h.

◆ UART_UARTCR_TXE_BITS

#define UART_UARTCR_TXE_BITS (1u << 8u)

UART transmit enable bit in control register.

Definition at line 39 of file uart_conf.h.

◆ UART_UARTCR_UARTEN_BITS

#define UART_UARTCR_UARTEN_BITS (1u << 0u)

UART enable bit in control register.

Definition at line 33 of file uart_conf.h.

◆ UART_UARTFR_RXFF_BITS

#define UART_UARTFR_RXFF_BITS (1u << 6u)

UART receive FIFO full flag bit in flag register.

Definition at line 42 of file uart_conf.h.

◆ UART_UARTFR_TXFE_BITS

#define UART_UARTFR_TXFE_BITS (1u << 7u)

UART transmit FIFO empty flag bit in flag register.

Definition at line 45 of file uart_conf.h.