w5500__regs_8h_source.html

/*

 * Copyright (C) 2023 Stefan Schmidt

 *

 * This file is subject to the terms and conditions of the GNU Lesser

 * General Public License v2.1. See the file LICENSE in the top level

 * directory for more details.

 */


#ifndef W5500_REGS_H

#define W5500_REGS_H


#ifdef __cplusplus

extern "C" {

#endif


/* The W5500 is accessed by sending a 16 Bit address first, then a 8 bit control byte

   which determines to which register (common or one of the 8 Sockets) this address shall be

   applied and finally the data.


   In order to simplify the functions to read and write to the W5500 via SPI the defined register

   addresses contain the control byte in the upper 5 bits and the actual register address in the

   lower 13 bits:

   0b00000 -> common register     (0x0xxx)

   0b00001 -> Socket 0 register   (0x08xx)


   The RX and TX buffers are accessed via separate functions in order to be able to access the full

   16 kB buffers.

 */


#define REG_MODE            (0x0000)

#define REG_GAR0            (0x0001)

#define REG_GAR1            (0x0002)

#define REG_GAR2            (0x0003)

#define REG_GAR3            (0x0004)

#define REG_SUBR0           (0x0005)

#define REG_SUBR1           (0x0006)

#define REG_SUBR2           (0x0007)

#define REG_SUBR3           (0x0008)

#define REG_SHAR0           (0x0009)

#define REG_SHAR1           (0x000a)

#define REG_SHAR2           (0x000b)

#define REG_SHAR3           (0x000c)

#define REG_SHAR4           (0x000d)

#define REG_SHAR5           (0x000e)

#define REG_SIPR0           (0x000f)

#define REG_SIPR1           (0x0010)

#define REG_SIPR2           (0x0011)

#define REG_SIPR3           (0x0012)

#define REG_INTLEVEL0       (0x0013)

#define REG_INTLEVEL1       (0x0014)

#define REG_IR              (0x0015)

#define REG_IMR             (0x0016)

#define REG_SIR             (0x0017)

#define REG_SIMR            (0x0018)

#define REG_RTR0            (0x0019)

#define REG_RTR1            (0x001a)

#define REG_RCR             (0x001b)

#define REG_PTIMER          (0x001c)

#define REG_PMAGIC          (0x001d)

#define REG_PHAR0           (0x001e)

#define REG_PHAR1           (0x001f)

#define REG_PHAR2           (0x0020)

#define REG_PHAR3           (0x0021)

#define REG_PHAR4           (0x0022)

#define REG_PHAR5           (0x0023)

#define REG_PSID0           (0x0024)

#define REG_PSID1           (0x0025)

#define REG_PMRU0           (0x0026)

#define REG_PMRU1           (0x0027)

#define REG_UIPR0           (0x0028)

#define REG_UIPR1           (0x0029)

#define REG_UIPR2           (0x002a)

#define REG_UIPR3           (0x002b)

#define REG_UPORT0          (0x002c)

#define REG_UPORT1          (0x002d)

#define REG_PHYCFGR         (0x002e)

#define REG_VERSIONR        (0x0039)

#define REG_S0_MR               (0x0800)

#define REG_S0_CR               (0x0801)

#define REG_S0_IR               (0x0802)

#define REG_S0_SR               (0x0803)

#define REG_S0_PORT0            (0x0804)

#define REG_S0_PORT1            (0x0805)

#define REG_S0_DHAR0            (0x0806)

#define REG_S0_DHAR1            (0x0807)

#define REG_S0_DHAR2            (0x0808)

#define REG_S0_DHAR3            (0x0809)

#define REG_S0_DHAR4            (0x080a)

#define REG_S0_DHAR5            (0x080b)

#define REG_S0_DIPR0            (0x080c)

#define REG_S0_DIPR1            (0x080d)

#define REG_S0_DIPR2            (0x080e)

#define REG_S0_DIPR3            (0x080f)

#define REG_S0_DPORT0           (0x0810)

#define REG_S0_DPORT1           (0x0811)

#define REG_S0_MSSR0            (0x0812)

#define REG_S0_MSSR1            (0x0813)

#define REG_S0_TOS              (0x0815)

#define REG_S0_TTL              (0x0816)

#define REG_S0_RXBUF_SIZE       (0x081e)

#define REG_S0_TXBUF_SIZE       (0x081f)

#define REG_S0_TX_FSR0          (0x0820)

#define REG_S0_TX_FSR1          (0x0821)

#define REG_S0_TX_RD0           (0x0822)

#define REG_S0_TX_RD1           (0x0823)

#define REG_S0_TX_WR0           (0x0824)

#define REG_S0_TX_WR1           (0x0825)

#define REG_S0_RX_RSR0          (0x0826)

#define REG_S0_RX_RSR1          (0x0827)

#define REG_S0_RX_RD0           (0x0828)

#define REG_S0_RX_RD1           (0x0829)

#define REG_S0_RX_WR0           (0x082a)

#define REG_S0_RX_WR1           (0x082b)

#define REG_S0_IMR              (0x082c)

#define REG_S0_FRAG0            (0x082d)

#define REG_S0_FRAG1            (0x082e)

#define REG_S0_KPALVTR          (0x082f)

#define Sn_RXBUF_SIZE_BASE      (0x001E)

#define Sn_TXBUF_SIZE_BASE      (0x001F)

/* Common definitions. */

#define MODE_RESET              (0x80)

#define PHY_LINK_UP             (0x01)

#define IMR_S0_INT              (0x01)

#define SPI_CONF                SPI_MODE_0

#define CHIP_VERSION            (0x04)

#define ENABLE_MAC_FILTER       (0x80)

#define ENABLE_BROADCAST_FILTER (0x40)

#define ENABLE_MULTICAST_FILTER (0x20)

#define MR_MACRAW               (0x04)

#define CR_OPEN                 (0x01)

#define CR_SEND                 (0x20)

#define CR_RECV                 (0x40)

#define IR_RECV                 (0x04)

#define IR_SEND_OK              (0x10)

#define CMD_READ                (0x00)

#define CMD_WRITE               (0x04)

#define SOCKET0_RX_BUFFER       (0x18)

#define SOCKET0_TX_BUFFER       (0x10)

#ifdef __cplusplus

}

#endif


#endif /* W5500_REGS_H */