periph_cpu.h

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/*
 * Copyright (C) 2021 Otto-von-Guericke-Universität Magdeburg
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include "cpu.h"
#include "vendor/RP2040.h"
#include "io_reg.h"
#include "macros/units.h"
#include "periph/pio.h" /* pio_t */
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if !defined(PLL_SYS_REF_DIV) || defined(DOXYGEN)
#define PLL_SYS_REF_DIV         1
#endif
 
#if !defined(PLL_USB_REF_DIV) || defined(DOXYGEN)
#define PLL_USB_REF_DIV         1
#endif
 
#if !defined(PLL_SYS_VCO_FEEDBACK_SCALE) || defined(DOXYGEN)
#define PLL_SYS_VCO_FEEDBACK_SCALE  125
#endif
 
#if !defined(PLL_SYS_POSTDIV1) || defined(DOXYGEN)
#define PLL_SYS_POSTDIV1            6
#endif
 
#if !defined(PLL_SYS_POSTDIV2) || defined(DOXYGEN)
#define PLL_SYS_POSTDIV2            2
#endif
 
#if !defined(PLL_USB_VCO_FEEDBACK_SCALE) || defined(DOXYGEN)
#define PLL_USB_VCO_FEEDBACK_SCALE  40
#endif
 
#if !defined(PLL_USB_POSTDIV1) || defined(DOXYGEN)
#define PLL_USB_POSTDIV1            5
#endif
 
#if !defined(PLL_USB_POSTDIV2) || defined(DOXYGEN)
#define PLL_USB_POSTDIV2            2
#endif
 
#if !defined(CLOCK_XOSC) || defined(DOXYGEN)
#define CLOCK_XOSC          MHZ(12)
#endif
 
#define PLL_CLOCK(vco_feedback, postdiv1, postdiv2) \
    (CLOCK_XOSC * (vco_feedback) / (postdiv1) / (postdiv2))
 
#define CLOCK_CORECLOCK \
    PLL_CLOCK(PLL_SYS_VCO_FEEDBACK_SCALE, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2)
 
#define CLOCK_USB \
    PLL_CLOCK(PLL_USB_VCO_FEEDBACK_SCALE, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2)
 
#define CLOCK_XOSC_MAX              MHZ(15) 
#define CLOCK_XOSC_MIN              MHZ(5)  
#define PLL_POSTDIV_MIN             (1U)    
#define PLL_POSTDIV_MAX             (7U)    
#define PLL_VCO_FEEDBACK_SCALE_MIN  (16U)   
#define PLL_VCO_FEEDBACK_SCALE_MAX  (320U)  
#define PLL_REF_DIV_MIN             (1U)    
#define PLL_REF_DIV_MAX             (1U)    
#if CLOCK_USB != MHZ(48)
#error "USB clock != 48 MHz, check PLL_USB_VCO_FEEDBACK_SCALE, PLL_USB_POSTDIV1, PLL_SYS_POSTDIV2"
#endif
 
#if (CLOCK_XOSC > CLOCK_XOSC_MAX) || (CLOCK_XOSC < CLOCK_XOSC_MIN)
#error "Value for CLOCK_XOSC out of range, check config"
#endif
 
#if (PLL_SYS_REF_DIV < PLL_REF_DIV_MIN) || (PLL_SYS_REF_DIV > PLL_REF_DIV_MAX)
#error "Value for PLL_SYS_REF_DIV out of range, check config"
#endif
 
#if (PLL_USB_REF_DIV < PLL_REF_DIV_MIN) || (PLL_USB_REF_DIV > PLL_REF_DIV_MAX)
#error "Value for PLL_USB_REF_DIV out of range, check config"
#endif
 
#if (PLL_SYS_VCO_FEEDBACK_SCALE < PLL_VCO_FEEDBACK_SCALE_MIN) \
    || (PLL_SYS_VCO_FEEDBACK_SCALE > PLL_VCO_FEEDBACK_SCALE_MAX)
#error "Value for PLL_SYS_VCO_FEEDBACK_SCALE out of range, check config"
#endif
 
#if (PLL_USB_VCO_FEEDBACK_SCALE < PLL_VCO_FEEDBACK_SCALE_MIN) \
    || (PLL_USB_VCO_FEEDBACK_SCALE > PLL_VCO_FEEDBACK_SCALE_MAX)
#error "Value for PLL_USB_VCO_FEEDBACK_SCALE out of range, check config"
#endif
 
#if (PLL_SYS_POSTDIV1 < PLL_POSTDIV_MIN) || (PLL_SYS_POSTDIV1 > PLL_POSTDIV_MAX)
#error "Value for PLL_SYS_POSTDIV1 out of range, check config"
#endif
 
#if (PLL_SYS_POSTDIV2 < PLL_POSTDIV_MIN) || (PLL_SYS_POSTDIV2 > PLL_POSTDIV_MAX)
#error "Value for PLL_SYS_POSTDIV2 out of range, check config"
#endif
 
#if (PLL_USB_POSTDIV1 < PLL_POSTDIV_MIN) || (PLL_USB_POSTDIV1 > PLL_POSTDIV_MAX)
#error "Value for PLL_USB_POSTDIV1 out of range, check config"
#endif
 
#if (PLL_USB_POSTDIV2 < PLL_POSTDIV_MIN) || (PLL_USB_POSTDIV2 > PLL_POSTDIV_MAX)
#error "Value for PLL_USB_POSTDIV2 out of range, check config"
#endif
 
#if !defined(CLOCK_PERIPH_SOURCE) || defined(DOXYGEN)
#define CLOCK_PERIPH_SOURCE CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys
#endif
 
#if !defined(CLOCK_PERIPH) || defined(DOXYGEN)
#define CLOCK_PERIPH        CLOCK_CORECLOCK
#endif
 
#define RESETS_RESET_MASK               \
    (RESETS_RESET_usbctrl_Msk       |   \
     RESETS_RESET_uart1_Msk         |   \
     RESETS_RESET_uart0_Msk         |   \
     RESETS_RESET_timer_Msk         |   \
     RESETS_RESET_tbman_Msk         |   \
     RESETS_RESET_sysinfo_Msk       |   \
     RESETS_RESET_syscfg_Msk        |   \
     RESETS_RESET_spi1_Msk          |   \
     RESETS_RESET_spi0_Msk          |   \
     RESETS_RESET_rtc_Msk           |   \
     RESETS_RESET_pwm_Msk           |   \
     RESETS_RESET_pll_usb_Msk       |   \
     RESETS_RESET_pll_sys_Msk       |   \
     RESETS_RESET_pio1_Msk          |   \
     RESETS_RESET_pio0_Msk          |   \
     RESETS_RESET_pads_qspi_Msk     |   \
     RESETS_RESET_pads_bank0_Msk    |   \
     RESETS_RESET_jtag_Msk          |   \
     RESETS_RESET_io_qspi_Msk       |   \
     RESETS_RESET_io_bank0_Msk      |   \
     RESETS_RESET_i2c1_Msk          |   \
     RESETS_RESET_i2c0_Msk          |   \
     RESETS_RESET_dma_Msk           |   \
     RESETS_RESET_busctrl_Msk       |   \
     RESETS_RESET_adc_Msk)
 
#define GPIO_PIN(port, pin)     ((((port) & 0)) | (pin))
 
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO_UNDEF          UINT32_MAX
 
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_LEVEL_LOW  = 0x1,          
    GPIO_LEVEL_HIGH = 0x2,          
    GPIO_FALLING    = 0x4,          
    GPIO_RISING     = 0x8,          
    GPIO_BOTH       = 0xc           
} gpio_flank_t;
#define GPIO_PAD_REGISTER_RESET_VALUE    (0x00000056)
enum {
    DRIVE_STRENGTH_2MA,         
    DRIVE_STRENGTH_4MA,         
    DRIVE_STRENGTH_8MA,         
    DRIVE_STRENGTH_12MA,        
    DRIVE_STRENGTH_NUMOF        
};
 
typedef struct {
    uint32_t slew_rate_fast         : 1;    
    uint32_t schmitt_trig_enable    : 1;    
    uint32_t pull_down_enable       : 1;    
    uint32_t pull_up_enable         : 1;    
    uint32_t drive_strength         : 2;    
    uint32_t input_enable           : 1;    
    uint32_t output_disable         : 1;    
    uint32_t                        : 24;   
} gpio_pad_ctrl_t;
#define GPIO_IO_REGISTER_RESET_VALUE    (0x0000001f)
typedef enum {
    FUNCTION_SELECT_SPI     = 1,    
    FUNCTION_SELECT_UART    = 2,    
    FUNCTION_SELECT_I2C     = 3,    
    FUNCTION_SELECT_PWM     = 4,    
    FUNCTION_SELECT_SIO     = 5,    
    FUNCTION_SELECT_PIO0    = 6,    
    FUNCTION_SELECT_PIO1    = 7,    
    FUNCTION_SELECT_CLOCK   = 8,    
    FUNCTION_SELECT_USB     = 9,    
    FUNCTION_SELECT_NONE    = 31,   
} gpio_function_select_t;
 
enum {
    OUTPUT_OVERRIDE_NORMAL,         
    OUTPUT_OVERRIDE_INVERT,         
    OUTPUT_OVERRIDE_LOW,            
    OUTPUT_OVERRIDE_HIGH,           
    OUTPUT_OVERRIDE_NUMOF           
};
 
enum {
    OUTPUT_ENABLE_OVERRIDE_NOMARL,  
    OUTPUT_ENABLE_OVERRIDE_INVERT,  
    OUTPUT_ENABLE_OVERRIDE_DISABLE, 
    OUTPUT_ENABLE_OVERRIDE_ENABLE,  
    OUTPUT_ENABLE_OVERRIDE_NUMOF    
};
 
enum {
    INPUT_OVERRIDE_NOMARL,          
    INPUT_OVERRIDE_INVERT,          
    INPUT_OVERRIDE_LOW,             
    INPUT_OVERRIDE_HIGH,            
    INPUT_OVERRIDE_NUMOF            
};
 
enum {
    IRQ_OVERRIDE_NORMAL,            
    IRQ_OVERRIDE_INVERT,            
    IRQ_OVERRIDE_LOW,               
    IRQ_OVERRIDE_HIGH,              
    IRQ_OVERRIDE_NUMOF              
};
 
typedef struct {
    uint32_t function_select        : 5;    
    uint32_t                        : 3;    
    uint32_t output_override        : 2;    
    uint32_t                        : 2;    
    uint32_t output_enable_override : 2;    
    uint32_t                        : 2;    
    uint32_t input_override         : 2;    
    uint32_t                        : 10;   
    uint32_t irq_override           : 2;    
    uint32_t                        : 2;    
} gpio_io_ctrl_t;
typedef struct {
    gpio_t pin;             
    uint8_t chan;           
} adc_conf_t;
 
#define PWM_SLICE_NUMOF   (8)
 
#define PWM_CHANNEL_NUMOF (2)
 
typedef struct {
    gpio_t pin;             
    uint8_t cc_chan;        
} pwm_chan_t;
 
typedef struct {
    uint8_t pwm_slice;                      
    pwm_chan_t chan[PWM_CHANNEL_NUMOF];     
} pwm_conf_t;
 
typedef struct {
    UART0_Type *dev;    
    gpio_t rx_pin;      
    gpio_t tx_pin;      
    IRQn_Type irqn;     
} uart_conf_t;
 
#define PERIPH_TIMER_PROVIDES_SET
 
typedef struct {
    IRQn_Type irqn;                 
} timer_channel_conf_t;
 
typedef struct {
    TIMER_Type *dev;                
    const timer_channel_conf_t *ch; 
    uint8_t ch_numof;               
} timer_conf_t;
 
typedef struct {
    PIO0_Type *dev;                 
    IRQn_Type irqn0;                
    IRQn_Type irqn1;                
} pio_conf_t;
 
typedef struct {
    pio_t pio;                      
    gpio_t sda;                     
    gpio_t scl;                     
    unsigned irq;                   
} pio_i2c_conf_t;
 
static inline volatile uint32_t * gpio_pad_register(uint8_t pin)
{
    return (uint32_t *)(PADS_BANK0_BASE + 4 + (pin << 2));
}
 
static inline void gpio_set_pad_config(uint8_t pin, gpio_pad_ctrl_t config)
{
    uint32_t *c = (uint32_t *)&config;
    *gpio_pad_register(pin) = *c;
}
 
static inline volatile uint32_t * gpio_io_register(uint8_t pin)
{
    return (uint32_t *)(IO_BANK0_BASE + 4 + (pin << 3));
}
 
static inline void gpio_set_io_config(uint8_t pin, gpio_io_ctrl_t config)
{
    uint32_t *c = (uint32_t *)&config;
    *gpio_io_register(pin) = *c;
}
 
static inline void gpio_set_function_select(uint8_t pin, gpio_function_select_t funcsel)
{
    io_reg_write_dont_corrupt(gpio_io_register(pin), funcsel << IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos,
                              IO_BANK0_GPIO0_CTRL_FUNCSEL_Msk);
}
 
static inline void gpio_reset_all_config(uint8_t pin)
{
    *gpio_io_register(pin) = GPIO_IO_REGISTER_RESET_VALUE;
    *gpio_pad_register(pin) = GPIO_PAD_REGISTER_RESET_VALUE;
}
 
static inline void periph_reset(uint32_t components)
{
    io_reg_atomic_set(&RESETS->RESET, components);
}
 
static inline void periph_reset_done(uint32_t components)
{
    io_reg_atomic_clear(&RESETS->RESET, components);
    while ((~RESETS->RESET_DONE) & components) { }
}
 
void clock_sys_configure_source(uint32_t f_in, uint32_t f_out,
                                CLOCKS_CLK_SYS_CTRL_SRC_Enum source);
 
void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out,
                                    CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum aux);
 
void clock_ref_configure_source(uint32_t f_in, uint32_t f_out,
                                CLOCKS_CLK_REF_CTRL_SRC_Enum source);
 
void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out,
                                    CLOCKS_CLK_REF_CTRL_AUXSRC_Enum aux);
 
void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux);
 
void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux);
 
void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum aux);
 
void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum aux);
 
void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux);
 
void clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux);
void pll_start_sys(uint8_t ref_div,
                   uint16_t vco_feedback_scale,
                   uint8_t post_div_1, uint8_t post_div_2);
 
void pll_start_usb(uint8_t ref_div,
                   uint16_t vco_feedback_scale,
                   uint8_t post_div_1, uint8_t post_div_2);
 
void pll_stop_sys(void);
 
void pll_stop_usb(void);
 
void pll_reset_sys(void);
 
void pll_reset_usb(void);
 
void xosc_start(uint32_t f_ref);
 
void xosc_stop(void);
 
void rosc_start(void);
 
void rosc_stop(void);
 
#define HAVE_SPI_CLK_T
enum {
    SPI_CLK_100KHZ = KHZ(100), 
    SPI_CLK_400KHZ = KHZ(400), 
    SPI_CLK_1MHZ   = MHZ(1),   
    SPI_CLK_5MHZ   = MHZ(5),   
    SPI_CLK_10MHZ  = MHZ(10),  
};
 
typedef uint32_t spi_clk_t;
typedef struct {
    SPI0_Type *dev;     
    gpio_t miso_pin;    
    gpio_t mosi_pin;    
    gpio_t clk_pin;     
} spi_conf_t;
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */