at86rf215_internal.h

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/*
 * Copyright (C) 2019 ML!PA Consulting GmbH
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once

 
#include <stdint.h>
#include "at86rf215.h"
#include "at86rf215_registers.h"
#include "board.h"
 
#ifdef __cplusplus
extern "C" {
#endif

#ifndef CONFIG_AT86RF215_RESET_PULSE_WIDTH_US
#define CONFIG_AT86RF215_RESET_PULSE_WIDTH_US  (16U)
#endif

#define AT86RF215_RESET_DELAY_US        (16U)

#define AT86RF215_EDT_DEFAULT           (-84) /* dBm */

#define AT86RF215_RETRIES_MAX_DEFAULT       (3)
#define AT86RF215_CSMA_RETRIES_MAX_DEFAULT  (4)
#define AT86RF215_CSMA_MIN_BE_DEFAULT       (3)
#define AT86RF215_CSMA_MAX_BE_DEFAULT       (5)

#define AT86RF215_ACK_PSDU_BYTES            (5)
 
#define AT86RF215_OQPSK_MODE_LEGACY           (0x1)                             
#define AT86RF215_OQPSK_MODE_LEGACY_HDR       (0x3)                             
#define AT86RF215_MR_OQPSK_MODE(n)            ((n) << OQPSKPHRTX_MOD_SHIFT)     

int at86rf215_hardware_reset(at86rf215_t *dev);

void at86rf215_reg_write(const at86rf215_t *dev, uint16_t reg, uint8_t val);

void at86rf215_reg_write_bytes(const at86rf215_t *dev, uint16_t reg, const void *data, size_t len);

uint8_t at86rf215_reg_read(const at86rf215_t *dev, uint16_t reg);

void at86rf215_reg_read_bytes(const at86rf215_t *dev, uint16_t reg, void *data, size_t len);

void at86rf215_filter_ack(at86rf215_t *dev, bool on);

void at86rf215_get_random(at86rf215_t *dev, void *data, size_t len);


extern const uint8_t _at86rf215_fsk_srate_10kHz[];

extern const uint8_t _at86rf215_fsk_channel_spacing_25kHz[];

int at86rf215_configure_FSK(at86rf215_t *dev, uint8_t srate, uint8_t mod_idx, uint8_t mod_order, uint8_t fec);

int at86rf215_FSK_set_srate(at86rf215_t *dev, uint8_t srate);

uint8_t at86rf215_FSK_get_srate(at86rf215_t *dev);

int at86rf215_FSK_set_mod_idx(at86rf215_t *dev, uint8_t mod_idx);

uint8_t at86rf215_FSK_get_mod_idx(at86rf215_t *dev);

int at86rf215_FSK_set_fec(at86rf215_t *dev, uint8_t mode);

uint8_t at86rf215_FSK_get_fec(at86rf215_t *dev);

int at86rf215_FSK_set_channel_spacing(at86rf215_t *dev, uint8_t ch_space);

uint16_t at86rf215_get_channel_spacing(at86rf215_t *dev);

int at86rf215_FSK_set_mod_order(at86rf215_t *dev, uint8_t mod_order);

uint8_t at86rf215_FSK_get_mod_order(at86rf215_t *dev);

void at86rf215_FSK_prepare_rx(at86rf215_t *dev);

void at86rf215_FSK_prepare_tx(at86rf215_t *dev);


int at86rf215_configure_OFDM(at86rf215_t *dev, uint8_t option, uint8_t mcs);

int at86rf215_OFDM_set_scheme(at86rf215_t *dev, uint8_t mcs);

uint8_t at86rf215_OFDM_get_scheme(at86rf215_t *dev);

int at86rf215_OFDM_set_option(at86rf215_t *dev, uint8_t option);

uint8_t at86rf215_OFDM_get_option(at86rf215_t *dev);



int at86rf215_configure_legacy_OQPSK(at86rf215_t *dev, bool high_rate);

int at86rf215_configure_OQPSK(at86rf215_t *dev, uint8_t chips, uint8_t rate);

uint8_t at86rf215_OQPSK_get_chips(at86rf215_t *dev);

int at86rf215_OQPSK_set_chips(at86rf215_t *dev, uint8_t chips);

uint8_t at86rf215_OQPSK_get_mode(at86rf215_t *dev);

int at86rf215_OQPSK_set_mode(at86rf215_t *dev, uint8_t mode);

uint8_t at86rf215_OQPSK_get_mode_legacy(at86rf215_t *dev);

int at86rf215_OQPSK_set_mode_legacy(at86rf215_t *dev, bool high_rate);

static inline bool at86rf215_OQPSK_is_legacy(at86rf215_t *dev) {
    return at86rf215_reg_read(dev, dev->BBC->RG_OQPSKPHRTX) & AT86RF215_OQPSK_MODE_LEGACY;
}


uint8_t at86rf215_get_phy_mode(at86rf215_t *dev);

uint16_t at86rf215_chan_valid(at86rf215_t *dev, uint16_t chan);

const char* at86rf215_hw_state2a(uint8_t state);

const char* at86rf215_sw_state2a(at86rf215_state_t state);

static inline void at86rf215_reg_and(const at86rf215_t *dev, uint16_t reg, uint8_t val)
{
    val &= at86rf215_reg_read(dev, reg);
    at86rf215_reg_write(dev, reg, val);
}

static inline void at86rf215_reg_or(const at86rf215_t *dev, uint16_t reg, uint8_t val)
{
    val |= at86rf215_reg_read(dev, reg);
    at86rf215_reg_write(dev, reg, val);
}

static inline void at86rf215_reg_write16(const at86rf215_t *dev, uint16_t reg, uint16_t val)
{
    at86rf215_reg_write_bytes(dev, reg, &val, sizeof(val));
}

static inline uint16_t at86rf215_reg_read16(const at86rf215_t *dev, uint16_t reg)
{
    uint16_t value;
    at86rf215_reg_read_bytes(dev, reg, &value, sizeof(value));
    return value;
}

static inline void at86rf215_rf_cmd(const at86rf215_t *dev, uint8_t rf_cmd)
{
    at86rf215_reg_write(dev, dev->RF->RG_CMD, rf_cmd);
}

static inline uint8_t at86rf215_get_rf_state(const at86rf215_t *dev)
{
    return at86rf215_reg_read(dev, dev->RF->RG_STATE) & STATE_STATE_MASK;
}

static inline void at86rf215_await_state(const at86rf215_t *dev, uint8_t state)
{
    while (at86rf215_get_rf_state(dev) != state) {}
}

static inline void at86rf215_await_state_end(const at86rf215_t *dev, uint8_t state)
{
    while (at86rf215_get_rf_state(dev) == state) {}
}

bool at86rf215_set_rx_from_idle(at86rf215_t *dev, uint8_t *old_state);

bool at86rf215_set_idle_from_rx(at86rf215_t *dev, uint8_t state);

static inline void at86rf215_enable_baseband(const at86rf215_t *dev)
{
    at86rf215_reg_or(dev, dev->BBC->RG_PC, PC_BBEN_MASK);
}

static inline void at86rf215_disable_baseband(const at86rf215_t *dev) {
    at86rf215_reg_and(dev, dev->BBC->RG_PC, ~PC_BBEN_MASK);
}

static inline void at86rf215_enable_radio(at86rf215_t *dev, uint8_t modulation)
{
    /* 16 bit frame-checksum, baseband enabled, checksum calculated by chip,
       frames with invalid cs are dropped */
    at86rf215_reg_write(dev, dev->BBC->RG_PC, modulation   | PC_BBEN_MASK
                                            | PC_FCST_MASK | PC_TXAFCS_MASK
                                            | PC_FCSFE_MASK);
}

void at86rf215_disable_rpc(at86rf215_t *dev);

void at86rf215_enable_rpc(at86rf215_t *dev);

static inline bool is_subGHz(const at86rf215_t *dev)
{
    return dev->RF->RG_IRQS == RG_RF09_IRQS;
}
 
#ifdef __cplusplus
}
#endif