Register and command definitions for AT86RF2xx devices.
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◆ AT86RF212B_PARTNUM
#define AT86RF212B_PARTNUM (0x07) |
◆ AT86RF231_PARTNUM
#define AT86RF231_PARTNUM (0x03) |
◆ AT86RF232_PARTNUM
#define AT86RF232_PARTNUM (0x0a) |
◆ AT86RF233_PARTNUM
#define AT86RF233_PARTNUM (0x0b) |
◆ AT86RF2XX_ACCESS_FB
#define AT86RF2XX_ACCESS_FB (0x20) |
◆ AT86RF2XX_ACCESS_READ
#define AT86RF2XX_ACCESS_READ (0x00) |
◆ AT86RF2XX_ACCESS_REG
#define AT86RF2XX_ACCESS_REG (0x80) |
◆ AT86RF2XX_ACCESS_SRAM
#define AT86RF2XX_ACCESS_SRAM (0x00) |
◆ AT86RF2XX_ACCESS_WRITE
#define AT86RF2XX_ACCESS_WRITE (0x40) |
◆ AT86RF2XX_CCA_THRES_MASK__CCA_ED_THRES
#define AT86RF2XX_CCA_THRES_MASK__CCA_ED_THRES (0x0F) |
◆ AT86RF2XX_CCA_THRES_MASK__RSVD_HI_NIBBLE
#define AT86RF2XX_CCA_THRES_MASK__RSVD_HI_NIBBLE (0xC0) |
◆ AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK
#define AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10) |
◆ AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD
#define AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08) |
◆ AT86RF2XX_CSMA_SEED_1__AACK_SET_PD
#define AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20) |
◆ AT86RF2XX_CSMA_SEED_1__CSMA_SEED_1
#define AT86RF2XX_CSMA_SEED_1__CSMA_SEED_1 (0x07) |
◆ AT86RF2XX_IRQ_STATUS_MASK__AMI
#define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20) |
◆ AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW
#define AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80) |
◆ AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE
#define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10) |
◆ AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK
#define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01) |
◆ AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK
#define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02) |
◆ AT86RF2XX_IRQ_STATUS_MASK__RX_START
#define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04) |
◆ AT86RF2XX_IRQ_STATUS_MASK__TRX_END
#define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08) |
◆ AT86RF2XX_IRQ_STATUS_MASK__TRX_UR
#define AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40) |
◆ AT86RF2XX_PARTNUM
#define AT86RF2XX_PARTNUM AT86RF231_PARTNUM |
◆ AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE
#define AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20) |
◆ AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE
#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60) |
◆ AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST
#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80) |
◆ AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL
#define AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F) |
◆ AT86RF2XX_PHY_RSSI_MASK__RND_VALUE
#define AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60) |
◆ AT86RF2XX_PHY_RSSI_MASK__RSSI
#define AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F) |
◆ AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID
#define AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80) |
◆ AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT
#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0) |
◆ AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT
#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00) |
◆ AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR
#define AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00) |
◆ AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR
#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F) |
◆ AT86RF2XX_REG__ANT_DIV
#define AT86RF2XX_REG__ANT_DIV (0x0D) |
◆ AT86RF2XX_REG__BATMON
#define AT86RF2XX_REG__BATMON (0x11) |
◆ AT86RF2XX_REG__CC_CTRL_1
#define AT86RF2XX_REG__CC_CTRL_1 (0x14) |
◆ AT86RF2XX_REG__CCA_THRES
#define AT86RF2XX_REG__CCA_THRES (0x09) |
◆ AT86RF2XX_REG__CSMA_BE
#define AT86RF2XX_REG__CSMA_BE (0x2F) |
◆ AT86RF2XX_REG__CSMA_SEED_0
#define AT86RF2XX_REG__CSMA_SEED_0 (0x2D) |
◆ AT86RF2XX_REG__CSMA_SEED_1
#define AT86RF2XX_REG__CSMA_SEED_1 (0x2E) |
◆ AT86RF2XX_REG__FTN_CTRL
#define AT86RF2XX_REG__FTN_CTRL (0x18) |
◆ AT86RF2XX_REG__IEEE_ADDR_0
#define AT86RF2XX_REG__IEEE_ADDR_0 (0x24) |
◆ AT86RF2XX_REG__IEEE_ADDR_1
#define AT86RF2XX_REG__IEEE_ADDR_1 (0x25) |
◆ AT86RF2XX_REG__IEEE_ADDR_2
#define AT86RF2XX_REG__IEEE_ADDR_2 (0x26) |
◆ AT86RF2XX_REG__IEEE_ADDR_3
#define AT86RF2XX_REG__IEEE_ADDR_3 (0x27) |
◆ AT86RF2XX_REG__IEEE_ADDR_4
#define AT86RF2XX_REG__IEEE_ADDR_4 (0x28) |
◆ AT86RF2XX_REG__IEEE_ADDR_5
#define AT86RF2XX_REG__IEEE_ADDR_5 (0x29) |
◆ AT86RF2XX_REG__IEEE_ADDR_6
#define AT86RF2XX_REG__IEEE_ADDR_6 (0x2A) |
◆ AT86RF2XX_REG__IEEE_ADDR_7
#define AT86RF2XX_REG__IEEE_ADDR_7 (0x2B) |
◆ AT86RF2XX_REG__IRQ_MASK
#define AT86RF2XX_REG__IRQ_MASK (0x0E) |
◆ AT86RF2XX_REG__IRQ_STATUS
#define AT86RF2XX_REG__IRQ_STATUS (0x0F) |
◆ AT86RF2XX_REG__MAN_ID_0
#define AT86RF2XX_REG__MAN_ID_0 (0x1E) |
◆ AT86RF2XX_REG__MAN_ID_1
#define AT86RF2XX_REG__MAN_ID_1 (0x1F) |
◆ AT86RF2XX_REG__PAN_ID_0
#define AT86RF2XX_REG__PAN_ID_0 (0x22) |
◆ AT86RF2XX_REG__PAN_ID_1
#define AT86RF2XX_REG__PAN_ID_1 (0x23) |
◆ AT86RF2XX_REG__PART_NUM
#define AT86RF2XX_REG__PART_NUM (0x1C) |
◆ AT86RF2XX_REG__PHY_CC_CCA
#define AT86RF2XX_REG__PHY_CC_CCA (0x08) |
◆ AT86RF2XX_REG__PHY_ED_LEVEL
#define AT86RF2XX_REG__PHY_ED_LEVEL (0x07) |
◆ AT86RF2XX_REG__PHY_RSSI
#define AT86RF2XX_REG__PHY_RSSI (0x06) |
◆ AT86RF2XX_REG__PHY_TX_PWR
#define AT86RF2XX_REG__PHY_TX_PWR (0x05) |
◆ AT86RF2XX_REG__PLL_CF
#define AT86RF2XX_REG__PLL_CF (0x1A) |
◆ AT86RF2XX_REG__PLL_DCU
#define AT86RF2XX_REG__PLL_DCU (0x1B) |
◆ AT86RF2XX_REG__RX_CTRL
#define AT86RF2XX_REG__RX_CTRL (0x0A) |
◆ AT86RF2XX_REG__RX_SYN
#define AT86RF2XX_REG__RX_SYN (0x15) |
◆ AT86RF2XX_REG__SFD_VALUE
#define AT86RF2XX_REG__SFD_VALUE (0x0B) |
◆ AT86RF2XX_REG__SHORT_ADDR_0
#define AT86RF2XX_REG__SHORT_ADDR_0 (0x20) |
◆ AT86RF2XX_REG__SHORT_ADDR_1
#define AT86RF2XX_REG__SHORT_ADDR_1 (0x21) |
◆ AT86RF2XX_REG__TRX_CTRL_0
#define AT86RF2XX_REG__TRX_CTRL_0 (0x03) |
◆ AT86RF2XX_REG__TRX_CTRL_1
#define AT86RF2XX_REG__TRX_CTRL_1 (0x04) |
◆ AT86RF2XX_REG__TRX_CTRL_2
#define AT86RF2XX_REG__TRX_CTRL_2 (0x0C) |
◆ AT86RF2XX_REG__TRX_STATE
#define AT86RF2XX_REG__TRX_STATE (0x02) |
◆ AT86RF2XX_REG__TRX_STATUS
#define AT86RF2XX_REG__TRX_STATUS (0x01) |
◆ AT86RF2XX_REG__TST_CTRL_DIGI
#define AT86RF2XX_REG__TST_CTRL_DIGI (0x36) |
◆ AT86RF2XX_REG__VERSION_NUM
#define AT86RF2XX_REG__VERSION_NUM (0x1D) |
◆ AT86RF2XX_REG__VREG_CTRL
#define AT86RF2XX_REG__VREG_CTRL (0x10) |
◆ AT86RF2XX_REG__XAH_CTRL_0
#define AT86RF2XX_REG__XAH_CTRL_0 (0x2C) |
◆ AT86RF2XX_REG__XAH_CTRL_1
#define AT86RF2XX_REG__XAH_CTRL_1 (0x17) |
◆ AT86RF2XX_REG__XOSC_CTRL
#define AT86RF2XX_REG__XOSC_CTRL (0x12) |
◆ AT86RF2XX_RX_SYN__RX_OVERRIDE
#define AT86RF2XX_RX_SYN__RX_OVERRIDE (0x70) |
◆ AT86RF2XX_RX_SYN__RX_PDT_DIS
#define AT86RF2XX_RX_SYN__RX_PDT_DIS (0x80) |
◆ AT86RF2XX_RX_SYN__RX_PDT_LEVEL
#define AT86RF2XX_RX_SYN__RX_PDT_LEVEL (0x0F) |
◆ AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX
#define AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16) |
◆ AT86RF2XX_TIMING__RESET
#define AT86RF2XX_TIMING__RESET (100) |
◆ AT86RF2XX_TIMING__RESET_TO_TRX_OFF
#define AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37) |
◆ AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF
#define AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380) |
◆ AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON
#define AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110) |
◆ AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON
#define AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110) |
◆ AT86RF2XX_TIMING__VCC_TO_P_ON
#define AT86RF2XX_TIMING__VCC_TO_P_ON (330) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04) |
◆ AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF
#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00) |
◆ AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL
#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01) |
◆ AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL
#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08) |
◆ AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO
#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00) |
◆ AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM
#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10) |
◆ AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL
#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07) |
◆ AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL
#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08) |
◆ AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO
#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0) |
◆ AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM
#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN
#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE
#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY
#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN
#define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL
#define AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE
#define AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C) |
◆ AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON
#define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM
#define AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK
#define AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE
#define AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE
#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN
#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE
#define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE
#define AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04) |
◆ AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN
#define AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40) |
◆ AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN
#define AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN (0x02) |
◆ AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN
#define AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN (0x10) |
◆ AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN
#define AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN (0x08) |
◆ AT86RF2XX_TRX_RPC_MASK__RX_RPC__SMART_IDLE
#define AT86RF2XX_TRX_RPC_MASK__RX_RPC__SMART_IDLE |
Value: (AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN \
| AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN \
| AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN \
| AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN \
| AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN)
Bits to set to enable smart idle.
Definition at line 541 of file at86rf2xx_registers.h.
◆ AT86RF2XX_TRX_RPC_MASK__RX_RPC_CTRL_MAXPWR
#define AT86RF2XX_TRX_RPC_MASK__RX_RPC_CTRL_MAXPWR (0xC0) |
◆ AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN
#define AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN (0x20) |
◆ AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN
#define AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN (0x04) |
◆ AT86RF2XX_TRX_STATE__FORCE_PLL_ON
#define AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04) |
◆ AT86RF2XX_TRX_STATE__FORCE_TRX_OFF
#define AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03) |
◆ AT86RF2XX_TRX_STATE__NOP
#define AT86RF2XX_TRX_STATE__NOP (0x00) |
◆ AT86RF2XX_TRX_STATE__PLL_ON
#define AT86RF2XX_TRX_STATE__PLL_ON (0x09) |
◆ AT86RF2XX_TRX_STATE__RX_AACK_ON
#define AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16) |
◆ AT86RF2XX_TRX_STATE__RX_ON
#define AT86RF2XX_TRX_STATE__RX_ON (0x06) |
◆ AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE
#define AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60) |
◆ AT86RF2XX_TRX_STATE__TRAC_INVALID
#define AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0) |
◆ AT86RF2XX_TRX_STATE__TRAC_NO_ACK
#define AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0) |
◆ AT86RF2XX_TRX_STATE__TRAC_SUCCESS
#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00) |
◆ AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING
#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20) |
◆ AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK
#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40) |
◆ AT86RF2XX_TRX_STATE__TRX_OFF
#define AT86RF2XX_TRX_STATE__TRX_OFF (0x08) |
◆ AT86RF2XX_TRX_STATE__TX_ARET_ON
#define AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19) |
◆ AT86RF2XX_TRX_STATE__TX_START
#define AT86RF2XX_TRX_STATE__TX_START (0x02) |
◆ AT86RF2XX_TRX_STATE_MASK__TRAC
#define AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0) |
◆ AT86RF2XX_TRX_STATUS__BUSY_RX
#define AT86RF2XX_TRX_STATUS__BUSY_RX (0x01) |
◆ AT86RF2XX_TRX_STATUS__BUSY_RX_AACK
#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11) |
◆ AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK
#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E) |
◆ AT86RF2XX_TRX_STATUS__BUSY_TX
#define AT86RF2XX_TRX_STATUS__BUSY_TX (0x02) |
◆ AT86RF2XX_TRX_STATUS__BUSY_TX_ARET
#define AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12) |
◆ AT86RF2XX_TRX_STATUS__P_ON
#define AT86RF2XX_TRX_STATUS__P_ON (0x00) |
◆ AT86RF2XX_TRX_STATUS__PLL_ON
#define AT86RF2XX_TRX_STATUS__PLL_ON (0x09) |
◆ AT86RF2XX_TRX_STATUS__RX_AACK_ON
#define AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16) |
◆ AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK
#define AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D) |
◆ AT86RF2XX_TRX_STATUS__RX_ON
#define AT86RF2XX_TRX_STATUS__RX_ON (0x06) |
◆ AT86RF2XX_TRX_STATUS__RX_ON_NOCLK
#define AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C) |
◆ AT86RF2XX_TRX_STATUS__SLEEP
#define AT86RF2XX_TRX_STATUS__SLEEP (0x0F) |
◆ AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS
#define AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F) |
◆ AT86RF2XX_TRX_STATUS__TRX_OFF
#define AT86RF2XX_TRX_STATUS__TRX_OFF (0x08) |
◆ AT86RF2XX_TRX_STATUS__TX_ARET_ON
#define AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19) |
◆ AT86RF2XX_TRX_STATUS_MASK__CCA_DONE
#define AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80) |
◆ AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS
#define AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40) |
◆ AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS
#define AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F) |
◆ AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES
#define AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E) |
◆ AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES
#define AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0) |
◆ AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION
#define AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01) |
◆ AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME
#define AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04) |
◆ AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT
#define AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20) |
◆ AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE
#define AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02) |
◆ AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT
#define AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10) |
◆ AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL
#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0) |
◆ AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL
#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0) |
◆ AT86RFA1_PARTNUM
#define AT86RFA1_PARTNUM (0x83) |
◆ AT86RFR2_PARTNUM
#define AT86RFR2_PARTNUM (0x94) |