periph_conf.h

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/*
 * SPDX-FileCopyrightText: 2025 Mesotic SAS
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "periph_cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif

/* targeted system core clock */
#define CLOCK_CORECLOCK     MHZ(120)
/* external oscillator clock */
#define CLOCK_EXT_OSC       MHZ(12)
/* define PLL configuration
 *
 * The values must fulfill this equation:
 * CORECLOCK = (EXT_OCS / PLL_DIV) * (PLL_MUL + 1)
 */
#define CLOCK_PLL_MUL       (9)
#define CLOCK_PLL_DIV       (1)
 
/* number of wait states before flash read and write operations */
#define CLOCK_FWS           (5)         /* 5 is safe for 120 MHz */

#define CLOCK_SCLK_XTAL     (1)

static const timer_conf_t timer_config[] = {
    { .dev = TC0, .id_ch0 = ID_TC0 },
    { .dev = TC1, .id_ch0 = ID_TC3 }
};
 
#define TIMER_0_ISR         isr_tc0
#define TIMER_1_ISR         isr_tc3
 
#define TIMER_NUMOF         ARRAY_SIZE(timer_config)

static const uart_conf_t uart_config[] = {
    {
        .dev    = (Uart *)UART1,
        .rx_pin = GPIO_PIN(PB, 2),
        .tx_pin = GPIO_PIN(PB, 3),
        .mux    = GPIO_MUX_A,
        .pmc_id = ID_UART1,
        .irqn   = UART1_IRQn
    }
};
 
/* define interrupt vectors */
#define UART_0_ISR          isr_uart1
 
#define UART_NUMOF          ARRAY_SIZE(uart_config)
 
#ifdef __cplusplus
}
#endif