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cc2538.h
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1/*
2 * Copyright (C) 2014 Loci Controls Inc.
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef CC2538_H
20#define CC2538_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* ************************************************************************** */
27/* CMSIS DEFINITIONS FOR CC2538 */
28/* ************************************************************************** */
89
94void Reset_Handler(void);
95void NMI_Handler(void);
98void BusFault_Handler(void);
100void SVC_Handler(void);
102void PendSV_Handler(void);
103void SysTick_Handler(void);
110#define __CM3_REV 0x0200
111#define __MPU_PRESENT 1
112#define __NVIC_PRIO_BITS 3
113#define __Vendor_SysTickConfig 0
118#include <core_cm3.h>
121#define IEEE_ADDR_MSWORD ( *(const uint32_t*)0x00280028 )
122#define IEEE_ADDR_LSWORD ( *(const uint32_t*)0x0028002c )
124typedef volatile uint32_t cc2538_reg_t;
130#define FLASH_BASE 0x00200000
131#define SRAM_BASE 0x20000000
132#define PERIPH_BASE 0x40000000
134#define SRAM_BB_BASE 0x22000000
140#define SSI0_CR0 ( *(cc2538_reg_t*)0x40008000 )
141#define SSI0_CR1 ( *(cc2538_reg_t*)0x40008004 )
142#define SSI0_DR ( *(cc2538_reg_t*)0x40008008 )
143#define SSI0_SR ( *(cc2538_reg_t*)0x4000800c )
144#define SSI0_CPSR ( *(cc2538_reg_t*)0x40008010 )
145#define SSI0_IM ( *(cc2538_reg_t*)0x40008014 )
146#define SSI0_RIS ( *(cc2538_reg_t*)0x40008018 )
147#define SSI0_MIS ( *(cc2538_reg_t*)0x4000801c )
148#define SSI0_ICR ( *(cc2538_reg_t*)0x40008020 )
149#define SSI0_DMACTL ( *(cc2538_reg_t*)0x40008024 )
150#define SSI0_CC ( *(cc2538_reg_t*)0x40008fc8 )
151#define SSI1_CR0 ( *(cc2538_reg_t*)0x40009000 )
152#define SSI1_CR1 ( *(cc2538_reg_t*)0x40009004 )
153#define SSI1_DR ( *(cc2538_reg_t*)0x40009008 )
154#define SSI1_SR ( *(cc2538_reg_t*)0x4000900c )
155#define SSI1_CPSR ( *(cc2538_reg_t*)0x40009010 )
156#define SSI1_IM ( *(cc2538_reg_t*)0x40009014 )
157#define SSI1_RIS ( *(cc2538_reg_t*)0x40009018 )
158#define SSI1_MIS ( *(cc2538_reg_t*)0x4000901c )
159#define SSI1_ICR ( *(cc2538_reg_t*)0x40009020 )
160#define SSI1_DMACTL ( *(cc2538_reg_t*)0x40009024 )
161#define SSI1_CC ( *(cc2538_reg_t*)0x40009fc8 )
162#define UART0_DR ( *(cc2538_reg_t*)0x4000c000 )
163#define UART0_ECR ( *(cc2538_reg_t*)0x4000c004 )
164#define UART0_RSR ( *(cc2538_reg_t*)0x4000c004 )
165#define UART0_FR ( *(cc2538_reg_t*)0x4000c018 )
166#define UART0_ILPR ( *(cc2538_reg_t*)0x4000c020 )
167#define UART0_IBRD ( *(cc2538_reg_t*)0x4000c024 )
168#define UART0_FBRD ( *(cc2538_reg_t*)0x4000c028 )
169#define UART0_LCRH ( *(cc2538_reg_t*)0x4000c02c )
170#define UART0_CTL ( *(cc2538_reg_t*)0x4000c030 )
171#define UART0_IFLS ( *(cc2538_reg_t*)0x4000c034 )
172#define UART0_IM ( *(cc2538_reg_t*)0x4000c038 )
173#define UART0_RIS ( *(cc2538_reg_t*)0x4000c03c )
174#define UART0_MIS ( *(cc2538_reg_t*)0x4000c040 )
175#define UART0_ICR ( *(cc2538_reg_t*)0x4000c044 )
176#define UART0_DMACTL ( *(cc2538_reg_t*)0x4000c048 )
177#define UART0_LCTL ( *(cc2538_reg_t*)0x4000c090 )
178#define UART0_LSS ( *(cc2538_reg_t*)0x4000c094 )
179#define UART0_LTIM ( *(cc2538_reg_t*)0x4000c098 )
180#define UART0_NINEBITADDR ( *(cc2538_reg_t*)0x4000c0a4 )
181#define UART0_NINEBITAMASK ( *(cc2538_reg_t*)0x4000c0a8 )
182#define UART0_PP ( *(cc2538_reg_t*)0x4000cfc0 )
183#define UART0_CC ( *(cc2538_reg_t*)0x4000cfc8 )
184#define UART1_DR ( *(cc2538_reg_t*)0x4000d000 )
185#define UART1_ECR ( *(cc2538_reg_t*)0x4000d004 )
186#define UART1_RSR ( *(cc2538_reg_t*)0x4000d004 )
187#define UART1_FR ( *(cc2538_reg_t*)0x4000d018 )
188#define UART1_ILPR ( *(cc2538_reg_t*)0x4000d020 )
189#define UART1_IBRD ( *(cc2538_reg_t*)0x4000d024 )
190#define UART1_FBRD ( *(cc2538_reg_t*)0x4000d028 )
191#define UART1_LCRH ( *(cc2538_reg_t*)0x4000d02c )
192#define UART1_CTL ( *(cc2538_reg_t*)0x4000d030 )
193#define UART1_IFLS ( *(cc2538_reg_t*)0x4000d034 )
194#define UART1_IM ( *(cc2538_reg_t*)0x4000d038 )
195#define UART1_RIS ( *(cc2538_reg_t*)0x4000d03c )
196#define UART1_MIS ( *(cc2538_reg_t*)0x4000d040 )
197#define UART1_ICR ( *(cc2538_reg_t*)0x4000d044 )
198#define UART1_DMACTL ( *(cc2538_reg_t*)0x4000d048 )
199#define UART1_LCTL ( *(cc2538_reg_t*)0x4000d090 )
200#define UART1_LSS ( *(cc2538_reg_t*)0x4000d094 )
201#define UART1_LTIM ( *(cc2538_reg_t*)0x4000d098 )
202#define UART1_NINEBITADDR ( *(cc2538_reg_t*)0x4000d0a4 )
203#define UART1_NINEBITAMASK ( *(cc2538_reg_t*)0x4000d0a8 )
204#define UART1_PP ( *(cc2538_reg_t*)0x4000dfc0 )
205#define UART1_CC ( *(cc2538_reg_t*)0x4000dfc8 )
206#define I2CM_SA ( *(cc2538_reg_t*)0x40020000 )
207#define I2CM_CTRL ( *(cc2538_reg_t*)0x40020004 )
208#define I2CM_STAT ( *(cc2538_reg_t*)0x40020004 )
209#define I2CM_DR ( *(cc2538_reg_t*)0x40020008 )
210#define I2CM_TPR ( *(cc2538_reg_t*)0x4002000c )
211#define I2CM_IMR ( *(cc2538_reg_t*)0x40020010 )
212#define I2CM_RIS ( *(cc2538_reg_t*)0x40020014 )
213#define I2CM_MIS ( *(cc2538_reg_t*)0x40020018 )
214#define I2CM_ICR ( *(cc2538_reg_t*)0x4002001c )
215#define I2CM_CR ( *(cc2538_reg_t*)0x40020020 )
216#define I2CS_OAR ( *(cc2538_reg_t*)0x40020800 )
217#define I2CS_CTRL ( *(cc2538_reg_t*)0x40020804 )
218#define I2CS_STAT ( *(cc2538_reg_t*)0x40020804 )
219#define I2CS_DR ( *(cc2538_reg_t*)0x40020808 )
220#define I2CS_IMR ( *(cc2538_reg_t*)0x4002080c )
221#define I2CS_RIS ( *(cc2538_reg_t*)0x40020810 )
222#define I2CS_MIS ( *(cc2538_reg_t*)0x40020814 )
223#define I2CS_ICR ( *(cc2538_reg_t*)0x40020818 )
224#define GPTIMER0_CFG ( *(cc2538_reg_t*)0x40030000 )
225#define GPTIMER0_TAMR ( *(cc2538_reg_t*)0x40030004 )
226#define GPTIMER0_TBMR ( *(cc2538_reg_t*)0x40030008 )
227#define GPTIMER0_CTL ( *(cc2538_reg_t*)0x4003000c )
228#define GPTIMER0_SYNC ( *(cc2538_reg_t*)0x40030010 )
229#define GPTIMER0_IMR ( *(cc2538_reg_t*)0x40030018 )
230#define GPTIMER0_RIS ( *(cc2538_reg_t*)0x4003001c )
231#define GPTIMER0_MIS ( *(cc2538_reg_t*)0x40030020 )
232#define GPTIMER0_ICR ( *(cc2538_reg_t*)0x40030024 )
233#define GPTIMER0_TAILR ( *(cc2538_reg_t*)0x40030028 )
234#define GPTIMER0_TBILR ( *(cc2538_reg_t*)0x4003002c )
235#define GPTIMER0_TAMATCHR ( *(cc2538_reg_t*)0x40030030 )
236#define GPTIMER0_TBMATCHR ( *(cc2538_reg_t*)0x40030034 )
237#define GPTIMER0_TAPR ( *(cc2538_reg_t*)0x40030038 )
238#define GPTIMER0_TBPR ( *(cc2538_reg_t*)0x4003003c )
239#define GPTIMER0_TAPMR ( *(cc2538_reg_t*)0x40030040 )
240#define GPTIMER0_TBPMR ( *(cc2538_reg_t*)0x40030044 )
241#define GPTIMER0_TAR ( *(cc2538_reg_t*)0x40030048 )
242#define GPTIMER0_TBR ( *(cc2538_reg_t*)0x4003004c )
243#define GPTIMER0_TAV ( *(cc2538_reg_t*)0x40030050 )
244#define GPTIMER0_TBV ( *(cc2538_reg_t*)0x40030054 )
245#define GPTIMER0_TAPS ( *(cc2538_reg_t*)0x4003005c )
246#define GPTIMER0_TBPS ( *(cc2538_reg_t*)0x40030060 )
247#define GPTIMER0_TAPV ( *(cc2538_reg_t*)0x40030064 )
248#define GPTIMER0_TBPV ( *(cc2538_reg_t*)0x40030068 )
249#define GPTIMER0_PP ( *(cc2538_reg_t*)0x40030fc0 )
250#define GPTIMER1_CFG ( *(cc2538_reg_t*)0x40031000 )
251#define GPTIMER1_TAMR ( *(cc2538_reg_t*)0x40031004 )
252#define GPTIMER1_TBMR ( *(cc2538_reg_t*)0x40031008 )
253#define GPTIMER1_CTL ( *(cc2538_reg_t*)0x4003100c )
254#define GPTIMER1_SYNC ( *(cc2538_reg_t*)0x40031010 )
255#define GPTIMER1_IMR ( *(cc2538_reg_t*)0x40031018 )
256#define GPTIMER1_RIS ( *(cc2538_reg_t*)0x4003101c )
257#define GPTIMER1_MIS ( *(cc2538_reg_t*)0x40031020 )
258#define GPTIMER1_ICR ( *(cc2538_reg_t*)0x40031024 )
259#define GPTIMER1_TAILR ( *(cc2538_reg_t*)0x40031028 )
260#define GPTIMER1_TBILR ( *(cc2538_reg_t*)0x4003102c )
261#define GPTIMER1_TAMATCHR ( *(cc2538_reg_t*)0x40031030 )
262#define GPTIMER1_TBMATCHR ( *(cc2538_reg_t*)0x40031034 )
263#define GPTIMER1_TAPR ( *(cc2538_reg_t*)0x40031038 )
264#define GPTIMER1_TBPR ( *(cc2538_reg_t*)0x4003103c )
265#define GPTIMER1_TAPMR ( *(cc2538_reg_t*)0x40031040 )
266#define GPTIMER1_TBPMR ( *(cc2538_reg_t*)0x40031044 )
267#define GPTIMER1_TAR ( *(cc2538_reg_t*)0x40031048 )
268#define GPTIMER1_TBR ( *(cc2538_reg_t*)0x4003104c )
269#define GPTIMER1_TAV ( *(cc2538_reg_t*)0x40031050 )
270#define GPTIMER1_TBV ( *(cc2538_reg_t*)0x40031054 )
271#define GPTIMER1_TAPS ( *(cc2538_reg_t*)0x4003105c )
272#define GPTIMER1_TBPS ( *(cc2538_reg_t*)0x40031060 )
273#define GPTIMER1_TAPV ( *(cc2538_reg_t*)0x40031064 )
274#define GPTIMER1_TBPV ( *(cc2538_reg_t*)0x40031068 )
275#define GPTIMER1_PP ( *(cc2538_reg_t*)0x40031fc0 )
276#define GPTIMER2_CFG ( *(cc2538_reg_t*)0x40032000 )
277#define GPTIMER2_TAMR ( *(cc2538_reg_t*)0x40032004 )
278#define GPTIMER2_TBMR ( *(cc2538_reg_t*)0x40032008 )
279#define GPTIMER2_CTL ( *(cc2538_reg_t*)0x4003200c )
280#define GPTIMER2_SYNC ( *(cc2538_reg_t*)0x40032010 )
281#define GPTIMER2_IMR ( *(cc2538_reg_t*)0x40032018 )
282#define GPTIMER2_RIS ( *(cc2538_reg_t*)0x4003201c )
283#define GPTIMER2_MIS ( *(cc2538_reg_t*)0x40032020 )
284#define GPTIMER2_ICR ( *(cc2538_reg_t*)0x40032024 )
285#define GPTIMER2_TAILR ( *(cc2538_reg_t*)0x40032028 )
286#define GPTIMER2_TBILR ( *(cc2538_reg_t*)0x4003202c )
287#define GPTIMER2_TAMATCHR ( *(cc2538_reg_t*)0x40032030 )
288#define GPTIMER2_TBMATCHR ( *(cc2538_reg_t*)0x40032034 )
289#define GPTIMER2_TAPR ( *(cc2538_reg_t*)0x40032038 )
290#define GPTIMER2_TBPR ( *(cc2538_reg_t*)0x4003203c )
291#define GPTIMER2_TAPMR ( *(cc2538_reg_t*)0x40032040 )
292#define GPTIMER2_TBPMR ( *(cc2538_reg_t*)0x40032044 )
293#define GPTIMER2_TAR ( *(cc2538_reg_t*)0x40032048 )
294#define GPTIMER2_TBR ( *(cc2538_reg_t*)0x4003204c )
295#define GPTIMER2_TAV ( *(cc2538_reg_t*)0x40032050 )
296#define GPTIMER2_TBV ( *(cc2538_reg_t*)0x40032054 )
297#define GPTIMER2_TAPS ( *(cc2538_reg_t*)0x4003205c )
298#define GPTIMER2_TBPS ( *(cc2538_reg_t*)0x40032060 )
299#define GPTIMER2_TAPV ( *(cc2538_reg_t*)0x40032064 )
300#define GPTIMER2_TBPV ( *(cc2538_reg_t*)0x40032068 )
301#define GPTIMER2_PP ( *(cc2538_reg_t*)0x40032fc0 )
302#define GPTIMER3_CFG ( *(cc2538_reg_t*)0x40033000 )
303#define GPTIMER3_TAMR ( *(cc2538_reg_t*)0x40033004 )
304#define GPTIMER3_TBMR ( *(cc2538_reg_t*)0x40033008 )
305#define GPTIMER3_CTL ( *(cc2538_reg_t*)0x4003300c )
306#define GPTIMER3_SYNC ( *(cc2538_reg_t*)0x40033010 )
307#define GPTIMER3_IMR ( *(cc2538_reg_t*)0x40033018 )
308#define GPTIMER3_RIS ( *(cc2538_reg_t*)0x4003301c )
309#define GPTIMER3_MIS ( *(cc2538_reg_t*)0x40033020 )
310#define GPTIMER3_ICR ( *(cc2538_reg_t*)0x40033024 )
311#define GPTIMER3_TAILR ( *(cc2538_reg_t*)0x40033028 )
312#define GPTIMER3_TBILR ( *(cc2538_reg_t*)0x4003302c )
313#define GPTIMER3_TAMATCHR ( *(cc2538_reg_t*)0x40033030 )
314#define GPTIMER3_TBMATCHR ( *(cc2538_reg_t*)0x40033034 )
315#define GPTIMER3_TAPR ( *(cc2538_reg_t*)0x40033038 )
316#define GPTIMER3_TBPR ( *(cc2538_reg_t*)0x4003303c )
317#define GPTIMER3_TAPMR ( *(cc2538_reg_t*)0x40033040 )
318#define GPTIMER3_TBPMR ( *(cc2538_reg_t*)0x40033044 )
319#define GPTIMER3_TAR ( *(cc2538_reg_t*)0x40033048 )
320#define GPTIMER3_TBR ( *(cc2538_reg_t*)0x4003304c )
321#define GPTIMER3_TAV ( *(cc2538_reg_t*)0x40033050 )
322#define GPTIMER3_TBV ( *(cc2538_reg_t*)0x40033054 )
323#define GPTIMER3_TAPS ( *(cc2538_reg_t*)0x4003305c )
324#define GPTIMER3_TBPS ( *(cc2538_reg_t*)0x40033060 )
325#define GPTIMER3_TAPV ( *(cc2538_reg_t*)0x40033064 )
326#define GPTIMER3_TBPV ( *(cc2538_reg_t*)0x40033068 )
327#define GPTIMER3_PP ( *(cc2538_reg_t*)0x40033fc0 )
328#define RFCORE_FFSM_SRCRESMASK0 ( *(cc2538_reg_t*)0x40088580 )
329#define RFCORE_FFSM_SRCRESMASK1 ( *(cc2538_reg_t*)0x40088584 )
330#define RFCORE_FFSM_SRCRESMASK2 ( *(cc2538_reg_t*)0x40088588 )
331#define RFCORE_FFSM_SRCRESINDEX ( *(cc2538_reg_t*)0x4008858c )
332#define RFCORE_FFSM_SRCEXTPENDEN0 ( *(cc2538_reg_t*)0x40088590 )
333#define RFCORE_FFSM_SRCEXTPENDEN1 ( *(cc2538_reg_t*)0x40088594 )
334#define RFCORE_FFSM_SRCEXTPENDEN2 ( *(cc2538_reg_t*)0x40088598 )
335#define RFCORE_FFSM_SRCSHORTPENDEN0 ( *(cc2538_reg_t*)0x4008859c )
336#define RFCORE_FFSM_SRCSHORTPENDEN1 ( *(cc2538_reg_t*)0x400885a0 )
337#define RFCORE_FFSM_SRCSHORTPENDEN2 ( *(cc2538_reg_t*)0x400885a4 )
338#define RFCORE_FFSM_EXT_ADDR0 ( *(cc2538_reg_t*)0x400885a8 )
339#define RFCORE_FFSM_EXT_ADDR1 ( *(cc2538_reg_t*)0x400885ac )
340#define RFCORE_FFSM_EXT_ADDR2 ( *(cc2538_reg_t*)0x400885b0 )
341#define RFCORE_FFSM_EXT_ADDR3 ( *(cc2538_reg_t*)0x400885b4 )
342#define RFCORE_FFSM_EXT_ADDR4 ( *(cc2538_reg_t*)0x400885b8 )
343#define RFCORE_FFSM_EXT_ADDR5 ( *(cc2538_reg_t*)0x400885bc )
344#define RFCORE_FFSM_EXT_ADDR6 ( *(cc2538_reg_t*)0x400885c0 )
345#define RFCORE_FFSM_EXT_ADDR7 ( *(cc2538_reg_t*)0x400885c4 )
346#define RFCORE_FFSM_PAN_ID0 ( *(cc2538_reg_t*)0x400885c8 )
347#define RFCORE_FFSM_PAN_ID1 ( *(cc2538_reg_t*)0x400885cc )
348#define RFCORE_FFSM_SHORT_ADDR0 ( *(cc2538_reg_t*)0x400885d0 )
349#define RFCORE_FFSM_SHORT_ADDR1 ( *(cc2538_reg_t*)0x400885d4 )
350#define RFCORE_XREG_FRMFILT0 ( *(cc2538_reg_t*)0x40088600 )
351#define RFCORE_XREG_FRMFILT1 ( *(cc2538_reg_t*)0x40088604 )
352#define RFCORE_XREG_SRCMATCH ( *(cc2538_reg_t*)0x40088608 )
353#define RFCORE_XREG_SRCSHORTEN0 ( *(cc2538_reg_t*)0x4008860c )
354#define RFCORE_XREG_SRCSHORTEN1 ( *(cc2538_reg_t*)0x40088610 )
355#define RFCORE_XREG_SRCSHORTEN2 ( *(cc2538_reg_t*)0x40088614 )
356#define RFCORE_XREG_SRCEXTEN0 ( *(cc2538_reg_t*)0x40088618 )
357#define RFCORE_XREG_SRCEXTEN1 ( *(cc2538_reg_t*)0x4008861c )
358#define RFCORE_XREG_SRCEXTEN2 ( *(cc2538_reg_t*)0x40088620 )
359#define RFCORE_XREG_FRMCTRL0 ( *(cc2538_reg_t*)0x40088624 )
360#define RFCORE_XREG_FRMCTRL1 ( *(cc2538_reg_t*)0x40088628 )
361#define RFCORE_XREG_RXENABLE ( *(cc2538_reg_t*)0x4008862c )
362#define RFCORE_XREG_RXMASKSET ( *(cc2538_reg_t*)0x40088630 )
363#define RFCORE_XREG_RXMASKCLR ( *(cc2538_reg_t*)0x40088634 )
364#define RFCORE_XREG_FREQTUNE ( *(cc2538_reg_t*)0x40088638 )
365#define RFCORE_XREG_FREQCTRL ( *(cc2538_reg_t*)0x4008863c )
366#define RFCORE_XREG_TXPOWER ( *(cc2538_reg_t*)0x40088640 )
367#define RFCORE_XREG_TXCTRL ( *(cc2538_reg_t*)0x40088644 )
368#define RFCORE_XREG_FSMSTAT0 ( *(cc2538_reg_t*)0x40088648 )
369#define RFCORE_XREG_FSMSTAT1 ( *(cc2538_reg_t*)0x4008864c )
370#define RFCORE_XREG_FIFOPCTRL ( *(cc2538_reg_t*)0x40088650 )
371#define RFCORE_XREG_FSMCTRL ( *(cc2538_reg_t*)0x40088654 )
372#define RFCORE_XREG_CCACTRL0 ( *(cc2538_reg_t*)0x40088658 )
373#define RFCORE_XREG_CCACTRL1 ( *(cc2538_reg_t*)0x4008865c )
374#define RFCORE_XREG_RSSI ( *(cc2538_reg_t*)0x40088660 )
375#define RFCORE_XREG_RSSISTAT ( *(cc2538_reg_t*)0x40088664 )
376#define RFCORE_XREG_RXFIRST ( *(cc2538_reg_t*)0x40088668 )
377#define RFCORE_XREG_RXFIFOCNT ( *(cc2538_reg_t*)0x4008866c )
378#define RFCORE_XREG_TXFIFOCNT ( *(cc2538_reg_t*)0x40088670 )
379#define RFCORE_XREG_RXFIRST_PTR ( *(cc2538_reg_t*)0x40088674 )
380#define RFCORE_XREG_RXLAST_PTR ( *(cc2538_reg_t*)0x40088678 )
381#define RFCORE_XREG_RXP1_PTR ( *(cc2538_reg_t*)0x4008867c )
382#define RFCORE_XREG_TXFIRST_PTR ( *(cc2538_reg_t*)0x40088684 )
383#define RFCORE_XREG_TXLAST_PTR ( *(cc2538_reg_t*)0x40088688 )
384#define RFCORE_XREG_RFIRQM0 ( *(cc2538_reg_t*)0x4008868c )
385#define RFCORE_XREG_RFIRQM1 ( *(cc2538_reg_t*)0x40088690 )
386#define RFCORE_XREG_RFERRM ( *(cc2538_reg_t*)0x40088694 )
387#define RFCORE_XREG_RFRND ( *(cc2538_reg_t*)0x4008869c )
388#define RFCORE_XREG_MDMCTRL0 ( *(cc2538_reg_t*)0x400886a0 )
389#define RFCORE_XREG_MDMCTRL1 ( *(cc2538_reg_t*)0x400886a4 )
390#define RFCORE_XREG_FREQEST ( *(cc2538_reg_t*)0x400886a8 )
391#define RFCORE_XREG_RXCTRL ( *(cc2538_reg_t*)0x400886ac )
392#define RFCORE_XREG_FSCTRL ( *(cc2538_reg_t*)0x400886b0 )
393#define RFCORE_XREG_FSCAL0 ( *(cc2538_reg_t*)0x400886b4 )
394#define RFCORE_XREG_FSCAL1 ( *(cc2538_reg_t*)0x400886b8 )
395#define RFCORE_XREG_FSCAL2 ( *(cc2538_reg_t*)0x400886bc )
396#define RFCORE_XREG_FSCAL3 ( *(cc2538_reg_t*)0x400886c0 )
397#define RFCORE_XREG_AGCCTRL0 ( *(cc2538_reg_t*)0x400886c4 )
398#define RFCORE_XREG_AGCCTRL1 ( *(cc2538_reg_t*)0x400886c8 )
399#define RFCORE_XREG_AGCCTRL2 ( *(cc2538_reg_t*)0x400886cc )
400#define RFCORE_XREG_AGCCTRL3 ( *(cc2538_reg_t*)0x400886d0 )
401#define RFCORE_XREG_ADCTEST0 ( *(cc2538_reg_t*)0x400886d4 )
402#define RFCORE_XREG_ADCTEST1 ( *(cc2538_reg_t*)0x400886d8 )
403#define RFCORE_XREG_ADCTEST2 ( *(cc2538_reg_t*)0x400886dc )
404#define RFCORE_XREG_MDMTEST0 ( *(cc2538_reg_t*)0x400886e0 )
405#define RFCORE_XREG_MDMTEST1 ( *(cc2538_reg_t*)0x400886e4 )
406#define RFCORE_XREG_DACTEST0 ( *(cc2538_reg_t*)0x400886e8 )
407#define RFCORE_XREG_DACTEST1 ( *(cc2538_reg_t*)0x400886ec )
408#define RFCORE_XREG_DACTEST2 ( *(cc2538_reg_t*)0x400886f0 )
409#define RFCORE_XREG_ATEST ( *(cc2538_reg_t*)0x400886f4 )
410#define RFCORE_XREG_PTEST0 ( *(cc2538_reg_t*)0x400886f8 )
411#define RFCORE_XREG_PTEST1 ( *(cc2538_reg_t*)0x400886fc )
412#define RFCORE_XREG_CSPCTRL ( *(cc2538_reg_t*)0x40088780 )
413#define RFCORE_XREG_CSPSTAT ( *(cc2538_reg_t*)0x40088784 )
414#define RFCORE_XREG_CSPX ( *(cc2538_reg_t*)0x40088788 )
415#define RFCORE_XREG_CSPY ( *(cc2538_reg_t*)0x4008878c )
416#define RFCORE_XREG_CSPZ ( *(cc2538_reg_t*)0x40088790 )
417#define RFCORE_XREG_CSPT ( *(cc2538_reg_t*)0x40088794 )
418#define RFCORE_XREG_RFC_OBS_CTRL0 ( *(cc2538_reg_t*)0x400887ac )
419#define RFCORE_XREG_RFC_OBS_CTRL1 ( *(cc2538_reg_t*)0x400887b0 )
420#define RFCORE_XREG_RFC_OBS_CTRL2 ( *(cc2538_reg_t*)0x400887b4 )
421#define RFCORE_XREG_TXFILTCFG ( *(cc2538_reg_t*)0x400887e8 )
422#define RFCORE_SFR_MTCSPCFG ( *(cc2538_reg_t*)0x40088800 )
423#define RFCORE_SFR_MTCTRL ( *(cc2538_reg_t*)0x40088804 )
424#define RFCORE_SFR_MTIRQM ( *(cc2538_reg_t*)0x40088808 )
425#define RFCORE_SFR_MTIRQF ( *(cc2538_reg_t*)0x4008880c )
426#define RFCORE_SFR_MTMSEL ( *(cc2538_reg_t*)0x40088810 )
427#define RFCORE_SFR_MTM0 ( *(cc2538_reg_t*)0x40088814 )
428#define RFCORE_SFR_MTM1 ( *(cc2538_reg_t*)0x40088818 )
429#define RFCORE_SFR_MTMOVF2 ( *(cc2538_reg_t*)0x4008881c )
430#define RFCORE_SFR_MTMOVF1 ( *(cc2538_reg_t*)0x40088820 )
431#define RFCORE_SFR_MTMOVF0 ( *(cc2538_reg_t*)0x40088824 )
432#define RFCORE_SFR_RFDATA ( *(cc2538_reg_t*)0x40088828 )
433#define RFCORE_SFR_RFERRF ( *(cc2538_reg_t*)0x4008882c )
434#define RFCORE_SFR_RFIRQF1 ( *(cc2538_reg_t*)0x40088830 )
435#define RFCORE_SFR_RFIRQF0 ( *(cc2538_reg_t*)0x40088834 )
436#define RFCORE_SFR_RFST ( *(cc2538_reg_t*)0x40088838 )
437#define USB_ADDR ( *(cc2538_reg_t*)0x40089000 )
438#define USB_POW ( *(cc2538_reg_t*)0x40089004 )
439#define USB_IIF ( *(cc2538_reg_t*)0x40089008 )
440#define USB_OIF ( *(cc2538_reg_t*)0x40089010 )
441#define USB_CIF ( *(cc2538_reg_t*)0x40089018 )
442#define USB_IIE ( *(cc2538_reg_t*)0x4008901c )
443#define USB_OIE ( *(cc2538_reg_t*)0x40089024 )
444#define USB_CIE ( *(cc2538_reg_t*)0x4008902c )
445#define USB_FRML ( *(cc2538_reg_t*)0x40089030 )
446#define USB_FRMH ( *(cc2538_reg_t*)0x40089034 )
447#define USB_INDEX ( *(cc2538_reg_t*)0x40089038 )
448#define USB_CTRL ( *(cc2538_reg_t*)0x4008903c )
449#define USB_MAXI ( *(cc2538_reg_t*)0x40089040 )
450#define USB_CS0_CSIL ( *(cc2538_reg_t*)0x40089044 )
451#define USB_CSIH ( *(cc2538_reg_t*)0x40089048 )
452#define USB_MAXO ( *(cc2538_reg_t*)0x4008904c )
453#define USB_CSOL ( *(cc2538_reg_t*)0x40089050 )
454#define USB_CSOH ( *(cc2538_reg_t*)0x40089054 )
455#define USB_CNT0_CNTL ( *(cc2538_reg_t*)0x40089058 )
456#define USB_CNTH ( *(cc2538_reg_t*)0x4008905c )
457#define USB_F0 ( *(cc2538_reg_t*)0x40089080 )
458#define USB_F1 ( *(cc2538_reg_t*)0x40089088 )
459#define USB_F2 ( *(cc2538_reg_t*)0x40089090 )
460#define USB_F3 ( *(cc2538_reg_t*)0x40089098 )
461#define USB_F4 ( *(cc2538_reg_t*)0x400890a0 )
462#define USB_F5 ( *(cc2538_reg_t*)0x400890a8 )
463#define AES_DMAC_CH0_CTRL ( *(cc2538_reg_t*)0x4008b000 )
464#define AES_DMAC_CH0_EXTADDR ( *(cc2538_reg_t*)0x4008b004 )
465#define AES_DMAC_CH0_DMALENGTH ( *(cc2538_reg_t*)0x4008b00c )
466#define AES_DMAC_STATUS ( *(cc2538_reg_t*)0x4008b018 )
467#define AES_DMAC_SWRES ( *(cc2538_reg_t*)0x4008b01c )
468#define AES_DMAC_CH1_CTRL ( *(cc2538_reg_t*)0x4008b020 )
469#define AES_DMAC_CH1_EXTADDR ( *(cc2538_reg_t*)0x4008b024 )
470#define AES_DMAC_CH1_DMALENGTH ( *(cc2538_reg_t*)0x4008b02c )
471#define AES_DMAC_MST_RUNPARAMS ( *(cc2538_reg_t*)0x4008b078 )
472#define AES_DMAC_PERSR ( *(cc2538_reg_t*)0x4008b07c )
473#define AES_DMAC_OPTIONS ( *(cc2538_reg_t*)0x4008b0f8 )
474#define AES_DMAC_VERSION ( *(cc2538_reg_t*)0x4008b0fc )
475#define AES_KEY_STORE_WRITE_AREA ( *(cc2538_reg_t*)0x4008b400 )
476#define AES_KEY_STORE_WRITTEN_AREA ( *(cc2538_reg_t*)0x4008b404 )
477#define AES_KEY_STORE_SIZE ( *(cc2538_reg_t*)0x4008b408 )
478#define AES_KEY_STORE_READ_AREA ( *(cc2538_reg_t*)0x4008b40c )
479#define AES_AES_KEY2_0 ( *(cc2538_reg_t*)0x4008b500 )
480#define AES_AES_KEY2_1 ( *(cc2538_reg_t*)0x4008b504 )
481#define AES_AES_KEY2_2 ( *(cc2538_reg_t*)0x4008b508 )
482#define AES_AES_KEY2_3 ( *(cc2538_reg_t*)0x4008b50c )
483#define AES_AES_KEY3_0 ( *(cc2538_reg_t*)0x4008b510 )
484#define AES_AES_KEY3_1 ( *(cc2538_reg_t*)0x4008b514 )
485#define AES_AES_KEY3_2 ( *(cc2538_reg_t*)0x4008b518 )
486#define AES_AES_KEY3_3 ( *(cc2538_reg_t*)0x4008b51c )
487#define AES_AES_IV_0 ( *(cc2538_reg_t*)0x4008b540 )
488#define AES_AES_IV_1 ( *(cc2538_reg_t*)0x4008b544 )
489#define AES_AES_IV_2 ( *(cc2538_reg_t*)0x4008b548 )
490#define AES_AES_IV_3 ( *(cc2538_reg_t*)0x4008b54c )
491#define AES_AES_CTRL ( *(cc2538_reg_t*)0x4008b550 )
492#define AES_AES_C_LENGTH_0 ( *(cc2538_reg_t*)0x4008b554 )
493#define AES_AES_C_LENGTH_1 ( *(cc2538_reg_t*)0x4008b558 )
494#define AES_AES_AUTH_LENGTH ( *(cc2538_reg_t*)0x4008b55c )
495#define AES_AES_DATA_IN_OUT_0 ( *(cc2538_reg_t*)0x4008b560 )
496#define AES_AES_DATA_IN_OUT_1 ( *(cc2538_reg_t*)0x4008b564 )
497#define AES_AES_DATA_IN_OUT_2 ( *(cc2538_reg_t*)0x4008b568 )
498#define AES_AES_DATA_IN_OUT_3 ( *(cc2538_reg_t*)0x4008b56c )
499#define AES_AES_TAG_OUT_0 ( *(cc2538_reg_t*)0x4008b570 )
500#define AES_AES_TAG_OUT_1 ( *(cc2538_reg_t*)0x4008b574 )
501#define AES_AES_TAG_OUT_2 ( *(cc2538_reg_t*)0x4008b578 )
502#define AES_AES_TAG_OUT_3 ( *(cc2538_reg_t*)0x4008b57c )
503#define AES_HASH_DATA_IN_0 ( *(cc2538_reg_t*)0x4008b600 )
504#define AES_HASH_DATA_IN_1 ( *(cc2538_reg_t*)0x4008b604 )
505#define AES_HASH_DATA_IN_2 ( *(cc2538_reg_t*)0x4008b608 )
506#define AES_HASH_DATA_IN_3 ( *(cc2538_reg_t*)0x4008b60c )
507#define AES_HASH_DATA_IN_4 ( *(cc2538_reg_t*)0x4008b610 )
508#define AES_HASH_DATA_IN_5 ( *(cc2538_reg_t*)0x4008b614 )
509#define AES_HASH_DATA_IN_6 ( *(cc2538_reg_t*)0x4008b618 )
510#define AES_HASH_DATA_IN_7 ( *(cc2538_reg_t*)0x4008b61c )
511#define AES_HASH_DATA_IN_8 ( *(cc2538_reg_t*)0x4008b620 )
512#define AES_HASH_DATA_IN_9 ( *(cc2538_reg_t*)0x4008b624 )
513#define AES_HASH_DATA_IN_10 ( *(cc2538_reg_t*)0x4008b628 )
514#define AES_HASH_DATA_IN_11 ( *(cc2538_reg_t*)0x4008b62c )
515#define AES_HASH_DATA_IN_12 ( *(cc2538_reg_t*)0x4008b630 )
516#define AES_HASH_DATA_IN_13 ( *(cc2538_reg_t*)0x4008b634 )
517#define AES_HASH_DATA_IN_14 ( *(cc2538_reg_t*)0x4008b638 )
518#define AES_HASH_DATA_IN_15 ( *(cc2538_reg_t*)0x4008b63c )
519#define AES_HASH_IO_BUF_CTRL ( *(cc2538_reg_t*)0x4008b640 )
520#define AES_HASH_MODE_IN ( *(cc2538_reg_t*)0x4008b644 )
521#define AES_HASH_LENGTH_IN_L ( *(cc2538_reg_t*)0x4008b648 )
522#define AES_HASH_LENGTH_IN_H ( *(cc2538_reg_t*)0x4008b64c )
523#define AES_HASH_DIGEST_A ( *(cc2538_reg_t*)0x4008b650 )
524#define AES_HASH_DIGEST_B ( *(cc2538_reg_t*)0x4008b654 )
525#define AES_HASH_DIGEST_C ( *(cc2538_reg_t*)0x4008b658 )
526#define AES_HASH_DIGEST_D ( *(cc2538_reg_t*)0x4008b65c )
527#define AES_HASH_DIGEST_E ( *(cc2538_reg_t*)0x4008b660 )
528#define AES_HASH_DIGEST_F ( *(cc2538_reg_t*)0x4008b664 )
529#define AES_HASH_DIGEST_G ( *(cc2538_reg_t*)0x4008b668 )
530#define AES_HASH_DIGEST_H ( *(cc2538_reg_t*)0x4008b66c )
531#define AES_CTRL_ALG_SEL ( *(cc2538_reg_t*)0x4008b700 )
532#define AES_CTRL_PROT_EN ( *(cc2538_reg_t*)0x4008b704 )
533#define AES_CTRL_SW_RESET ( *(cc2538_reg_t*)0x4008b740 )
534#define AES_CTRL_INT_CFG ( *(cc2538_reg_t*)0x4008b780 )
535#define AES_CTRL_INT_EN ( *(cc2538_reg_t*)0x4008b784 )
536#define AES_CTRL_INT_CLR ( *(cc2538_reg_t*)0x4008b788 )
537#define AES_CTRL_INT_SET ( *(cc2538_reg_t*)0x4008b78c )
538#define AES_CTRL_INT_STAT ( *(cc2538_reg_t*)0x4008b790 )
539#define AES_CTRL_OPTIONS ( *(cc2538_reg_t*)0x4008b7f8 )
540#define AES_CTRL_VERSION ( *(cc2538_reg_t*)0x4008b7fc )
541#define SYS_CTRL_CLOCK_CTRL ( *(cc2538_reg_t*)0x400d2000 )
542#define SYS_CTRL_CLOCK_STA ( *(cc2538_reg_t*)0x400d2004 )
543#define SYS_CTRL_RCGCGPT ( *(cc2538_reg_t*)0x400d2008 )
544#define SYS_CTRL_SCGCGPT ( *(cc2538_reg_t*)0x400d200c )
545#define SYS_CTRL_DCGCGPT ( *(cc2538_reg_t*)0x400d2010 )
546#define SYS_CTRL_SRGPT ( *(cc2538_reg_t*)0x400d2014 )
547#define SYS_CTRL_RCGCSSI ( *(cc2538_reg_t*)0x400d2018 )
548#define SYS_CTRL_SCGCSSI ( *(cc2538_reg_t*)0x400d201c )
549#define SYS_CTRL_DCGCSSI ( *(cc2538_reg_t*)0x400d2020 )
550#define SYS_CTRL_SRSSI ( *(cc2538_reg_t*)0x400d2024 )
551#define SYS_CTRL_RCGCUART ( *(cc2538_reg_t*)0x400d2028 )
552#define SYS_CTRL_SCGCUART ( *(cc2538_reg_t*)0x400d202c )
553#define SYS_CTRL_DCGCUART ( *(cc2538_reg_t*)0x400d2030 )
554#define SYS_CTRL_SRUART ( *(cc2538_reg_t*)0x400d2034 )
555#define SYS_CTRL_RCGCI2C ( *(cc2538_reg_t*)0x400d2038 )
556#define SYS_CTRL_SCGCI2C ( *(cc2538_reg_t*)0x400d203c )
557#define SYS_CTRL_DCGCI2C ( *(cc2538_reg_t*)0x400d2040 )
558#define SYS_CTRL_SRI2C ( *(cc2538_reg_t*)0x400d2044 )
559#define SYS_CTRL_RCGCSEC ( *(cc2538_reg_t*)0x400d2048 )
560#define SYS_CTRL_SCGCSEC ( *(cc2538_reg_t*)0x400d204c )
561#define SYS_CTRL_DCGCSEC ( *(cc2538_reg_t*)0x400d2050 )
562#define SYS_CTRL_SRSEC ( *(cc2538_reg_t*)0x400d2054 )
563#define SYS_CTRL_PMCTL ( *(cc2538_reg_t*)0x400d2058 )
564#define SYS_CTRL_SRCRC ( *(cc2538_reg_t*)0x400d205c )
565#define SYS_CTRL_PWRDBG ( *(cc2538_reg_t*)0x400d2074 )
566#define SYS_CTRL_CLD ( *(cc2538_reg_t*)0x400d2080 )
567#define SYS_CTRL_IWE ( *(cc2538_reg_t*)0x400d2094 )
568#define SYS_CTRL_I_MAP ( *(cc2538_reg_t*)0x400d2098 )
569#define SYS_CTRL_RCGCRFC ( *(cc2538_reg_t*)0x400d20a8 )
570#define SYS_CTRL_SCGCRFC ( *(cc2538_reg_t*)0x400d20ac )
571#define SYS_CTRL_DCGCRFC ( *(cc2538_reg_t*)0x400d20b0 )
572#define SYS_CTRL_EMUOVR ( *(cc2538_reg_t*)0x400d20b4 )
573#define FLASH_CTRL_FCTL ( *(cc2538_reg_t*)0x400d3008 )
574#define FLASH_CTRL_FADDR ( *(cc2538_reg_t*)0x400d300c )
575#define FLASH_CTRL_FWDATA ( *(cc2538_reg_t*)0x400d3010 )
576#define FLASH_CTRL_DIECFG0 ( *(cc2538_reg_t*)0x400d3014 )
577#define FLASH_CTRL_DIECFG1 ( *(cc2538_reg_t*)0x400d3018 )
578#define FLASH_CTRL_DIECFG2 ( *(cc2538_reg_t*)0x400d301c )
579#define IOC_PA0_SEL ( *(cc2538_reg_t*)0x400d4000 )
580#define IOC_PA1_SEL ( *(cc2538_reg_t*)0x400d4004 )
581#define IOC_PA2_SEL ( *(cc2538_reg_t*)0x400d4008 )
582#define IOC_PA3_SEL ( *(cc2538_reg_t*)0x400d400c )
583#define IOC_PA4_SEL ( *(cc2538_reg_t*)0x400d4010 )
584#define IOC_PA5_SEL ( *(cc2538_reg_t*)0x400d4014 )
585#define IOC_PA6_SEL ( *(cc2538_reg_t*)0x400d4018 )
586#define IOC_PA7_SEL ( *(cc2538_reg_t*)0x400d401c )
587#define IOC_PB0_SEL ( *(cc2538_reg_t*)0x400d4020 )
588#define IOC_PB1_SEL ( *(cc2538_reg_t*)0x400d4024 )
589#define IOC_PB2_SEL ( *(cc2538_reg_t*)0x400d4028 )
590#define IOC_PB3_SEL ( *(cc2538_reg_t*)0x400d402c )
591#define IOC_PB4_SEL ( *(cc2538_reg_t*)0x400d4030 )
592#define IOC_PB5_SEL ( *(cc2538_reg_t*)0x400d4034 )
593#define IOC_PB6_SEL ( *(cc2538_reg_t*)0x400d4038 )
594#define IOC_PB7_SEL ( *(cc2538_reg_t*)0x400d403c )
595#define IOC_PC0_SEL ( *(cc2538_reg_t*)0x400d4040 )
596#define IOC_PC1_SEL ( *(cc2538_reg_t*)0x400d4044 )
597#define IOC_PC2_SEL ( *(cc2538_reg_t*)0x400d4048 )
598#define IOC_PC3_SEL ( *(cc2538_reg_t*)0x400d404c )
599#define IOC_PC4_SEL ( *(cc2538_reg_t*)0x400d4050 )
600#define IOC_PC5_SEL ( *(cc2538_reg_t*)0x400d4054 )
601#define IOC_PC6_SEL ( *(cc2538_reg_t*)0x400d4058 )
602#define IOC_PC7_SEL ( *(cc2538_reg_t*)0x400d405c )
603#define IOC_PD0_SEL ( *(cc2538_reg_t*)0x400d4060 )
604#define IOC_PD1_SEL ( *(cc2538_reg_t*)0x400d4064 )
605#define IOC_PD2_SEL ( *(cc2538_reg_t*)0x400d4068 )
606#define IOC_PD3_SEL ( *(cc2538_reg_t*)0x400d406c )
607#define IOC_PD4_SEL ( *(cc2538_reg_t*)0x400d4070 )
608#define IOC_PD5_SEL ( *(cc2538_reg_t*)0x400d4074 )
609#define IOC_PD6_SEL ( *(cc2538_reg_t*)0x400d4078 )
610#define IOC_PD7_SEL ( *(cc2538_reg_t*)0x400d407c )
611#define IOC_PA0_OVER ( *(cc2538_reg_t*)0x400d4080 )
612#define IOC_PA1_OVER ( *(cc2538_reg_t*)0x400d4084 )
613#define IOC_PA2_OVER ( *(cc2538_reg_t*)0x400d4088 )
614#define IOC_PA3_OVER ( *(cc2538_reg_t*)0x400d408c )
615#define IOC_PA4_OVER ( *(cc2538_reg_t*)0x400d4090 )
616#define IOC_PA5_OVER ( *(cc2538_reg_t*)0x400d4094 )
617#define IOC_PA6_OVER ( *(cc2538_reg_t*)0x400d4098 )
618#define IOC_PA7_OVER ( *(cc2538_reg_t*)0x400d409c )
619#define IOC_PB0_OVER ( *(cc2538_reg_t*)0x400d40a0 )
620#define IOC_PB1_OVER ( *(cc2538_reg_t*)0x400d40a4 )
621#define IOC_PB2_OVER ( *(cc2538_reg_t*)0x400d40a8 )
622#define IOC_PB3_OVER ( *(cc2538_reg_t*)0x400d40ac )
623#define IOC_PB4_OVER ( *(cc2538_reg_t*)0x400d40b0 )
624#define IOC_PB5_OVER ( *(cc2538_reg_t*)0x400d40b4 )
625#define IOC_PB6_OVER ( *(cc2538_reg_t*)0x400d40b8 )
626#define IOC_PB7_OVER ( *(cc2538_reg_t*)0x400d40bc )
627#define IOC_PC0_OVER ( *(cc2538_reg_t*)0x400d40c0 )
628#define IOC_PC1_OVER ( *(cc2538_reg_t*)0x400d40c4 )
629#define IOC_PC2_OVER ( *(cc2538_reg_t*)0x400d40c8 )
630#define IOC_PC3_OVER ( *(cc2538_reg_t*)0x400d40cc )
631#define IOC_PC4_OVER ( *(cc2538_reg_t*)0x400d40d0 )
632#define IOC_PC5_OVER ( *(cc2538_reg_t*)0x400d40d4 )
633#define IOC_PC6_OVER ( *(cc2538_reg_t*)0x400d40d8 )
634#define IOC_PC7_OVER ( *(cc2538_reg_t*)0x400d40dc )
635#define IOC_PD0_OVER ( *(cc2538_reg_t*)0x400d40e0 )
636#define IOC_PD1_OVER ( *(cc2538_reg_t*)0x400d40e4 )
637#define IOC_PD2_OVER ( *(cc2538_reg_t*)0x400d40e8 )
638#define IOC_PD3_OVER ( *(cc2538_reg_t*)0x400d40ec )
639#define IOC_PD4_OVER ( *(cc2538_reg_t*)0x400d40f0 )
640#define IOC_PD5_OVER ( *(cc2538_reg_t*)0x400d40f4 )
641#define IOC_PD6_OVER ( *(cc2538_reg_t*)0x400d40f8 )
642#define IOC_PD7_OVER ( *(cc2538_reg_t*)0x400d40fc )
643#define IOC_UARTRXD_UART0 ( *(cc2538_reg_t*)0x400d4100 )
644#define IOC_UARTCTS_UART1 ( *(cc2538_reg_t*)0x400d4104 )
645#define IOC_UARTRXD_UART1 ( *(cc2538_reg_t*)0x400d4108 )
646#define IOC_CLK_SSI_SSI0 ( *(cc2538_reg_t*)0x400d410c )
647#define IOC_SSIRXD_SSI0 ( *(cc2538_reg_t*)0x400d4110 )
648#define IOC_SSIFSSIN_SSI0 ( *(cc2538_reg_t*)0x400d4114 )
649#define IOC_CLK_SSIIN_SSI0 ( *(cc2538_reg_t*)0x400d4118 )
650#define IOC_CLK_SSI_SSI1 ( *(cc2538_reg_t*)0x400d411c )
651#define IOC_SSIRXD_SSI1 ( *(cc2538_reg_t*)0x400d4120 )
652#define IOC_SSIFSSIN_SSI1 ( *(cc2538_reg_t*)0x400d4124 )
653#define IOC_CLK_SSIIN_SSI1 ( *(cc2538_reg_t*)0x400d4128 )
654#define IOC_I2CMSSDA ( *(cc2538_reg_t*)0x400d412c )
655#define IOC_I2CMSSCL ( *(cc2538_reg_t*)0x400d4130 )
656#define IOC_GPT0OCP1 ( *(cc2538_reg_t*)0x400d4134 )
657#define IOC_GPT0OCP2 ( *(cc2538_reg_t*)0x400d4138 )
658#define IOC_GPT1OCP1 ( *(cc2538_reg_t*)0x400d413c )
659#define IOC_GPT1OCP2 ( *(cc2538_reg_t*)0x400d4140 )
660#define IOC_GPT2OCP1 ( *(cc2538_reg_t*)0x400d4144 )
661#define IOC_GPT2OCP2 ( *(cc2538_reg_t*)0x400d4148 )
662#define IOC_GPT3OCP1 ( *(cc2538_reg_t*)0x400d414c )
663#define IOC_GPT3OCP2 ( *(cc2538_reg_t*)0x400d4150 )
664#define SMWDTHROSC_WDCTL ( *(cc2538_reg_t*)0x400d5000 )
665#define SMWDTHROSC_ST0 ( *(cc2538_reg_t*)0x400d5040 )
666#define SMWDTHROSC_ST1 ( *(cc2538_reg_t*)0x400d5044 )
667#define SMWDTHROSC_ST2 ( *(cc2538_reg_t*)0x400d5048 )
668#define SMWDTHROSC_ST3 ( *(cc2538_reg_t*)0x400d504c )
669#define SMWDTHROSC_STLOAD ( *(cc2538_reg_t*)0x400d5050 )
670#define SMWDTHROSC_STCC ( *(cc2538_reg_t*)0x400d5054 )
671#define SMWDTHROSC_STCS ( *(cc2538_reg_t*)0x400d5058 )
672#define SMWDTHROSC_STCV0 ( *(cc2538_reg_t*)0x400d505c )
673#define SMWDTHROSC_STCV1 ( *(cc2538_reg_t*)0x400d5060 )
674#define SMWDTHROSC_STCV2 ( *(cc2538_reg_t*)0x400d5064 )
675#define SMWDTHROSC_STCV3 ( *(cc2538_reg_t*)0x400d5068 )
676#define ANA_REGS_IVCTRL ( *(cc2538_reg_t*)0x400d6004 )
677#define GPIO_A_DATA ( *(cc2538_reg_t*)0x400d9000 )
678#define GPIO_A_DIR ( *(cc2538_reg_t*)0x400d9400 )
679#define GPIO_A_IS ( *(cc2538_reg_t*)0x400d9404 )
680#define GPIO_A_IBE ( *(cc2538_reg_t*)0x400d9408 )
681#define GPIO_A_IEV ( *(cc2538_reg_t*)0x400d940c )
682#define GPIO_A_IE ( *(cc2538_reg_t*)0x400d9410 )
683#define GPIO_A_RIS ( *(cc2538_reg_t*)0x400d9414 )
684#define GPIO_A_MIS ( *(cc2538_reg_t*)0x400d9418 )
685#define GPIO_A_IC ( *(cc2538_reg_t*)0x400d941c )
686#define GPIO_A_AFSEL ( *(cc2538_reg_t*)0x400d9420 )
687#define GPIO_A_GPIOLOCK ( *(cc2538_reg_t*)0x400d9520 )
688#define GPIO_A_GPIOCR ( *(cc2538_reg_t*)0x400d9524 )
689#define GPIO_A_PMUX ( *(cc2538_reg_t*)0x400d9700 )
690#define GPIO_A_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400d9704 )
691#define GPIO_A_PI_IEN ( *(cc2538_reg_t*)0x400d9710 )
692#define GPIO_A_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400d9718 )
693#define GPIO_A_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400d971c )
694#define GPIO_A_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400d9720 )
695#define GPIO_B_DATA ( *(cc2538_reg_t*)0x400da000 )
696#define GPIO_B_DIR ( *(cc2538_reg_t*)0x400da400 )
697#define GPIO_B_IS ( *(cc2538_reg_t*)0x400da404 )
698#define GPIO_B_IBE ( *(cc2538_reg_t*)0x400da408 )
699#define GPIO_B_IEV ( *(cc2538_reg_t*)0x400da40c )
700#define GPIO_B_IE ( *(cc2538_reg_t*)0x400da410 )
701#define GPIO_B_RIS ( *(cc2538_reg_t*)0x400da414 )
702#define GPIO_B_MIS ( *(cc2538_reg_t*)0x400da418 )
703#define GPIO_B_IC ( *(cc2538_reg_t*)0x400da41c )
704#define GPIO_B_AFSEL ( *(cc2538_reg_t*)0x400da420 )
705#define GPIO_B_GPIOLOCK ( *(cc2538_reg_t*)0x400da520 )
706#define GPIO_B_GPIOCR ( *(cc2538_reg_t*)0x400da524 )
707#define GPIO_B_PMUX ( *(cc2538_reg_t*)0x400da700 )
708#define GPIO_B_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400da704 )
709#define GPIO_B_PI_IEN ( *(cc2538_reg_t*)0x400da710 )
710#define GPIO_B_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400da718 )
711#define GPIO_B_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400da71c )
712#define GPIO_B_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400da720 )
713#define GPIO_C_DATA ( *(cc2538_reg_t*)0x400db000 )
714#define GPIO_C_DIR ( *(cc2538_reg_t*)0x400db400 )
715#define GPIO_C_IS ( *(cc2538_reg_t*)0x400db404 )
716#define GPIO_C_IBE ( *(cc2538_reg_t*)0x400db408 )
717#define GPIO_C_IEV ( *(cc2538_reg_t*)0x400db40c )
718#define GPIO_C_IE ( *(cc2538_reg_t*)0x400db410 )
719#define GPIO_C_RIS ( *(cc2538_reg_t*)0x400db414 )
720#define GPIO_C_MIS ( *(cc2538_reg_t*)0x400db418 )
721#define GPIO_C_IC ( *(cc2538_reg_t*)0x400db41c )
722#define GPIO_C_AFSEL ( *(cc2538_reg_t*)0x400db420 )
723#define GPIO_C_GPIOLOCK ( *(cc2538_reg_t*)0x400db520 )
724#define GPIO_C_GPIOCR ( *(cc2538_reg_t*)0x400db524 )
725#define GPIO_C_PMUX ( *(cc2538_reg_t*)0x400db700 )
726#define GPIO_C_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400db704 )
727#define GPIO_C_PI_IEN ( *(cc2538_reg_t*)0x400db710 )
728#define GPIO_C_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400db718 )
729#define GPIO_C_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400db71c )
730#define GPIO_C_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400db720 )
731#define GPIO_D_DATA ( *(cc2538_reg_t*)0x400dc000 )
732#define GPIO_D_DIR ( *(cc2538_reg_t*)0x400dc400 )
733#define GPIO_D_IS ( *(cc2538_reg_t*)0x400dc404 )
734#define GPIO_D_IBE ( *(cc2538_reg_t*)0x400dc408 )
735#define GPIO_D_IEV ( *(cc2538_reg_t*)0x400dc40c )
736#define GPIO_D_IE ( *(cc2538_reg_t*)0x400dc410 )
737#define GPIO_D_RIS ( *(cc2538_reg_t*)0x400dc414 )
738#define GPIO_D_MIS ( *(cc2538_reg_t*)0x400dc418 )
739#define GPIO_D_IC ( *(cc2538_reg_t*)0x400dc41c )
740#define GPIO_D_AFSEL ( *(cc2538_reg_t*)0x400dc420 )
741#define GPIO_D_GPIOLOCK ( *(cc2538_reg_t*)0x400dc520 )
742#define GPIO_D_GPIOCR ( *(cc2538_reg_t*)0x400dc524 )
743#define GPIO_D_PMUX ( *(cc2538_reg_t*)0x400dc700 )
744#define GPIO_D_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400dc704 )
745#define GPIO_D_PI_IEN ( *(cc2538_reg_t*)0x400dc710 )
746#define GPIO_D_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400dc718 )
747#define GPIO_D_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400dc71c )
748#define GPIO_D_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400dc720 )
749#define UDMA_STAT ( *(cc2538_reg_t*)0x400ff000 )
750#define UDMA_CFG ( *(cc2538_reg_t*)0x400ff004 )
751#define UDMA_CTLBASE ( *(cc2538_reg_t*)0x400ff008 )
752#define UDMA_ALTBASE ( *(cc2538_reg_t*)0x400ff00c )
753#define UDMA_WAITSTAT ( *(cc2538_reg_t*)0x400ff010 )
754#define UDMA_SWREQ ( *(cc2538_reg_t*)0x400ff014 )
755#define UDMA_USEBURSTSET ( *(cc2538_reg_t*)0x400ff018 )
756#define UDMA_USEBURSTCLR ( *(cc2538_reg_t*)0x400ff01c )
757#define UDMA_REQMASKSET ( *(cc2538_reg_t*)0x400ff020 )
758#define UDMA_REQMASKCLR ( *(cc2538_reg_t*)0x400ff024 )
759#define UDMA_ENASET ( *(cc2538_reg_t*)0x400ff028 )
760#define UDMA_ENACLR ( *(cc2538_reg_t*)0x400ff02c )
761#define UDMA_ALTSET ( *(cc2538_reg_t*)0x400ff030 )
762#define UDMA_ALTCLR ( *(cc2538_reg_t*)0x400ff034 )
763#define UDMA_PRIOSET ( *(cc2538_reg_t*)0x400ff038 )
764#define UDMA_PRIOCLR ( *(cc2538_reg_t*)0x400ff03c )
765#define UDMA_ERRCLR ( *(cc2538_reg_t*)0x400ff04c )
766#define UDMA_CHASGN ( *(cc2538_reg_t*)0x400ff500 )
767#define UDMA_CHIS ( *(cc2538_reg_t*)0x400ff504 )
768#define UDMA_CHMAP0 ( *(cc2538_reg_t*)0x400ff510 )
769#define UDMA_CHMAP1 ( *(cc2538_reg_t*)0x400ff514 )
770#define UDMA_CHMAP2 ( *(cc2538_reg_t*)0x400ff518 )
771#define UDMA_CHMAP3 ( *(cc2538_reg_t*)0x400ff51c )
772#define PKA_APTR ( *(cc2538_reg_t*)0x44004000 )
773#define PKA_BPTR ( *(cc2538_reg_t*)0x44004004 )
774#define PKA_CPTR ( *(cc2538_reg_t*)0x44004008 )
775#define PKA_DPTR ( *(cc2538_reg_t*)0x4400400c )
776#define PKA_ALENGTH ( *(cc2538_reg_t*)0x44004010 )
777#define PKA_BLENGTH ( *(cc2538_reg_t*)0x44004014 )
778#define PKA_SHIFT ( *(cc2538_reg_t*)0x44004018 )
779#define PKA_FUNCTION ( *(cc2538_reg_t*)0x4400401c )
780#define PKA_COMPARE ( *(cc2538_reg_t*)0x44004020 )
781#define PKA_MSW ( *(cc2538_reg_t*)0x44004024 )
782#define PKA_DIVMSW ( *(cc2538_reg_t*)0x44004028 )
783#define PKA_SEQ_CTRL ( *(cc2538_reg_t*)0x440040c8 )
784#define PKA_OPTIONS ( *(cc2538_reg_t*)0x440040f4 )
785#define PKA_SW_REV ( *(cc2538_reg_t*)0x440040f8 )
786#define PKA_REVISION ( *(cc2538_reg_t*)0x440040fc )
787#define CCTEST_IO ( *(cc2538_reg_t*)0x44010000 )
788#define CCTEST_OBSSEL0 ( *(cc2538_reg_t*)0x44010014 )
789#define CCTEST_OBSSEL1 ( *(cc2538_reg_t*)0x44010018 )
790#define CCTEST_OBSSEL2 ( *(cc2538_reg_t*)0x4401001c )
791#define CCTEST_OBSSEL3 ( *(cc2538_reg_t*)0x44010020 )
792#define CCTEST_OBSSEL4 ( *(cc2538_reg_t*)0x44010024 )
793#define CCTEST_OBSSEL5 ( *(cc2538_reg_t*)0x44010028 )
794#define CCTEST_OBSSEL6 ( *(cc2538_reg_t*)0x4401002c )
795#define CCTEST_OBSSEL7 ( *(cc2538_reg_t*)0x44010030 )
796#define CCTEST_TR0 ( *(cc2538_reg_t*)0x44010034 )
797#define CCTEST_USBCTRL ( *(cc2538_reg_t*)0x44010050 )
800#define XOSC32M_FREQ 32000000U
801#define RCOSC16M_FREQ 16000000U
803#define XOSC32K_FREQ 32768U
804#define RCOSC32K_FREQ 32753U
806#define CC2538_VTOR_ALIGN 512
808#ifdef __cplusplus
809}
810#endif
811
812#endif /* CC2538_H */
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition cc2538.h:124
void UsageFault_Handler(void)
Usage fault handler.
void HardFault_Handler(void)
Hard fault handler.
void MemManage_Handler(void)
Memory management handler.
void SVC_Handler(void)
SVC handler.
enum IRQn IRQn_Type
Interrupt Number Definition.
void PendSV_Handler(void)
PendSV handler.
IRQn
Interrupt Number Definition.
Definition cc2538.h:35
void NMI_Handler(void)
NMI handler.
void BusFault_Handler(void)
Bus fault handler.
void SysTick_Handler(void)
SysTick handler.
void DebugMon_Handler(void)
Debug monitor handler.
void Reset_Handler(void)
Reset handler.
@ SSI0_IRQn
SSI0
Definition cc2538.h:55
@ GPTIMER_2A_IRQn
GPTimer 2A
Definition cc2538.h:63
@ PendSV_IRQn
14 Cortex-M3 Pend SV Interrupt
Definition cc2538.h:45
@ UDMA_IRQn
uDMA software
Definition cc2538.h:77
@ PKA_IRQn
PKA
Definition cc2538.h:83
@ PKA_ALT_IRQn
PKA (Alternate)
Definition cc2538.h:71
@ RF_RXTX_IRQn
RF Core Rx/Tx
Definition cc2538.h:80
@ MemoryManagement_IRQn
4 Cortex-M3 Memory Management Interrupt
Definition cc2538.h:40
@ UDMA_ERR_IRQn
uDMA error
Definition cc2538.h:78
@ GPTIMER_1B_IRQn
GPTimer 1B
Definition cc2538.h:62
@ SVCall_IRQn
11 Cortex-M3 SV Call Interrupt
Definition cc2538.h:43
@ ADC_IRQn
ADC
Definition cc2538.h:57
@ RF_RXTX_ALT_IRQn
RF TX/RX (Alternate)
Definition cc2538.h:66
@ ADC_CMP_IRQn
Analog Comparator
Definition cc2538.h:65
@ USB_IRQn
USB
Definition cc2538.h:79
@ RF_ERR_ALT_IRQn
RF Error (Alternate)
Definition cc2538.h:67
@ GPIO_PORT_D_IRQn
GPIO port D
Definition cc2538.h:52
@ UsageFault_IRQn
6 Cortex-M3 Usage Fault Interrupt
Definition cc2538.h:42
@ SysTick_IRQn
15 Cortex-M3 System Tick Interrupt
Definition cc2538.h:46
@ WDT_IRQn
Watchdog Timer
Definition cc2538.h:58
@ RF_ERR_IRQn
RF Core Error
Definition cc2538.h:81
@ ResetHandler_IRQn
1 Reset Handler
Definition cc2538.h:37
@ GPTIMER_3A_IRQn
GPTimer 3A
Definition cc2538.h:75
@ PERIPH_COUNT_IRQn
Number of peripheral IDs.
Definition cc2538.h:87
@ AES_IRQn
AES
Definition cc2538.h:82
@ BusFault_IRQn
5 Cortex-M3 Bus Fault Interrupt
Definition cc2538.h:41
@ GPTIMER_2B_IRQn
GPTimer 2B
Definition cc2538.h:64
@ DebugMonitor_IRQn
12 Cortex-M3 Debug Monitor Interrupt
Definition cc2538.h:44
@ GPIO_PORT_A_IRQn
GPIO port A
Definition cc2538.h:49
@ MAC_TIMER_ALT_IRQn
MAC Timer (Alternate)
Definition cc2538.h:73
@ SM_TIMER_IRQn
SM Timer
Definition cc2538.h:84
@ UART1_IRQn
UART1
Definition cc2538.h:54
@ FLASH_CTRL_IRQn
Flash memory control
Definition cc2538.h:69
@ GPIO_PORT_C_IRQn
GPIO port C
Definition cc2538.h:51
@ HardFault_IRQn
3 Cortex-M3 Hard Fault Interrupt
Definition cc2538.h:39
@ GPTIMER_1A_IRQn
GPTimer 1A
Definition cc2538.h:61
@ MACTIMER_IRQn
MAC Timer
Definition cc2538.h:85
@ GPIO_PORT_B_IRQn
GPIO port B
Definition cc2538.h:50
@ GPTIMER_0B_IRQn
GPTimer 0B
Definition cc2538.h:60
@ SYS_CTRL_IRQn
System Control
Definition cc2538.h:68
@ NonMaskableInt_IRQn
2 Non Maskable Interrupt
Definition cc2538.h:38
@ I2C_IRQn
I2C
Definition cc2538.h:56
@ SSI1_IRQn
SSI1
Definition cc2538.h:74
@ UART0_IRQn
UART0
Definition cc2538.h:53
@ GPTIMER_0A_IRQn
GPTimer 0A
Definition cc2538.h:59
@ AES_ALT_IRQn
AES (Alternate)
Definition cc2538.h:70
@ SM_TIMER_ALT_IRQn
SM Timer (Alternate)
Definition cc2538.h:72
@ GPTIMER_3B_IRQn
GPTimer 3B
Definition cc2538.h:76