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cc2538.h File Reference

CC2538 MCU interrupt and register definitions. More...

Detailed Description

CC2538 MCU interrupt and register definitions.

Author
Ian Martin ian@l.nosp@m.ocic.nosp@m.ontro.nosp@m.ls.c.nosp@m.om

Definition in file cc2538.h.

#include <core_cm3.h>
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Go to the source code of this file.

Macros

#define __CM3_REV   0x0200
 Configuration of the Cortex-M3 Processor and Core Peripherals.
 
#define __MPU_PRESENT   1
 CC2538 does provide a MPU.
 
#define __NVIC_PRIO_BITS   3
 CC2538 uses 3 Bits for the Priority Levels.
 
#define __Vendor_SysTickConfig   0
 Set to 1 if different SysTick Config is used.
 
#define IEEE_ADDR_MSWORD   ( *(const uint32_t*)0x00280028 )
 CMSIS includes.
 
#define IEEE_ADDR_LSWORD   ( *(const uint32_t*)0x0028002c )
 Least-significant 32 bits of the IEEE address.
 
#define FLASH_BASE   0x00200000
 FLASH base address.
 
#define SRAM_BASE   0x20000000
 SRAM base address.
 
#define PERIPH_BASE   0x40000000
 Peripheral base address.
 
#define SRAM_BB_BASE   0x22000000
 SRAM base address in the bit-band region.
 
#define XOSC32M_FREQ   32000000U
 32 MHz external oscillator/clock frequency
 
#define RCOSC16M_FREQ   16000000U
 16 MHz internal RC oscillator frequency
 
#define XOSC32K_FREQ   32768U
 32 KHz external oscillator/clock frequency
 
#define RCOSC32K_FREQ   32753U
 32 KHz internal RC oscillator frequency
 
#define CC2538_VTOR_ALIGN   512
 CC2538 Vector Table alignment.
 

Typedefs

typedef volatile uint32_t cc2538_reg_t
 Least-significant 32 bits of the IEEE address.
 

CC2538 Special Function Registers

#define SSI0_CR0   ( *(cc2538_reg_t*)0x40008000 )
 SSI0 Control Register 0.
 
#define SSI0_CR1   ( *(cc2538_reg_t*)0x40008004 )
 SSI0 Control Register 1.
 
#define SSI0_DR   ( *(cc2538_reg_t*)0x40008008 )
 SSI0 Data register.
 
#define SSI0_SR   ( *(cc2538_reg_t*)0x4000800c )
 SSI0 FIFO/busy Status Register.
 
#define SSI0_CPSR   ( *(cc2538_reg_t*)0x40008010 )
 SSI0 Clock Register.
 
#define SSI0_IM   ( *(cc2538_reg_t*)0x40008014 )
 SSI0 Interrupt Mask register.
 
#define SSI0_RIS   ( *(cc2538_reg_t*)0x40008018 )
 SSI0 Raw Interrupt Status register.
 
#define SSI0_MIS   ( *(cc2538_reg_t*)0x4000801c )
 SSI0 Masked Interrupt Status register.
 
#define SSI0_ICR   ( *(cc2538_reg_t*)0x40008020 )
 SSI0 Interrupt Clear Register.
 
#define SSI0_DMACTL   ( *(cc2538_reg_t*)0x40008024 )
 SSI0 uDMA Control Register.
 
#define SSI0_CC   ( *(cc2538_reg_t*)0x40008fc8 )
 SSI0 clock configuration.
 
#define SSI1_CR0   ( *(cc2538_reg_t*)0x40009000 )
 SSI1 Control Register 0.
 
#define SSI1_CR1   ( *(cc2538_reg_t*)0x40009004 )
 SSI1 Control Register 1.
 
#define SSI1_DR   ( *(cc2538_reg_t*)0x40009008 )
 SSI1 Data register.
 
#define SSI1_SR   ( *(cc2538_reg_t*)0x4000900c )
 SSI1 FIFO/busy Status Register.
 
#define SSI1_CPSR   ( *(cc2538_reg_t*)0x40009010 )
 SSI1 Clock Register.
 
#define SSI1_IM   ( *(cc2538_reg_t*)0x40009014 )
 SSI1 Interrupt Mask register.
 
#define SSI1_RIS   ( *(cc2538_reg_t*)0x40009018 )
 SSI1 Raw Interrupt Status register.
 
#define SSI1_MIS   ( *(cc2538_reg_t*)0x4000901c )
 SSI1 Masked Interrupt Status register.
 
#define SSI1_ICR   ( *(cc2538_reg_t*)0x40009020 )
 SSI1 Interrupt Clear Register.
 
#define SSI1_DMACTL   ( *(cc2538_reg_t*)0x40009024 )
 SSI1 uDMA Control Register.
 
#define SSI1_CC   ( *(cc2538_reg_t*)0x40009fc8 )
 SSI1 clock configuration.
 
#define UART0_DR   ( *(cc2538_reg_t*)0x4000c000 )
 UART0 Data Register.
 
#define UART0_ECR   ( *(cc2538_reg_t*)0x4000c004 )
 UART0 receive status and error clear.
 
#define UART0_RSR   ( *(cc2538_reg_t*)0x4000c004 )
 UART0 receive status and error clear.
 
#define UART0_FR   ( *(cc2538_reg_t*)0x4000c018 )
 UART0 flag.
 
#define UART0_ILPR   ( *(cc2538_reg_t*)0x4000c020 )
 UART0 IrDA low-power register.
 
#define UART0_IBRD   ( *(cc2538_reg_t*)0x4000c024 )
 UART0 integer baud-rate divisor.
 
#define UART0_FBRD   ( *(cc2538_reg_t*)0x4000c028 )
 UART0 fractional baud-rate divisor.
 
#define UART0_LCRH   ( *(cc2538_reg_t*)0x4000c02c )
 UART0 line control.
 
#define UART0_CTL   ( *(cc2538_reg_t*)0x4000c030 )
 UART0 control.
 
#define UART0_IFLS   ( *(cc2538_reg_t*)0x4000c034 )
 UART0 interrupt FIFO level select.
 
#define UART0_IM   ( *(cc2538_reg_t*)0x4000c038 )
 UART0 interrupt mask.
 
#define UART0_RIS   ( *(cc2538_reg_t*)0x4000c03c )
 UART0 raw interrupt status.
 
#define UART0_MIS   ( *(cc2538_reg_t*)0x4000c040 )
 UART0 masked interrupt status.
 
#define UART0_ICR   ( *(cc2538_reg_t*)0x4000c044 )
 UART0 interrupt clear.
 
#define UART0_DMACTL   ( *(cc2538_reg_t*)0x4000c048 )
 UART0 DMA control.
 
#define UART0_LCTL   ( *(cc2538_reg_t*)0x4000c090 )
 UART0 LIN control.
 
#define UART0_LSS   ( *(cc2538_reg_t*)0x4000c094 )
 UART0 LIN snap shot.
 
#define UART0_LTIM   ( *(cc2538_reg_t*)0x4000c098 )
 UART0 LIN timer.
 
#define UART0_NINEBITADDR   ( *(cc2538_reg_t*)0x4000c0a4 )
 UART0 9-bit self address.
 
#define UART0_NINEBITAMASK   ( *(cc2538_reg_t*)0x4000c0a8 )
 UART0 9-bit self address mask.
 
#define UART0_PP   ( *(cc2538_reg_t*)0x4000cfc0 )
 UART0 peripheral properties.
 
#define UART0_CC   ( *(cc2538_reg_t*)0x4000cfc8 )
 UART0 clock configuration.
 
#define UART1_DR   ( *(cc2538_reg_t*)0x4000d000 )
 UART1 Data Register.
 
#define UART1_ECR   ( *(cc2538_reg_t*)0x4000d004 )
 UART1 receive status and error clear.
 
#define UART1_RSR   ( *(cc2538_reg_t*)0x4000d004 )
 UART1 receive status and error clear.
 
#define UART1_FR   ( *(cc2538_reg_t*)0x4000d018 )
 UART1 flag.
 
#define UART1_ILPR   ( *(cc2538_reg_t*)0x4000d020 )
 UART1 IrDA low-power register.
 
#define UART1_IBRD   ( *(cc2538_reg_t*)0x4000d024 )
 UART1 integer baud-rate divisor.
 
#define UART1_FBRD   ( *(cc2538_reg_t*)0x4000d028 )
 UART1 fractional baud-rate divisor.
 
#define UART1_LCRH   ( *(cc2538_reg_t*)0x4000d02c )
 UART1 line control.
 
#define UART1_CTL   ( *(cc2538_reg_t*)0x4000d030 )
 UART1 control.
 
#define UART1_IFLS   ( *(cc2538_reg_t*)0x4000d034 )
 UART1 interrupt FIFO level select.
 
#define UART1_IM   ( *(cc2538_reg_t*)0x4000d038 )
 UART1 interrupt mask.
 
#define UART1_RIS   ( *(cc2538_reg_t*)0x4000d03c )
 UART1 raw interrupt status.
 
#define UART1_MIS   ( *(cc2538_reg_t*)0x4000d040 )
 UART1 masked interrupt status.
 
#define UART1_ICR   ( *(cc2538_reg_t*)0x4000d044 )
 UART1 interrupt clear.
 
#define UART1_DMACTL   ( *(cc2538_reg_t*)0x4000d048 )
 UART1 DMA control.
 
#define UART1_LCTL   ( *(cc2538_reg_t*)0x4000d090 )
 UART1 LIN control.
 
#define UART1_LSS   ( *(cc2538_reg_t*)0x4000d094 )
 UART1 LIN snap shot.
 
#define UART1_LTIM   ( *(cc2538_reg_t*)0x4000d098 )
 UART1 LIN timer.
 
#define UART1_NINEBITADDR   ( *(cc2538_reg_t*)0x4000d0a4 )
 UART1 9-bit self address.
 
#define UART1_NINEBITAMASK   ( *(cc2538_reg_t*)0x4000d0a8 )
 UART1 9-bit self address mask.
 
#define UART1_PP   ( *(cc2538_reg_t*)0x4000dfc0 )
 UART1 peripheral properties.
 
#define UART1_CC   ( *(cc2538_reg_t*)0x4000dfc8 )
 UART1 clock configuration.
 
#define I2CM_SA   ( *(cc2538_reg_t*)0x40020000 )
 I2C Master Slave address.
 
#define I2CM_CTRL   ( *(cc2538_reg_t*)0x40020004 )
 I2C Master Control and status.
 
#define I2CM_STAT   ( *(cc2538_reg_t*)0x40020004 )
 I2C Master Control and status.
 
#define I2CM_DR   ( *(cc2538_reg_t*)0x40020008 )
 I2C Master Data.
 
#define I2CM_TPR   ( *(cc2538_reg_t*)0x4002000c )
 I2C Master Timer period.
 
#define I2CM_IMR   ( *(cc2538_reg_t*)0x40020010 )
 I2C Master Interrupt mask.
 
#define I2CM_RIS   ( *(cc2538_reg_t*)0x40020014 )
 I2C Master Raw interrupt status.
 
#define I2CM_MIS   ( *(cc2538_reg_t*)0x40020018 )
 I2C Master Masked interrupt status.
 
#define I2CM_ICR   ( *(cc2538_reg_t*)0x4002001c )
 I2C Master Interrupt clear.
 
#define I2CM_CR   ( *(cc2538_reg_t*)0x40020020 )
 I2C Master Configuration.
 
#define I2CS_OAR   ( *(cc2538_reg_t*)0x40020800 )
 I2C Slave own address.
 
#define I2CS_CTRL   ( *(cc2538_reg_t*)0x40020804 )
 I2C Slave Control and status.
 
#define I2CS_STAT   ( *(cc2538_reg_t*)0x40020804 )
 I2C Slave Control and status.
 
#define I2CS_DR   ( *(cc2538_reg_t*)0x40020808 )
 I2C Slave Data.
 
#define I2CS_IMR   ( *(cc2538_reg_t*)0x4002080c )
 I2C Slave Interrupt mask.
 
#define I2CS_RIS   ( *(cc2538_reg_t*)0x40020810 )
 I2C Slave Raw interrupt status.
 
#define I2CS_MIS   ( *(cc2538_reg_t*)0x40020814 )
 I2C Slave Masked interrupt status.
 
#define I2CS_ICR   ( *(cc2538_reg_t*)0x40020818 )
 I2C Slave Interrupt clear.
 
#define GPTIMER0_CFG   ( *(cc2538_reg_t*)0x40030000 )
 GPTM0 configuration.
 
#define GPTIMER0_TAMR   ( *(cc2538_reg_t*)0x40030004 )
 GPTM0 Timer A mode.
 
#define GPTIMER0_TBMR   ( *(cc2538_reg_t*)0x40030008 )
 GPTM0 Timer B mode.
 
#define GPTIMER0_CTL   ( *(cc2538_reg_t*)0x4003000c )
 GPTM0 control.
 
#define GPTIMER0_SYNC   ( *(cc2538_reg_t*)0x40030010 )
 GPTM0 synchronize.
 
#define GPTIMER0_IMR   ( *(cc2538_reg_t*)0x40030018 )
 GPTM0 interrupt mask.
 
#define GPTIMER0_RIS   ( *(cc2538_reg_t*)0x4003001c )
 GPTM0 raw interrupt status.
 
#define GPTIMER0_MIS   ( *(cc2538_reg_t*)0x40030020 )
 GPTM0 masked interrupt status.
 
#define GPTIMER0_ICR   ( *(cc2538_reg_t*)0x40030024 )
 GPTM0 interrupt clear.
 
#define GPTIMER0_TAILR   ( *(cc2538_reg_t*)0x40030028 )
 GPTM0 Timer A interval load.
 
#define GPTIMER0_TBILR   ( *(cc2538_reg_t*)0x4003002c )
 GPTM0 Timer B interval load.
 
#define GPTIMER0_TAMATCHR   ( *(cc2538_reg_t*)0x40030030 )
 GPTM0 Timer A match.
 
#define GPTIMER0_TBMATCHR   ( *(cc2538_reg_t*)0x40030034 )
 GPTM0 Timer B match.
 
#define GPTIMER0_TAPR   ( *(cc2538_reg_t*)0x40030038 )
 GPTM0 Timer A prescale.
 
#define GPTIMER0_TBPR   ( *(cc2538_reg_t*)0x4003003c )
 GPTM0 Timer B prescale.
 
#define GPTIMER0_TAPMR   ( *(cc2538_reg_t*)0x40030040 )
 GPTM0 Timer A prescale match.
 
#define GPTIMER0_TBPMR   ( *(cc2538_reg_t*)0x40030044 )
 GPTM0 Timer B prescale match.
 
#define GPTIMER0_TAR   ( *(cc2538_reg_t*)0x40030048 )
 GPTM0 Timer A.
 
#define GPTIMER0_TBR   ( *(cc2538_reg_t*)0x4003004c )
 GPTM0 Timer B.
 
#define GPTIMER0_TAV   ( *(cc2538_reg_t*)0x40030050 )
 GPTM0 Timer A value.
 
#define GPTIMER0_TBV   ( *(cc2538_reg_t*)0x40030054 )
 GPTM0 Timer B value.
 
#define GPTIMER0_TAPS   ( *(cc2538_reg_t*)0x4003005c )
 GPTM0 Timer A prescale snapshot.
 
#define GPTIMER0_TBPS   ( *(cc2538_reg_t*)0x40030060 )
 GPTM0 Timer B prescale snapshot.
 
#define GPTIMER0_TAPV   ( *(cc2538_reg_t*)0x40030064 )
 GPTM0 Timer A prescale value.
 
#define GPTIMER0_TBPV   ( *(cc2538_reg_t*)0x40030068 )
 GPTM0 Timer B prescale value.
 
#define GPTIMER0_PP   ( *(cc2538_reg_t*)0x40030fc0 )
 GPTM0 peripheral properties.
 
#define GPTIMER1_CFG   ( *(cc2538_reg_t*)0x40031000 )
 GPTM1 configuration.
 
#define GPTIMER1_TAMR   ( *(cc2538_reg_t*)0x40031004 )
 GPTM1 Timer A mode.
 
#define GPTIMER1_TBMR   ( *(cc2538_reg_t*)0x40031008 )
 GPTM1 Timer B mode.
 
#define GPTIMER1_CTL   ( *(cc2538_reg_t*)0x4003100c )
 GPTM1 control.
 
#define GPTIMER1_SYNC   ( *(cc2538_reg_t*)0x40031010 )
 GPTM1 synchronize.
 
#define GPTIMER1_IMR   ( *(cc2538_reg_t*)0x40031018 )
 GPTM1 interrupt mask.
 
#define GPTIMER1_RIS   ( *(cc2538_reg_t*)0x4003101c )
 GPTM1 raw interrupt status.
 
#define GPTIMER1_MIS   ( *(cc2538_reg_t*)0x40031020 )
 GPTM1 masked interrupt status.
 
#define GPTIMER1_ICR   ( *(cc2538_reg_t*)0x40031024 )
 GPTM1 interrupt clear.
 
#define GPTIMER1_TAILR   ( *(cc2538_reg_t*)0x40031028 )
 GPTM1 Timer A interval load.
 
#define GPTIMER1_TBILR   ( *(cc2538_reg_t*)0x4003102c )
 GPTM1 Timer B interval load.
 
#define GPTIMER1_TAMATCHR   ( *(cc2538_reg_t*)0x40031030 )
 GPTM1 Timer A match.
 
#define GPTIMER1_TBMATCHR   ( *(cc2538_reg_t*)0x40031034 )
 GPTM1 Timer B match.
 
#define GPTIMER1_TAPR   ( *(cc2538_reg_t*)0x40031038 )
 GPTM1 Timer A prescale.
 
#define GPTIMER1_TBPR   ( *(cc2538_reg_t*)0x4003103c )
 GPTM1 Timer B prescale.
 
#define GPTIMER1_TAPMR   ( *(cc2538_reg_t*)0x40031040 )
 GPTM1 Timer A prescale match.
 
#define GPTIMER1_TBPMR   ( *(cc2538_reg_t*)0x40031044 )
 GPTM1 Timer B prescale match.
 
#define GPTIMER1_TAR   ( *(cc2538_reg_t*)0x40031048 )
 GPTM1 Timer A.
 
#define GPTIMER1_TBR   ( *(cc2538_reg_t*)0x4003104c )
 GPTM1 Timer B.
 
#define GPTIMER1_TAV   ( *(cc2538_reg_t*)0x40031050 )
 GPTM1 Timer A value.
 
#define GPTIMER1_TBV   ( *(cc2538_reg_t*)0x40031054 )
 GPTM1 Timer B value.
 
#define GPTIMER1_TAPS   ( *(cc2538_reg_t*)0x4003105c )
 GPTM1 Timer A prescale snapshot.
 
#define GPTIMER1_TBPS   ( *(cc2538_reg_t*)0x40031060 )
 GPTM1 Timer B prescale snapshot.
 
#define GPTIMER1_TAPV   ( *(cc2538_reg_t*)0x40031064 )
 GPTM1 Timer A prescale value.
 
#define GPTIMER1_TBPV   ( *(cc2538_reg_t*)0x40031068 )
 GPTM1 Timer B prescale value.
 
#define GPTIMER1_PP   ( *(cc2538_reg_t*)0x40031fc0 )
 GPTM1 peripheral properties.
 
#define GPTIMER2_CFG   ( *(cc2538_reg_t*)0x40032000 )
 GPTM2 configuration.
 
#define GPTIMER2_TAMR   ( *(cc2538_reg_t*)0x40032004 )
 GPTM2 Timer A mode.
 
#define GPTIMER2_TBMR   ( *(cc2538_reg_t*)0x40032008 )
 GPTM2 Timer B mode.
 
#define GPTIMER2_CTL   ( *(cc2538_reg_t*)0x4003200c )
 GPTM2 control.
 
#define GPTIMER2_SYNC   ( *(cc2538_reg_t*)0x40032010 )
 GPTM2 synchronize.
 
#define GPTIMER2_IMR   ( *(cc2538_reg_t*)0x40032018 )
 GPTM2 interrupt mask.
 
#define GPTIMER2_RIS   ( *(cc2538_reg_t*)0x4003201c )
 GPTM2 raw interrupt status.
 
#define GPTIMER2_MIS   ( *(cc2538_reg_t*)0x40032020 )
 GPTM2 masked interrupt status.
 
#define GPTIMER2_ICR   ( *(cc2538_reg_t*)0x40032024 )
 GPTM2 interrupt clear.
 
#define GPTIMER2_TAILR   ( *(cc2538_reg_t*)0x40032028 )
 GPTM2 Timer A interval load.
 
#define GPTIMER2_TBILR   ( *(cc2538_reg_t*)0x4003202c )
 GPTM2 Timer B interval load.
 
#define GPTIMER2_TAMATCHR   ( *(cc2538_reg_t*)0x40032030 )
 GPTM2 Timer A match.
 
#define GPTIMER2_TBMATCHR   ( *(cc2538_reg_t*)0x40032034 )
 GPTM2 Timer B match.
 
#define GPTIMER2_TAPR   ( *(cc2538_reg_t*)0x40032038 )
 GPTM2 Timer A prescale.
 
#define GPTIMER2_TBPR   ( *(cc2538_reg_t*)0x4003203c )
 GPTM2 Timer B prescale.
 
#define GPTIMER2_TAPMR   ( *(cc2538_reg_t*)0x40032040 )
 GPTM2 Timer A prescale match.
 
#define GPTIMER2_TBPMR   ( *(cc2538_reg_t*)0x40032044 )
 GPTM2 Timer B prescale match.
 
#define GPTIMER2_TAR   ( *(cc2538_reg_t*)0x40032048 )
 GPTM2 Timer A.
 
#define GPTIMER2_TBR   ( *(cc2538_reg_t*)0x4003204c )
 GPTM2 Timer B.
 
#define GPTIMER2_TAV   ( *(cc2538_reg_t*)0x40032050 )
 GPTM2 Timer A value.
 
#define GPTIMER2_TBV   ( *(cc2538_reg_t*)0x40032054 )
 GPTM2 Timer B value.
 
#define GPTIMER2_TAPS   ( *(cc2538_reg_t*)0x4003205c )
 GPTM2 Timer A prescale snapshot.
 
#define GPTIMER2_TBPS   ( *(cc2538_reg_t*)0x40032060 )
 GPTM2 Timer B prescale snapshot.
 
#define GPTIMER2_TAPV   ( *(cc2538_reg_t*)0x40032064 )
 GPTM2 Timer A prescale value.
 
#define GPTIMER2_TBPV   ( *(cc2538_reg_t*)0x40032068 )
 GPTM2 Timer B prescale value.
 
#define GPTIMER2_PP   ( *(cc2538_reg_t*)0x40032fc0 )
 GPTM2 peripheral properties.
 
#define GPTIMER3_CFG   ( *(cc2538_reg_t*)0x40033000 )
 GPTM3 configuration.
 
#define GPTIMER3_TAMR   ( *(cc2538_reg_t*)0x40033004 )
 GPTM3 Timer A mode.
 
#define GPTIMER3_TBMR   ( *(cc2538_reg_t*)0x40033008 )
 GPTM3 Timer B mode.
 
#define GPTIMER3_CTL   ( *(cc2538_reg_t*)0x4003300c )
 GPTM3 control.
 
#define GPTIMER3_SYNC   ( *(cc2538_reg_t*)0x40033010 )
 GPTM3 synchronize.
 
#define GPTIMER3_IMR   ( *(cc2538_reg_t*)0x40033018 )
 GPTM3 interrupt mask.
 
#define GPTIMER3_RIS   ( *(cc2538_reg_t*)0x4003301c )
 GPTM3 raw interrupt status.
 
#define GPTIMER3_MIS   ( *(cc2538_reg_t*)0x40033020 )
 GPTM3 masked interrupt status.
 
#define GPTIMER3_ICR   ( *(cc2538_reg_t*)0x40033024 )
 GPTM3 interrupt clear.
 
#define GPTIMER3_TAILR   ( *(cc2538_reg_t*)0x40033028 )
 GPTM3 Timer A interval load.
 
#define GPTIMER3_TBILR   ( *(cc2538_reg_t*)0x4003302c )
 GPTM3 Timer B interval load.
 
#define GPTIMER3_TAMATCHR   ( *(cc2538_reg_t*)0x40033030 )
 GPTM3 Timer A match.
 
#define GPTIMER3_TBMATCHR   ( *(cc2538_reg_t*)0x40033034 )
 GPTM3 Timer B match.
 
#define GPTIMER3_TAPR   ( *(cc2538_reg_t*)0x40033038 )
 GPTM3 Timer A prescale.
 
#define GPTIMER3_TBPR   ( *(cc2538_reg_t*)0x4003303c )
 GPTM3 Timer B prescale.
 
#define GPTIMER3_TAPMR   ( *(cc2538_reg_t*)0x40033040 )
 GPTM3 Timer A prescale match.
 
#define GPTIMER3_TBPMR   ( *(cc2538_reg_t*)0x40033044 )
 GPTM3 Timer B prescale match.
 
#define GPTIMER3_TAR   ( *(cc2538_reg_t*)0x40033048 )
 GPTM3 Timer A.
 
#define GPTIMER3_TBR   ( *(cc2538_reg_t*)0x4003304c )
 GPTM3 Timer B.
 
#define GPTIMER3_TAV   ( *(cc2538_reg_t*)0x40033050 )
 GPTM3 Timer A value.
 
#define GPTIMER3_TBV   ( *(cc2538_reg_t*)0x40033054 )
 GPTM3 Timer B value.
 
#define GPTIMER3_TAPS   ( *(cc2538_reg_t*)0x4003305c )
 GPTM3 Timer A prescale snapshot.
 
#define GPTIMER3_TBPS   ( *(cc2538_reg_t*)0x40033060 )
 GPTM3 Timer B prescale snapshot.
 
#define GPTIMER3_TAPV   ( *(cc2538_reg_t*)0x40033064 )
 GPTM3 Timer A prescale value.
 
#define GPTIMER3_TBPV   ( *(cc2538_reg_t*)0x40033068 )
 GPTM3 Timer B prescale value.
 
#define GPTIMER3_PP   ( *(cc2538_reg_t*)0x40033fc0 )
 GPTM3 peripheral properties.
 
#define RFCORE_FFSM_SRCRESMASK0   ( *(cc2538_reg_t*)0x40088580 )
 RF Source address matching result.
 
#define RFCORE_FFSM_SRCRESMASK1   ( *(cc2538_reg_t*)0x40088584 )
 RF Source address matching result.
 
#define RFCORE_FFSM_SRCRESMASK2   ( *(cc2538_reg_t*)0x40088588 )
 RF Source address matching result.
 
#define RFCORE_FFSM_SRCRESINDEX   ( *(cc2538_reg_t*)0x4008858c )
 RF Source address matching result.
 
#define RFCORE_FFSM_SRCEXTPENDEN0   ( *(cc2538_reg_t*)0x40088590 )
 RF Source address matching control.
 
#define RFCORE_FFSM_SRCEXTPENDEN1   ( *(cc2538_reg_t*)0x40088594 )
 RF Source address matching control.
 
#define RFCORE_FFSM_SRCEXTPENDEN2   ( *(cc2538_reg_t*)0x40088598 )
 RF Source address matching control.
 
#define RFCORE_FFSM_SRCSHORTPENDEN0   ( *(cc2538_reg_t*)0x4008859c )
 RF Source address matching control.
 
#define RFCORE_FFSM_SRCSHORTPENDEN1   ( *(cc2538_reg_t*)0x400885a0 )
 RF Source address matching control.
 
#define RFCORE_FFSM_SRCSHORTPENDEN2   ( *(cc2538_reg_t*)0x400885a4 )
 RF Source address matching control.
 
#define RFCORE_FFSM_EXT_ADDR0   ( *(cc2538_reg_t*)0x400885a8 )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR1   ( *(cc2538_reg_t*)0x400885ac )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR2   ( *(cc2538_reg_t*)0x400885b0 )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR3   ( *(cc2538_reg_t*)0x400885b4 )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR4   ( *(cc2538_reg_t*)0x400885b8 )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR5   ( *(cc2538_reg_t*)0x400885bc )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR6   ( *(cc2538_reg_t*)0x400885c0 )
 RF Local address information.
 
#define RFCORE_FFSM_EXT_ADDR7   ( *(cc2538_reg_t*)0x400885c4 )
 RF Local address information.
 
#define RFCORE_FFSM_PAN_ID0   ( *(cc2538_reg_t*)0x400885c8 )
 RF Local address information.
 
#define RFCORE_FFSM_PAN_ID1   ( *(cc2538_reg_t*)0x400885cc )
 RF Local address information.
 
#define RFCORE_FFSM_SHORT_ADDR0   ( *(cc2538_reg_t*)0x400885d0 )
 RF Local address information.
 
#define RFCORE_FFSM_SHORT_ADDR1   ( *(cc2538_reg_t*)0x400885d4 )
 RF Local address information.
 
#define RFCORE_XREG_FRMFILT0   ( *(cc2538_reg_t*)0x40088600 )
 RF Frame Filter 0.
 
#define RFCORE_XREG_FRMFILT1   ( *(cc2538_reg_t*)0x40088604 )
 RF Frame Filter 1.
 
#define RFCORE_XREG_SRCMATCH   ( *(cc2538_reg_t*)0x40088608 )
 RF Source address matching and pending bits.
 
#define RFCORE_XREG_SRCSHORTEN0   ( *(cc2538_reg_t*)0x4008860c )
 RF Short address matching.
 
#define RFCORE_XREG_SRCSHORTEN1   ( *(cc2538_reg_t*)0x40088610 )
 RF Short address matching.
 
#define RFCORE_XREG_SRCSHORTEN2   ( *(cc2538_reg_t*)0x40088614 )
 RF Short address matching.
 
#define RFCORE_XREG_SRCEXTEN0   ( *(cc2538_reg_t*)0x40088618 )
 RF Extended address matching.
 
#define RFCORE_XREG_SRCEXTEN1   ( *(cc2538_reg_t*)0x4008861c )
 RF Extended address matching.
 
#define RFCORE_XREG_SRCEXTEN2   ( *(cc2538_reg_t*)0x40088620 )
 RF Extended address matching.
 
#define RFCORE_XREG_FRMCTRL0   ( *(cc2538_reg_t*)0x40088624 )
 RF Frame handling.
 
#define RFCORE_XREG_FRMCTRL1   ( *(cc2538_reg_t*)0x40088628 )
 RF Frame handling.
 
#define RFCORE_XREG_RXENABLE   ( *(cc2538_reg_t*)0x4008862c )
 RF RX enabling.
 
#define RFCORE_XREG_RXMASKSET   ( *(cc2538_reg_t*)0x40088630 )
 RF RX enabling.
 
#define RFCORE_XREG_RXMASKCLR   ( *(cc2538_reg_t*)0x40088634 )
 RF RX disabling.
 
#define RFCORE_XREG_FREQTUNE   ( *(cc2538_reg_t*)0x40088638 )
 RF Crystal oscillator frequency tuning.
 
#define RFCORE_XREG_FREQCTRL   ( *(cc2538_reg_t*)0x4008863c )
 RF Controls the RF frequency.
 
#define RFCORE_XREG_TXPOWER   ( *(cc2538_reg_t*)0x40088640 )
 RF Controls the output power.
 
#define RFCORE_XREG_TXCTRL   ( *(cc2538_reg_t*)0x40088644 )
 RF Controls the TX settings.
 
#define RFCORE_XREG_FSMSTAT0   ( *(cc2538_reg_t*)0x40088648 )
 RF Radio status register.
 
#define RFCORE_XREG_FSMSTAT1   ( *(cc2538_reg_t*)0x4008864c )
 RF Radio status register.
 
#define RFCORE_XREG_FIFOPCTRL   ( *(cc2538_reg_t*)0x40088650 )
 RF FIFOP threshold.
 
#define RFCORE_XREG_FSMCTRL   ( *(cc2538_reg_t*)0x40088654 )
 RF FSM options.
 
#define RFCORE_XREG_CCACTRL0   ( *(cc2538_reg_t*)0x40088658 )
 RF CCA threshold.
 
#define RFCORE_XREG_CCACTRL1   ( *(cc2538_reg_t*)0x4008865c )
 RF Other CCA Options.
 
#define RFCORE_XREG_RSSI   ( *(cc2538_reg_t*)0x40088660 )
 RF RSSI status register.
 
#define RFCORE_XREG_RSSISTAT   ( *(cc2538_reg_t*)0x40088664 )
 RF RSSI valid status register.
 
#define RFCORE_XREG_RXFIRST   ( *(cc2538_reg_t*)0x40088668 )
 RF First byte in RX FIFO.
 
#define RFCORE_XREG_RXFIFOCNT   ( *(cc2538_reg_t*)0x4008866c )
 RF Number of bytes in RX FIFO.
 
#define RFCORE_XREG_TXFIFOCNT   ( *(cc2538_reg_t*)0x40088670 )
 RF Number of bytes in TX FIFO.
 
#define RFCORE_XREG_RXFIRST_PTR   ( *(cc2538_reg_t*)0x40088674 )
 RF RX FIFO pointer.
 
#define RFCORE_XREG_RXLAST_PTR   ( *(cc2538_reg_t*)0x40088678 )
 RF RX FIFO pointer.
 
#define RFCORE_XREG_RXP1_PTR   ( *(cc2538_reg_t*)0x4008867c )
 RF RX FIFO pointer.
 
#define RFCORE_XREG_TXFIRST_PTR   ( *(cc2538_reg_t*)0x40088684 )
 RF TX FIFO pointer.
 
#define RFCORE_XREG_TXLAST_PTR   ( *(cc2538_reg_t*)0x40088688 )
 RF TX FIFO pointer.
 
#define RFCORE_XREG_RFIRQM0   ( *(cc2538_reg_t*)0x4008868c )
 RF interrupt masks.
 
#define RFCORE_XREG_RFIRQM1   ( *(cc2538_reg_t*)0x40088690 )
 RF interrupt masks.
 
#define RFCORE_XREG_RFERRM   ( *(cc2538_reg_t*)0x40088694 )
 RF error interrupt mask.
 
#define RFCORE_XREG_RFRND   ( *(cc2538_reg_t*)0x4008869c )
 RF Random data.
 
#define RFCORE_XREG_MDMCTRL0   ( *(cc2538_reg_t*)0x400886a0 )
 RF Controls modem.
 
#define RFCORE_XREG_MDMCTRL1   ( *(cc2538_reg_t*)0x400886a4 )
 RF Controls modem.
 
#define RFCORE_XREG_FREQEST   ( *(cc2538_reg_t*)0x400886a8 )
 RF Estimated RF frequency offset.
 
#define RFCORE_XREG_RXCTRL   ( *(cc2538_reg_t*)0x400886ac )
 RF Tune receive section.
 
#define RFCORE_XREG_FSCTRL   ( *(cc2538_reg_t*)0x400886b0 )
 RF Tune frequency synthesizer.
 
#define RFCORE_XREG_FSCAL0   ( *(cc2538_reg_t*)0x400886b4 )
 RF Tune frequency calibration.
 
#define RFCORE_XREG_FSCAL1   ( *(cc2538_reg_t*)0x400886b8 )
 RF Tune frequency calibration.
 
#define RFCORE_XREG_FSCAL2   ( *(cc2538_reg_t*)0x400886bc )
 RF Tune frequency calibration.
 
#define RFCORE_XREG_FSCAL3   ( *(cc2538_reg_t*)0x400886c0 )
 RF Tune frequency calibration.
 
#define RFCORE_XREG_AGCCTRL0   ( *(cc2538_reg_t*)0x400886c4 )
 RF AGC dynamic range control.
 
#define RFCORE_XREG_AGCCTRL1   ( *(cc2538_reg_t*)0x400886c8 )
 RF AGC reference level.
 
#define RFCORE_XREG_AGCCTRL2   ( *(cc2538_reg_t*)0x400886cc )
 RF AGC gain override.
 
#define RFCORE_XREG_AGCCTRL3   ( *(cc2538_reg_t*)0x400886d0 )
 RF AGC control.
 
#define RFCORE_XREG_ADCTEST0   ( *(cc2538_reg_t*)0x400886d4 )
 RF ADC tuning.
 
#define RFCORE_XREG_ADCTEST1   ( *(cc2538_reg_t*)0x400886d8 )
 RF ADC tuning.
 
#define RFCORE_XREG_ADCTEST2   ( *(cc2538_reg_t*)0x400886dc )
 RF ADC tuning.
 
#define RFCORE_XREG_MDMTEST0   ( *(cc2538_reg_t*)0x400886e0 )
 RF Test register for modem.
 
#define RFCORE_XREG_MDMTEST1   ( *(cc2538_reg_t*)0x400886e4 )
 RF Test Register for Modem.
 
#define RFCORE_XREG_DACTEST0   ( *(cc2538_reg_t*)0x400886e8 )
 RF DAC override value.
 
#define RFCORE_XREG_DACTEST1   ( *(cc2538_reg_t*)0x400886ec )
 RF DAC override value.
 
#define RFCORE_XREG_DACTEST2   ( *(cc2538_reg_t*)0x400886f0 )
 RF DAC test setting.
 
#define RFCORE_XREG_ATEST   ( *(cc2538_reg_t*)0x400886f4 )
 RF Analog test control.
 
#define RFCORE_XREG_PTEST0   ( *(cc2538_reg_t*)0x400886f8 )
 RF Override power-down register.
 
#define RFCORE_XREG_PTEST1   ( *(cc2538_reg_t*)0x400886fc )
 RF Override power-down register.
 
#define RFCORE_XREG_CSPCTRL   ( *(cc2538_reg_t*)0x40088780 )
 RF CSP control bit.
 
#define RFCORE_XREG_CSPSTAT   ( *(cc2538_reg_t*)0x40088784 )
 RF CSP status register.
 
#define RFCORE_XREG_CSPX   ( *(cc2538_reg_t*)0x40088788 )
 RF CSP X data register.
 
#define RFCORE_XREG_CSPY   ( *(cc2538_reg_t*)0x4008878c )
 RF CSP Y data register.
 
#define RFCORE_XREG_CSPZ   ( *(cc2538_reg_t*)0x40088790 )
 RF CSP Z data register.
 
#define RFCORE_XREG_CSPT   ( *(cc2538_reg_t*)0x40088794 )
 RF CSP T data register.
 
#define RFCORE_XREG_RFC_OBS_CTRL0   ( *(cc2538_reg_t*)0x400887ac )
 RF observation mux control.
 
#define RFCORE_XREG_RFC_OBS_CTRL1   ( *(cc2538_reg_t*)0x400887b0 )
 RF observation mux control.
 
#define RFCORE_XREG_RFC_OBS_CTRL2   ( *(cc2538_reg_t*)0x400887b4 )
 RF observation mux control.
 
#define RFCORE_XREG_TXFILTCFG   ( *(cc2538_reg_t*)0x400887e8 )
 RF TX filter configuration.
 
#define RFCORE_SFR_MTCSPCFG   ( *(cc2538_reg_t*)0x40088800 )
 RF MAC Timer event configuration.
 
#define RFCORE_SFR_MTCTRL   ( *(cc2538_reg_t*)0x40088804 )
 RF MAC Timer control register.
 
#define RFCORE_SFR_MTIRQM   ( *(cc2538_reg_t*)0x40088808 )
 RF MAC Timer interrupt mask.
 
#define RFCORE_SFR_MTIRQF   ( *(cc2538_reg_t*)0x4008880c )
 RF MAC Timer interrupt flags.
 
#define RFCORE_SFR_MTMSEL   ( *(cc2538_reg_t*)0x40088810 )
 RF MAC Timer multiplex select.
 
#define RFCORE_SFR_MTM0   ( *(cc2538_reg_t*)0x40088814 )
 RF MAC Timer multiplexed register 0.
 
#define RFCORE_SFR_MTM1   ( *(cc2538_reg_t*)0x40088818 )
 RF MAC Timer multiplexed register 1.
 
#define RFCORE_SFR_MTMOVF2   ( *(cc2538_reg_t*)0x4008881c )
 RF MAC Timer multiplexed overflow register 2.
 
#define RFCORE_SFR_MTMOVF1   ( *(cc2538_reg_t*)0x40088820 )
 RF MAC Timer multiplexed overflow register 1.
 
#define RFCORE_SFR_MTMOVF0   ( *(cc2538_reg_t*)0x40088824 )
 RF MAC Timer multiplexed overflow register 0.
 
#define RFCORE_SFR_RFDATA   ( *(cc2538_reg_t*)0x40088828 )
 RF Tx/Rx FIFO.
 
#define RFCORE_SFR_RFERRF   ( *(cc2538_reg_t*)0x4008882c )
 RF error interrupt flags.
 
#define RFCORE_SFR_RFIRQF1   ( *(cc2538_reg_t*)0x40088830 )
 RF interrupt flags.
 
#define RFCORE_SFR_RFIRQF0   ( *(cc2538_reg_t*)0x40088834 )
 RF interrupt flags.
 
#define RFCORE_SFR_RFST   ( *(cc2538_reg_t*)0x40088838 )
 RF CSMA-CA/strobe processor.
 
#define USB_ADDR   ( *(cc2538_reg_t*)0x40089000 )
 USB Function address.
 
#define USB_POW   ( *(cc2538_reg_t*)0x40089004 )
 USB Power management and control register.
 
#define USB_IIF   ( *(cc2538_reg_t*)0x40089008 )
 USB Interrupt flags for endpoint 0 and IN endpoints 1-5.
 
#define USB_OIF   ( *(cc2538_reg_t*)0x40089010 )
 USB Interrupt flags for OUT endpoints 1-5.
 
#define USB_CIF   ( *(cc2538_reg_t*)0x40089018 )
 USB Common USB interrupt flags.
 
#define USB_IIE   ( *(cc2538_reg_t*)0x4008901c )
 USB Interrupt enable mask for IN endpoints 1-5 and endpoint 0.
 
#define USB_OIE   ( *(cc2538_reg_t*)0x40089024 )
 USB Interrupt enable mask for OUT endpoints 1-5.
 
#define USB_CIE   ( *(cc2538_reg_t*)0x4008902c )
 USB Common USB interrupt enable mask.
 
#define USB_FRML   ( *(cc2538_reg_t*)0x40089030 )
 USB Frame number (low byte)
 
#define USB_FRMH   ( *(cc2538_reg_t*)0x40089034 )
 USB Frame number (high byte)
 
#define USB_INDEX   ( *(cc2538_reg_t*)0x40089038 )
 USB Index register for selecting the endpoint status and control registers.
 
#define USB_CTRL   ( *(cc2538_reg_t*)0x4008903c )
 USB USB peripheral control register.
 
#define USB_MAXI   ( *(cc2538_reg_t*)0x40089040 )
 USB Indexed register:
 
#define USB_CS0_CSIL   ( *(cc2538_reg_t*)0x40089044 )
 USB Indexed register:
 
#define USB_CSIH   ( *(cc2538_reg_t*)0x40089048 )
 USB Indexed register:
 
#define USB_MAXO   ( *(cc2538_reg_t*)0x4008904c )
 USB Indexed register:
 
#define USB_CSOL   ( *(cc2538_reg_t*)0x40089050 )
 USB Indexed register:
 
#define USB_CSOH   ( *(cc2538_reg_t*)0x40089054 )
 USB Indexed register:
 
#define USB_CNT0_CNTL   ( *(cc2538_reg_t*)0x40089058 )
 USB Indexed register:
 
#define USB_CNTH   ( *(cc2538_reg_t*)0x4008905c )
 USB Indexed register:
 
#define USB_F0   ( *(cc2538_reg_t*)0x40089080 )
 USB Endpoint 0 FIFO.
 
#define USB_F1   ( *(cc2538_reg_t*)0x40089088 )
 USB IN/OUT endpoint 1 FIFO.
 
#define USB_F2   ( *(cc2538_reg_t*)0x40089090 )
 USB IN/OUT endpoint 2 FIFO.
 
#define USB_F3   ( *(cc2538_reg_t*)0x40089098 )
 USB IN/OUT endpoint 3 FIFO.
 
#define USB_F4   ( *(cc2538_reg_t*)0x400890a0 )
 USB IN/OUT endpoint 4 FIFO.
 
#define USB_F5   ( *(cc2538_reg_t*)0x400890a8 )
 USB IN/OUT endpoint 5 FIFO.
 
#define AES_DMAC_CH0_CTRL   ( *(cc2538_reg_t*)0x4008b000 )
 AES Channel control.
 
#define AES_DMAC_CH0_EXTADDR   ( *(cc2538_reg_t*)0x4008b004 )
 AES Channel external address.
 
#define AES_DMAC_CH0_DMALENGTH   ( *(cc2538_reg_t*)0x4008b00c )
 AES Channel DMA length.
 
#define AES_DMAC_STATUS   ( *(cc2538_reg_t*)0x4008b018 )
 AES DMAC status.
 
#define AES_DMAC_SWRES   ( *(cc2538_reg_t*)0x4008b01c )
 AES DMAC software reset register.
 
#define AES_DMAC_CH1_CTRL   ( *(cc2538_reg_t*)0x4008b020 )
 AES Channel control.
 
#define AES_DMAC_CH1_EXTADDR   ( *(cc2538_reg_t*)0x4008b024 )
 AES Channel external address.
 
#define AES_DMAC_CH1_DMALENGTH   ( *(cc2538_reg_t*)0x4008b02c )
 AES Channel DMA length.
 
#define AES_DMAC_MST_RUNPARAMS   ( *(cc2538_reg_t*)0x4008b078 )
 AES DMAC master run-time parameters.
 
#define AES_DMAC_PERSR   ( *(cc2538_reg_t*)0x4008b07c )
 AES DMAC port error raw status register.
 
#define AES_DMAC_OPTIONS   ( *(cc2538_reg_t*)0x4008b0f8 )
 AES DMAC options register.
 
#define AES_DMAC_VERSION   ( *(cc2538_reg_t*)0x4008b0fc )
 AES DMAC version register.
 
#define AES_KEY_STORE_WRITE_AREA   ( *(cc2538_reg_t*)0x4008b400 )
 AES Key store write area register.
 
#define AES_KEY_STORE_WRITTEN_AREA   ( *(cc2538_reg_t*)0x4008b404 )
 AES Key store written area register.
 
#define AES_KEY_STORE_SIZE   ( *(cc2538_reg_t*)0x4008b408 )
 AES Key store size register.
 
#define AES_KEY_STORE_READ_AREA   ( *(cc2538_reg_t*)0x4008b40c )
 AES Key store read area register.
 
#define AES_AES_KEY2_0   ( *(cc2538_reg_t*)0x4008b500 )
 AES_KEY2_0 / AES_GHASH_H_IN_0.
 
#define AES_AES_KEY2_1   ( *(cc2538_reg_t*)0x4008b504 )
 AES_KEY2_1 / AES_GHASH_H_IN_1.
 
#define AES_AES_KEY2_2   ( *(cc2538_reg_t*)0x4008b508 )
 AES_KEY2_2 / AES_GHASH_H_IN_2.
 
#define AES_AES_KEY2_3   ( *(cc2538_reg_t*)0x4008b50c )
 AES_KEY2_3 / AES_GHASH_H_IN_3.
 
#define AES_AES_KEY3_0   ( *(cc2538_reg_t*)0x4008b510 )
 AES_KEY3_0 / AES_KEY2_4.
 
#define AES_AES_KEY3_1   ( *(cc2538_reg_t*)0x4008b514 )
 AES_KEY3_1 / AES_KEY2_5.
 
#define AES_AES_KEY3_2   ( *(cc2538_reg_t*)0x4008b518 )
 AES_KEY3_2 / AES_KEY2_6.
 
#define AES_AES_KEY3_3   ( *(cc2538_reg_t*)0x4008b51c )
 AES_KEY3_3 / AES_KEY2_7.
 
#define AES_AES_IV_0   ( *(cc2538_reg_t*)0x4008b540 )
 AES initialization vector registers.
 
#define AES_AES_IV_1   ( *(cc2538_reg_t*)0x4008b544 )
 AES initialization vector registers.
 
#define AES_AES_IV_2   ( *(cc2538_reg_t*)0x4008b548 )
 AES initialization vector registers.
 
#define AES_AES_IV_3   ( *(cc2538_reg_t*)0x4008b54c )
 AES initialization vector registers.
 
#define AES_AES_CTRL   ( *(cc2538_reg_t*)0x4008b550 )
 AES input/output buffer control and mode register.
 
#define AES_AES_C_LENGTH_0   ( *(cc2538_reg_t*)0x4008b554 )
 AES crypto length registers (LSW)
 
#define AES_AES_C_LENGTH_1   ( *(cc2538_reg_t*)0x4008b558 )
 AES crypto length registers (MSW)
 
#define AES_AES_AUTH_LENGTH   ( *(cc2538_reg_t*)0x4008b55c )
 AES Authentication length register.
 
#define AES_AES_DATA_IN_OUT_0   ( *(cc2538_reg_t*)0x4008b560 )
 AES Data input/output registers.
 
#define AES_AES_DATA_IN_OUT_1   ( *(cc2538_reg_t*)0x4008b564 )
 AES Data Input/Output Registers.
 
#define AES_AES_DATA_IN_OUT_2   ( *(cc2538_reg_t*)0x4008b568 )
 AES Data Input/Output Registers.
 
#define AES_AES_DATA_IN_OUT_3   ( *(cc2538_reg_t*)0x4008b56c )
 AES Data Input/Output Registers.
 
#define AES_AES_TAG_OUT_0   ( *(cc2538_reg_t*)0x4008b570 )
 AES TAG register 0.
 
#define AES_AES_TAG_OUT_1   ( *(cc2538_reg_t*)0x4008b574 )
 AES TAG register 1.
 
#define AES_AES_TAG_OUT_2   ( *(cc2538_reg_t*)0x4008b578 )
 AES TAG register 2.
 
#define AES_AES_TAG_OUT_3   ( *(cc2538_reg_t*)0x4008b57c )
 AES TAG register 3.
 
#define AES_HASH_DATA_IN_0   ( *(cc2538_reg_t*)0x4008b600 )
 AES HASH data input register 0

 
#define AES_HASH_DATA_IN_1   ( *(cc2538_reg_t*)0x4008b604 )
 AES HASH data input register 1

 
#define AES_HASH_DATA_IN_2   ( *(cc2538_reg_t*)0x4008b608 )
 AES HASH data input register 2

 
#define AES_HASH_DATA_IN_3   ( *(cc2538_reg_t*)0x4008b60c )
 AES HASH data input register 3

 
#define AES_HASH_DATA_IN_4   ( *(cc2538_reg_t*)0x4008b610 )
 AES HASH data input register 4

 
#define AES_HASH_DATA_IN_5   ( *(cc2538_reg_t*)0x4008b614 )
 AES HASH data input register 5

 
#define AES_HASH_DATA_IN_6   ( *(cc2538_reg_t*)0x4008b618 )
 AES HASH data input register 6

 
#define AES_HASH_DATA_IN_7   ( *(cc2538_reg_t*)0x4008b61c )
 AES HASH data input register 7

 
#define AES_HASH_DATA_IN_8   ( *(cc2538_reg_t*)0x4008b620 )
 AES HASH data input register 8

 
#define AES_HASH_DATA_IN_9   ( *(cc2538_reg_t*)0x4008b624 )
 AES HASH data input register 9

 
#define AES_HASH_DATA_IN_10   ( *(cc2538_reg_t*)0x4008b628 )
 AES HASH data input register 10.
 
#define AES_HASH_DATA_IN_11   ( *(cc2538_reg_t*)0x4008b62c )
 AES HASH data input register 11.
 
#define AES_HASH_DATA_IN_12   ( *(cc2538_reg_t*)0x4008b630 )
 AES HASH data input register 12.
 
#define AES_HASH_DATA_IN_13   ( *(cc2538_reg_t*)0x4008b634 )
 AES HASH data input register 13.
 
#define AES_HASH_DATA_IN_14   ( *(cc2538_reg_t*)0x4008b638 )
 AES HASH data input register 14.
 
#define AES_HASH_DATA_IN_15   ( *(cc2538_reg_t*)0x4008b63c )
 AES HASH data input register 15.
 
#define AES_HASH_IO_BUF_CTRL   ( *(cc2538_reg_t*)0x4008b640 )
 AES Input/output buffer control and status register.
 
#define AES_HASH_MODE_IN   ( *(cc2538_reg_t*)0x4008b644 )
 AES Hash mode register.
 
#define AES_HASH_LENGTH_IN_L   ( *(cc2538_reg_t*)0x4008b648 )
 AES Hash length register.
 
#define AES_HASH_LENGTH_IN_H   ( *(cc2538_reg_t*)0x4008b64c )
 AES Hash length register.
 
#define AES_HASH_DIGEST_A   ( *(cc2538_reg_t*)0x4008b650 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_B   ( *(cc2538_reg_t*)0x4008b654 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_C   ( *(cc2538_reg_t*)0x4008b658 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_D   ( *(cc2538_reg_t*)0x4008b65c )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_E   ( *(cc2538_reg_t*)0x4008b660 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_F   ( *(cc2538_reg_t*)0x4008b664 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_G   ( *(cc2538_reg_t*)0x4008b668 )
 AES Hash digest registers.
 
#define AES_HASH_DIGEST_H   ( *(cc2538_reg_t*)0x4008b66c )
 AES Hash digest registers.
 
#define AES_CTRL_ALG_SEL   ( *(cc2538_reg_t*)0x4008b700 )
 AES Algorithm select.
 
#define AES_CTRL_PROT_EN   ( *(cc2538_reg_t*)0x4008b704 )
 AES Master PROT privileged access enable.
 
#define AES_CTRL_SW_RESET   ( *(cc2538_reg_t*)0x4008b740 )
 AES Software reset.
 
#define AES_CTRL_INT_CFG   ( *(cc2538_reg_t*)0x4008b780 )
 AES Interrupt configuration.
 
#define AES_CTRL_INT_EN   ( *(cc2538_reg_t*)0x4008b784 )
 AES Interrupt enable.
 
#define AES_CTRL_INT_CLR   ( *(cc2538_reg_t*)0x4008b788 )
 AES Interrupt clear.
 
#define AES_CTRL_INT_SET   ( *(cc2538_reg_t*)0x4008b78c )
 AES Interrupt set.
 
#define AES_CTRL_INT_STAT   ( *(cc2538_reg_t*)0x4008b790 )
 AES Interrupt status.
 
#define AES_CTRL_OPTIONS   ( *(cc2538_reg_t*)0x4008b7f8 )
 AES Options register.
 
#define AES_CTRL_VERSION   ( *(cc2538_reg_t*)0x4008b7fc )
 AES Version register.
 
#define SYS_CTRL_CLOCK_CTRL   ( *(cc2538_reg_t*)0x400d2000 )
 Clock control register.
 
#define SYS_CTRL_CLOCK_STA   ( *(cc2538_reg_t*)0x400d2004 )
 Clock status register.
 
#define SYS_CTRL_RCGCGPT   ( *(cc2538_reg_t*)0x400d2008 )
 Module clocks for GPT[3:0] when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCGPT   ( *(cc2538_reg_t*)0x400d200c )
 Module clocks for GPT[3:0] when the CPU is in sleep mode.
 
#define SYS_CTRL_DCGCGPT   ( *(cc2538_reg_t*)0x400d2010 )
 Module clocks for GPT[3:0] when the CPU is in PM0.
 
#define SYS_CTRL_SRGPT   ( *(cc2538_reg_t*)0x400d2014 )
 Reset for GPT[3:0].
 
#define SYS_CTRL_RCGCSSI   ( *(cc2538_reg_t*)0x400d2018 )
 Module clocks for SSI[1:0] when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCSSI   ( *(cc2538_reg_t*)0x400d201c )
 Module clocks for SSI[1:0] when the CPU is insSleep mode.
 
#define SYS_CTRL_DCGCSSI   ( *(cc2538_reg_t*)0x400d2020 )
 Module clocks for SSI[1:0] when the CPU is in PM0.
 
#define SYS_CTRL_SRSSI   ( *(cc2538_reg_t*)0x400d2024 )
 Reset for SSI[1:0].
 
#define SYS_CTRL_RCGCUART   ( *(cc2538_reg_t*)0x400d2028 )
 Module clocks for UART[1:0] when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCUART   ( *(cc2538_reg_t*)0x400d202c )
 Module clocks for UART[1:0] when the CPU is in sleep mode.
 
#define SYS_CTRL_DCGCUART   ( *(cc2538_reg_t*)0x400d2030 )
 Module clocks for UART[1:0] when the CPU is in PM0.
 
#define SYS_CTRL_SRUART   ( *(cc2538_reg_t*)0x400d2034 )
 Reset for UART[1:0].
 
#define SYS_CTRL_RCGCI2C   ( *(cc2538_reg_t*)0x400d2038 )
 Module clocks for I2C when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCI2C   ( *(cc2538_reg_t*)0x400d203c )
 Module clocks for I2C when the CPU is in sleep mode.
 
#define SYS_CTRL_DCGCI2C   ( *(cc2538_reg_t*)0x400d2040 )
 Module clocks for I2C when the CPU is in PM0.
 
#define SYS_CTRL_SRI2C   ( *(cc2538_reg_t*)0x400d2044 )
 Reset for I2C.
 
#define SYS_CTRL_RCGCSEC   ( *(cc2538_reg_t*)0x400d2048 )
 Module clocks for the security module when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCSEC   ( *(cc2538_reg_t*)0x400d204c )
 Module clocks for the security module when the CPU is in sleep mode.
 
#define SYS_CTRL_DCGCSEC   ( *(cc2538_reg_t*)0x400d2050 )
 Module clocks for the security module when the CPU is in PM0.
 
#define SYS_CTRL_SRSEC   ( *(cc2538_reg_t*)0x400d2054 )
 Reset for the security module.
 
#define SYS_CTRL_PMCTL   ( *(cc2538_reg_t*)0x400d2058 )
 Power mode.
 
#define SYS_CTRL_SRCRC   ( *(cc2538_reg_t*)0x400d205c )
 CRC on state retention.
 
#define SYS_CTRL_PWRDBG   ( *(cc2538_reg_t*)0x400d2074 )
 Power debug register.
 
#define SYS_CTRL_CLD   ( *(cc2538_reg_t*)0x400d2080 )
 This register controls the clock loss detection feature.
 
#define SYS_CTRL_IWE   ( *(cc2538_reg_t*)0x400d2094 )
 This register controls interrupt wake-up.
 
#define SYS_CTRL_I_MAP   ( *(cc2538_reg_t*)0x400d2098 )
 This register selects which interrupt map to be used.
 
#define SYS_CTRL_RCGCRFC   ( *(cc2538_reg_t*)0x400d20a8 )
 This register defines the module clocks for RF CORE when the CPU is in active (run) mode.
 
#define SYS_CTRL_SCGCRFC   ( *(cc2538_reg_t*)0x400d20ac )
 This register defines the module clocks for RF CORE when the CPU is in sleep mode.
 
#define SYS_CTRL_DCGCRFC   ( *(cc2538_reg_t*)0x400d20b0 )
 This register defines the module clocks for RF CORE when the CPU is in PM0.
 
#define SYS_CTRL_EMUOVR   ( *(cc2538_reg_t*)0x400d20b4 )
 This register defines the emulator override controls for power mode and peripheral clock gate.
 
#define FLASH_CTRL_FCTL   ( *(cc2538_reg_t*)0x400d3008 )
 Flash control.
 
#define FLASH_CTRL_FADDR   ( *(cc2538_reg_t*)0x400d300c )
 Flash address.
 
#define FLASH_CTRL_FWDATA   ( *(cc2538_reg_t*)0x400d3010 )
 Flash data.
 
#define FLASH_CTRL_DIECFG0   ( *(cc2538_reg_t*)0x400d3014 )
 Flash Die Configuration 0.
 
#define FLASH_CTRL_DIECFG1   ( *(cc2538_reg_t*)0x400d3018 )
 Flash Die Configuration 1.
 
#define FLASH_CTRL_DIECFG2   ( *(cc2538_reg_t*)0x400d301c )
 Flash Die Configuration 2.
 
#define IOC_PA0_SEL   ( *(cc2538_reg_t*)0x400d4000 )
 Peripheral select control for PA0.
 
#define IOC_PA1_SEL   ( *(cc2538_reg_t*)0x400d4004 )
 Peripheral select control for PA1.
 
#define IOC_PA2_SEL   ( *(cc2538_reg_t*)0x400d4008 )
 Peripheral select control for PA2.
 
#define IOC_PA3_SEL   ( *(cc2538_reg_t*)0x400d400c )
 Peripheral select control for PA3.
 
#define IOC_PA4_SEL   ( *(cc2538_reg_t*)0x400d4010 )
 Peripheral select control for PA4.
 
#define IOC_PA5_SEL   ( *(cc2538_reg_t*)0x400d4014 )
 Peripheral select control for PA5.
 
#define IOC_PA6_SEL   ( *(cc2538_reg_t*)0x400d4018 )
 Peripheral select control for PA6.
 
#define IOC_PA7_SEL   ( *(cc2538_reg_t*)0x400d401c )
 Peripheral select control for PA7.
 
#define IOC_PB0_SEL   ( *(cc2538_reg_t*)0x400d4020 )
 Peripheral select control for PB0.
 
#define IOC_PB1_SEL   ( *(cc2538_reg_t*)0x400d4024 )
 Peripheral select control for PB1.
 
#define IOC_PB2_SEL   ( *(cc2538_reg_t*)0x400d4028 )
 Peripheral select control for PB2.
 
#define IOC_PB3_SEL   ( *(cc2538_reg_t*)0x400d402c )
 Peripheral select control for PB3.
 
#define IOC_PB4_SEL   ( *(cc2538_reg_t*)0x400d4030 )
 Peripheral select control for PB4.
 
#define IOC_PB5_SEL   ( *(cc2538_reg_t*)0x400d4034 )
 Peripheral select control for PB5.
 
#define IOC_PB6_SEL   ( *(cc2538_reg_t*)0x400d4038 )
 Peripheral select control for PB6.
 
#define IOC_PB7_SEL   ( *(cc2538_reg_t*)0x400d403c )
 Peripheral select control for PB7.
 
#define IOC_PC0_SEL   ( *(cc2538_reg_t*)0x400d4040 )
 Peripheral select control for PC0.
 
#define IOC_PC1_SEL   ( *(cc2538_reg_t*)0x400d4044 )
 Peripheral select control for PC1.
 
#define IOC_PC2_SEL   ( *(cc2538_reg_t*)0x400d4048 )
 Peripheral select control for PC2.
 
#define IOC_PC3_SEL   ( *(cc2538_reg_t*)0x400d404c )
 Peripheral select control for PC3.
 
#define IOC_PC4_SEL   ( *(cc2538_reg_t*)0x400d4050 )
 Peripheral select control for PC4.
 
#define IOC_PC5_SEL   ( *(cc2538_reg_t*)0x400d4054 )
 Peripheral select control for PC5.
 
#define IOC_PC6_SEL   ( *(cc2538_reg_t*)0x400d4058 )
 Peripheral select control for PC6.
 
#define IOC_PC7_SEL   ( *(cc2538_reg_t*)0x400d405c )
 Peripheral select control for PC7.
 
#define IOC_PD0_SEL   ( *(cc2538_reg_t*)0x400d4060 )
 Peripheral select control for PD0.
 
#define IOC_PD1_SEL   ( *(cc2538_reg_t*)0x400d4064 )
 Peripheral select control for PD1.
 
#define IOC_PD2_SEL   ( *(cc2538_reg_t*)0x400d4068 )
 Peripheral select control for PD2.
 
#define IOC_PD3_SEL   ( *(cc2538_reg_t*)0x400d406c )
 Peripheral select control for PD3.
 
#define IOC_PD4_SEL   ( *(cc2538_reg_t*)0x400d4070 )
 Peripheral select control for PD4.
 
#define IOC_PD5_SEL   ( *(cc2538_reg_t*)0x400d4074 )
 Peripheral select control for PD5.
 
#define IOC_PD6_SEL   ( *(cc2538_reg_t*)0x400d4078 )
 Peripheral select control for PD6.
 
#define IOC_PD7_SEL   ( *(cc2538_reg_t*)0x400d407c )
 Peripheral select control for PD7.
 
#define IOC_PA0_OVER   ( *(cc2538_reg_t*)0x400d4080 )
 Override configuration register for PA0.
 
#define IOC_PA1_OVER   ( *(cc2538_reg_t*)0x400d4084 )
 Override configuration register for PA1.
 
#define IOC_PA2_OVER   ( *(cc2538_reg_t*)0x400d4088 )
 Override configuration register for PA2.
 
#define IOC_PA3_OVER   ( *(cc2538_reg_t*)0x400d408c )
 Override configuration register for PA3.
 
#define IOC_PA4_OVER   ( *(cc2538_reg_t*)0x400d4090 )
 Override configuration register for PA4.
 
#define IOC_PA5_OVER   ( *(cc2538_reg_t*)0x400d4094 )
 Override configuration register for PA5.
 
#define IOC_PA6_OVER   ( *(cc2538_reg_t*)0x400d4098 )
 Override configuration register for PA6.
 
#define IOC_PA7_OVER   ( *(cc2538_reg_t*)0x400d409c )
 Override configuration register for PA7.
 
#define IOC_PB0_OVER   ( *(cc2538_reg_t*)0x400d40a0 )
 Override configuration register for PB0.
 
#define IOC_PB1_OVER   ( *(cc2538_reg_t*)0x400d40a4 )
 Override configuration register for PB1.
 
#define IOC_PB2_OVER   ( *(cc2538_reg_t*)0x400d40a8 )
 Override configuration register for PB2.
 
#define IOC_PB3_OVER   ( *(cc2538_reg_t*)0x400d40ac )
 Override configuration register for PB3.
 
#define IOC_PB4_OVER   ( *(cc2538_reg_t*)0x400d40b0 )
 Override configuration register for PB4.
 
#define IOC_PB5_OVER   ( *(cc2538_reg_t*)0x400d40b4 )
 Override configuration register for PB5.
 
#define IOC_PB6_OVER   ( *(cc2538_reg_t*)0x400d40b8 )
 Override configuration register for PB6.
 
#define IOC_PB7_OVER   ( *(cc2538_reg_t*)0x400d40bc )
 Override configuration register for PB7.
 
#define IOC_PC0_OVER   ( *(cc2538_reg_t*)0x400d40c0 )
 Override configuration register for PC0.
 
#define IOC_PC1_OVER   ( *(cc2538_reg_t*)0x400d40c4 )
 Override configuration register for PC1.
 
#define IOC_PC2_OVER   ( *(cc2538_reg_t*)0x400d40c8 )
 Override configuration register for PC2.
 
#define IOC_PC3_OVER   ( *(cc2538_reg_t*)0x400d40cc )
 Override configuration register for PC3.
 
#define IOC_PC4_OVER   ( *(cc2538_reg_t*)0x400d40d0 )
 Override configuration register for PC4.
 
#define IOC_PC5_OVER   ( *(cc2538_reg_t*)0x400d40d4 )
 Override configuration register for PC5.
 
#define IOC_PC6_OVER   ( *(cc2538_reg_t*)0x400d40d8 )
 Override configuration register for PC6.
 
#define IOC_PC7_OVER   ( *(cc2538_reg_t*)0x400d40dc )
 Override configuration register for PC7.
 
#define IOC_PD0_OVER   ( *(cc2538_reg_t*)0x400d40e0 )
 Override configuration register for PD0.
 
#define IOC_PD1_OVER   ( *(cc2538_reg_t*)0x400d40e4 )
 Override configuration register for PD1.
 
#define IOC_PD2_OVER   ( *(cc2538_reg_t*)0x400d40e8 )
 Override configuration register for PD2.
 
#define IOC_PD3_OVER   ( *(cc2538_reg_t*)0x400d40ec )
 Override configuration register for PD3.
 
#define IOC_PD4_OVER   ( *(cc2538_reg_t*)0x400d40f0 )
 Override configuration register for PD4.
 
#define IOC_PD5_OVER   ( *(cc2538_reg_t*)0x400d40f4 )
 Override configuration register for PD5.
 
#define IOC_PD6_OVER   ( *(cc2538_reg_t*)0x400d40f8 )
 Override configuration register for PD6.
 
#define IOC_PD7_OVER   ( *(cc2538_reg_t*)0x400d40fc )
 Override configuration register for PD7.
 
#define IOC_UARTRXD_UART0   ( *(cc2538_reg_t*)0x400d4100 )
 Pin selection for UART0 RX.
 
#define IOC_UARTCTS_UART1   ( *(cc2538_reg_t*)0x400d4104 )
 Pin selection for UART1 CTS.
 
#define IOC_UARTRXD_UART1   ( *(cc2538_reg_t*)0x400d4108 )
 Pin selection for UART1 RX.
 
#define IOC_CLK_SSI_SSI0   ( *(cc2538_reg_t*)0x400d410c )
 Pin selection for SSI0 CLK.
 
#define IOC_SSIRXD_SSI0   ( *(cc2538_reg_t*)0x400d4110 )
 Pin selection for SSI0 RX.
 
#define IOC_SSIFSSIN_SSI0   ( *(cc2538_reg_t*)0x400d4114 )
 Pin selection for SSI0 FSSIN.
 
#define IOC_CLK_SSIIN_SSI0   ( *(cc2538_reg_t*)0x400d4118 )
 Pin selection for SSI0 CLK_SSIN.
 
#define IOC_CLK_SSI_SSI1   ( *(cc2538_reg_t*)0x400d411c )
 Pin selection for SSI1 CLK.
 
#define IOC_SSIRXD_SSI1   ( *(cc2538_reg_t*)0x400d4120 )
 Pin selection for SSI1 RX.
 
#define IOC_SSIFSSIN_SSI1   ( *(cc2538_reg_t*)0x400d4124 )
 Pin selection for SSI1 FSSIN.
 
#define IOC_CLK_SSIIN_SSI1   ( *(cc2538_reg_t*)0x400d4128 )
 Pin selection for SSI1 CLK_SSIN.
 
#define IOC_I2CMSSDA   ( *(cc2538_reg_t*)0x400d412c )
 Pin selection for I2C SDA.
 
#define IOC_I2CMSSCL   ( *(cc2538_reg_t*)0x400d4130 )
 Pin selection for I2C SCL.
 
#define IOC_GPT0OCP1   ( *(cc2538_reg_t*)0x400d4134 )
 Pin selection for GPT0OCP1.
 
#define IOC_GPT0OCP2   ( *(cc2538_reg_t*)0x400d4138 )
 Pin selection for GPT0OCP2.
 
#define IOC_GPT1OCP1   ( *(cc2538_reg_t*)0x400d413c )
 Pin selection for GPT1OCP1.
 
#define IOC_GPT1OCP2   ( *(cc2538_reg_t*)0x400d4140 )
 Pin selection for GPT1OCP2.
 
#define IOC_GPT2OCP1   ( *(cc2538_reg_t*)0x400d4144 )
 Pin selection for GPT2OCP1.
 
#define IOC_GPT2OCP2   ( *(cc2538_reg_t*)0x400d4148 )
 Pin selection for GPT2OCP2.
 
#define IOC_GPT3OCP1   ( *(cc2538_reg_t*)0x400d414c )
 Pin selection for GPT3OCP1.
 
#define IOC_GPT3OCP2   ( *(cc2538_reg_t*)0x400d4150 )
 Pin selection for GPT3OCP2.
 
#define SMWDTHROSC_WDCTL   ( *(cc2538_reg_t*)0x400d5000 )
 Watchdog Timer Control.
 
#define SMWDTHROSC_ST0   ( *(cc2538_reg_t*)0x400d5040 )
 Sleep Timer 0 count and compare.
 
#define SMWDTHROSC_ST1   ( *(cc2538_reg_t*)0x400d5044 )
 Sleep Timer 1 count and compare.
 
#define SMWDTHROSC_ST2   ( *(cc2538_reg_t*)0x400d5048 )
 Sleep Timer 2 count and compare.
 
#define SMWDTHROSC_ST3   ( *(cc2538_reg_t*)0x400d504c )
 Sleep Timer 3 count and compare.
 
#define SMWDTHROSC_STLOAD   ( *(cc2538_reg_t*)0x400d5050 )
 Sleep Timer load status.
 
#define SMWDTHROSC_STCC   ( *(cc2538_reg_t*)0x400d5054 )
 Sleep Timer Capture control.
 
#define SMWDTHROSC_STCS   ( *(cc2538_reg_t*)0x400d5058 )
 Sleep Timer Capture status.
 
#define SMWDTHROSC_STCV0   ( *(cc2538_reg_t*)0x400d505c )
 Sleep Timer Capture value byte 0.
 
#define SMWDTHROSC_STCV1   ( *(cc2538_reg_t*)0x400d5060 )
 Sleep Timer Capture value byte 1.
 
#define SMWDTHROSC_STCV2   ( *(cc2538_reg_t*)0x400d5064 )
 Sleep Timer Capture value byte 2.
 
#define SMWDTHROSC_STCV3   ( *(cc2538_reg_t*)0x400d5068 )
 Sleep Timer Capture value byte 3.
 
#define ANA_REGS_IVCTRL   ( *(cc2538_reg_t*)0x400d6004 )
 Analog control register.
 
#define GPIO_A_DATA   ( *(cc2538_reg_t*)0x400d9000 )
 GPIO_A Data Register.
 
#define GPIO_A_DIR   ( *(cc2538_reg_t*)0x400d9400 )
 GPIO_A data direction register.
 
#define GPIO_A_IS   ( *(cc2538_reg_t*)0x400d9404 )
 GPIO_A Interrupt Sense register.
 
#define GPIO_A_IBE   ( *(cc2538_reg_t*)0x400d9408 )
 GPIO_A Interrupt Both-Edges register.
 
#define GPIO_A_IEV   ( *(cc2538_reg_t*)0x400d940c )
 GPIO_A Interrupt Event Register.
 
#define GPIO_A_IE   ( *(cc2538_reg_t*)0x400d9410 )
 GPIO_A Interrupt mask register.
 
#define GPIO_A_RIS   ( *(cc2538_reg_t*)0x400d9414 )
 GPIO_A Raw Interrupt Status register.
 
#define GPIO_A_MIS   ( *(cc2538_reg_t*)0x400d9418 )
 GPIO_A Masked Interrupt Status register.
 
#define GPIO_A_IC   ( *(cc2538_reg_t*)0x400d941c )
 GPIO_A Interrupt Clear register.
 
#define GPIO_A_AFSEL   ( *(cc2538_reg_t*)0x400d9420 )
 GPIO_A Alternate Function / mode control select register.
 
#define GPIO_A_GPIOLOCK   ( *(cc2538_reg_t*)0x400d9520 )
 GPIO_A Lock register.
 
#define GPIO_A_GPIOCR   ( *(cc2538_reg_t*)0x400d9524 )
 GPIO_A Commit Register.
 
#define GPIO_A_PMUX   ( *(cc2538_reg_t*)0x400d9700 )
 GPIO_A The PMUX register.
 
#define GPIO_A_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400d9704 )
 GPIO_A The Port Edge Control register.
 
#define GPIO_A_PI_IEN   ( *(cc2538_reg_t*)0x400d9710 )
 GPIO_A The Power-up Interrupt Enable register.
 
#define GPIO_A_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400d9718 )
 GPIO_A IRQ Detect ACK register.
 
#define GPIO_A_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400d971c )
 GPIO_A IRQ Detect ACK for USB.
 
#define GPIO_A_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400d9720 )
 GPIO_A IRQ Detect ACK for masked interrupts.
 
#define GPIO_B_DATA   ( *(cc2538_reg_t*)0x400da000 )
 GPIO Data Register.
 
#define GPIO_B_DIR   ( *(cc2538_reg_t*)0x400da400 )
 GPIO_B data direction register.
 
#define GPIO_B_IS   ( *(cc2538_reg_t*)0x400da404 )
 GPIO_B Interrupt Sense register.
 
#define GPIO_B_IBE   ( *(cc2538_reg_t*)0x400da408 )
 GPIO_B Interrupt Both-Edges register.
 
#define GPIO_B_IEV   ( *(cc2538_reg_t*)0x400da40c )
 GPIO_B Interrupt Event Register.
 
#define GPIO_B_IE   ( *(cc2538_reg_t*)0x400da410 )
 GPIO_B Interrupt mask register.
 
#define GPIO_B_RIS   ( *(cc2538_reg_t*)0x400da414 )
 GPIO_B Raw Interrupt Status register.
 
#define GPIO_B_MIS   ( *(cc2538_reg_t*)0x400da418 )
 GPIO_B Masked Interrupt Status register.
 
#define GPIO_B_IC   ( *(cc2538_reg_t*)0x400da41c )
 GPIO_B Interrupt Clear register.
 
#define GPIO_B_AFSEL   ( *(cc2538_reg_t*)0x400da420 )
 GPIO_B Alternate Function / mode control select register.
 
#define GPIO_B_GPIOLOCK   ( *(cc2538_reg_t*)0x400da520 )
 GPIO_B Lock register.
 
#define GPIO_B_GPIOCR   ( *(cc2538_reg_t*)0x400da524 )
 GPIO_B Commit Register.
 
#define GPIO_B_PMUX   ( *(cc2538_reg_t*)0x400da700 )
 GPIO_B The PMUX register.
 
#define GPIO_B_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400da704 )
 GPIO_B The Port Edge Control register.
 
#define GPIO_B_PI_IEN   ( *(cc2538_reg_t*)0x400da710 )
 GPIO_B The Power-up Interrupt Enable register.
 
#define GPIO_B_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400da718 )
 GPIO_B IRQ Detect ACK register.
 
#define GPIO_B_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400da71c )
 GPIO_B IRQ Detect ACK for USB.
 
#define GPIO_B_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400da720 )
 GPIO_B IRQ Detect ACK for masked interrupts.
 
#define GPIO_C_DATA   ( *(cc2538_reg_t*)0x400db000 )
 GPIO_C Data Register.
 
#define GPIO_C_DIR   ( *(cc2538_reg_t*)0x400db400 )
 GPIO_C data direction register.
 
#define GPIO_C_IS   ( *(cc2538_reg_t*)0x400db404 )
 GPIO_C Interrupt Sense register.
 
#define GPIO_C_IBE   ( *(cc2538_reg_t*)0x400db408 )
 GPIO_C Interrupt Both-Edges register.
 
#define GPIO_C_IEV   ( *(cc2538_reg_t*)0x400db40c )
 GPIO_C Interrupt Event Register.
 
#define GPIO_C_IE   ( *(cc2538_reg_t*)0x400db410 )
 GPIO_C Interrupt mask register.
 
#define GPIO_C_RIS   ( *(cc2538_reg_t*)0x400db414 )
 GPIO_C Raw Interrupt Status register.
 
#define GPIO_C_MIS   ( *(cc2538_reg_t*)0x400db418 )
 GPIO_C Masked Interrupt Status register.
 
#define GPIO_C_IC   ( *(cc2538_reg_t*)0x400db41c )
 GPIO_C Interrupt Clear register.
 
#define GPIO_C_AFSEL   ( *(cc2538_reg_t*)0x400db420 )
 GPIO_C Alternate Function / mode control select register.
 
#define GPIO_C_GPIOLOCK   ( *(cc2538_reg_t*)0x400db520 )
 GPIO_C Lock register.
 
#define GPIO_C_GPIOCR   ( *(cc2538_reg_t*)0x400db524 )
 GPIO_C Commit Register.
 
#define GPIO_C_PMUX   ( *(cc2538_reg_t*)0x400db700 )
 GPIO_C The PMUX register.
 
#define GPIO_C_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400db704 )
 GPIO_C The Port Edge Control register.
 
#define GPIO_C_PI_IEN   ( *(cc2538_reg_t*)0x400db710 )
 GPIO_C The Power-up Interrupt Enable register.
 
#define GPIO_C_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400db718 )
 GPIO_C IRQ Detect ACK register.
 
#define GPIO_C_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400db71c )
 GPIO_C IRQ Detect ACK for USB.
 
#define GPIO_C_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400db720 )
 GPIO_C IRQ Detect ACK for masked interrupts.
 
#define GPIO_D_DATA   ( *(cc2538_reg_t*)0x400dc000 )
 GPIO_D Data Register.
 
#define GPIO_D_DIR   ( *(cc2538_reg_t*)0x400dc400 )
 GPIO_D data direction register.
 
#define GPIO_D_IS   ( *(cc2538_reg_t*)0x400dc404 )
 GPIO_D Interrupt Sense register.
 
#define GPIO_D_IBE   ( *(cc2538_reg_t*)0x400dc408 )
 GPIO_D Interrupt Both-Edges register.
 
#define GPIO_D_IEV   ( *(cc2538_reg_t*)0x400dc40c )
 GPIO_D Interrupt Event Register.
 
#define GPIO_D_IE   ( *(cc2538_reg_t*)0x400dc410 )
 GPIO_D Interrupt mask register.
 
#define GPIO_D_RIS   ( *(cc2538_reg_t*)0x400dc414 )
 GPIO_D Raw Interrupt Status register.
 
#define GPIO_D_MIS   ( *(cc2538_reg_t*)0x400dc418 )
 GPIO_D Masked Interrupt Status register.
 
#define GPIO_D_IC   ( *(cc2538_reg_t*)0x400dc41c )
 GPIO_D Interrupt Clear register.
 
#define GPIO_D_AFSEL   ( *(cc2538_reg_t*)0x400dc420 )
 GPIO_D Alternate Function / mode control select register.
 
#define GPIO_D_GPIOLOCK   ( *(cc2538_reg_t*)0x400dc520 )
 GPIO_D Lock register.
 
#define GPIO_D_GPIOCR   ( *(cc2538_reg_t*)0x400dc524 )
 GPIO_D Commit Register.
 
#define GPIO_D_PMUX   ( *(cc2538_reg_t*)0x400dc700 )
 GPIO_D The PMUX register.
 
#define GPIO_D_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400dc704 )
 GPIO_D The Port Edge Control register.
 
#define GPIO_D_PI_IEN   ( *(cc2538_reg_t*)0x400dc710 )
 GPIO_D The Power-up Interrupt Enable register.
 
#define GPIO_D_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400dc718 )
 GPIO_D IRQ Detect ACK register.
 
#define GPIO_D_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400dc71c )
 GPIO_D IRQ Detect ACK for USB.
 
#define GPIO_D_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400dc720 )
 GPIO_D IRQ Detect ACK for masked interrupts.
 
#define UDMA_STAT   ( *(cc2538_reg_t*)0x400ff000 )
 DMA status.
 
#define UDMA_CFG   ( *(cc2538_reg_t*)0x400ff004 )
 DMA configuration.
 
#define UDMA_CTLBASE   ( *(cc2538_reg_t*)0x400ff008 )
 DMA channel control base pointer.
 
#define UDMA_ALTBASE   ( *(cc2538_reg_t*)0x400ff00c )
 DMA alternate channel control base pointer.
 
#define UDMA_WAITSTAT   ( *(cc2538_reg_t*)0x400ff010 )
 DMA channel wait-on-request status.
 
#define UDMA_SWREQ   ( *(cc2538_reg_t*)0x400ff014 )
 DMA channel software request.
 
#define UDMA_USEBURSTSET   ( *(cc2538_reg_t*)0x400ff018 )
 DMA channel useburst set.
 
#define UDMA_USEBURSTCLR   ( *(cc2538_reg_t*)0x400ff01c )
 DMA channel useburst clear.
 
#define UDMA_REQMASKSET   ( *(cc2538_reg_t*)0x400ff020 )
 DMA channel request mask set.
 
#define UDMA_REQMASKCLR   ( *(cc2538_reg_t*)0x400ff024 )
 DMA channel request mask clear.
 
#define UDMA_ENASET   ( *(cc2538_reg_t*)0x400ff028 )
 DMA channel enable set.
 
#define UDMA_ENACLR   ( *(cc2538_reg_t*)0x400ff02c )
 DMA channel enable clear.
 
#define UDMA_ALTSET   ( *(cc2538_reg_t*)0x400ff030 )
 DMA channel primary alternate set.
 
#define UDMA_ALTCLR   ( *(cc2538_reg_t*)0x400ff034 )
 DMA channel primary alternate clear.
 
#define UDMA_PRIOSET   ( *(cc2538_reg_t*)0x400ff038 )
 DMA channel priority set.
 
#define UDMA_PRIOCLR   ( *(cc2538_reg_t*)0x400ff03c )
 DMA channel priority clear.
 
#define UDMA_ERRCLR   ( *(cc2538_reg_t*)0x400ff04c )
 DMA bus error clear.
 
#define UDMA_CHASGN   ( *(cc2538_reg_t*)0x400ff500 )
 DMA channel assignment.
 
#define UDMA_CHIS   ( *(cc2538_reg_t*)0x400ff504 )
 DMA channel interrupt status.
 
#define UDMA_CHMAP0   ( *(cc2538_reg_t*)0x400ff510 )
 DMA channel map select 0.
 
#define UDMA_CHMAP1   ( *(cc2538_reg_t*)0x400ff514 )
 DMA channel map select 1.
 
#define UDMA_CHMAP2   ( *(cc2538_reg_t*)0x400ff518 )
 DMA channel map select 2.
 
#define UDMA_CHMAP3   ( *(cc2538_reg_t*)0x400ff51c )
 DMA channel map select 3.
 
#define PKA_APTR   ( *(cc2538_reg_t*)0x44004000 )
 PKA vector A address.
 
#define PKA_BPTR   ( *(cc2538_reg_t*)0x44004004 )
 PKA vector B address.
 
#define PKA_CPTR   ( *(cc2538_reg_t*)0x44004008 )
 PKA vector C address.
 
#define PKA_DPTR   ( *(cc2538_reg_t*)0x4400400c )
 PKA vector D address.
 
#define PKA_ALENGTH   ( *(cc2538_reg_t*)0x44004010 )
 PKA vector A length.
 
#define PKA_BLENGTH   ( *(cc2538_reg_t*)0x44004014 )
 PKA vector B length.
 
#define PKA_SHIFT   ( *(cc2538_reg_t*)0x44004018 )
 PKA bit shift value.
 
#define PKA_FUNCTION   ( *(cc2538_reg_t*)0x4400401c )
 PKA function.
 
#define PKA_COMPARE   ( *(cc2538_reg_t*)0x44004020 )
 PKA compare result.
 
#define PKA_MSW   ( *(cc2538_reg_t*)0x44004024 )
 PKA most-significant-word of result vector.
 
#define PKA_DIVMSW   ( *(cc2538_reg_t*)0x44004028 )
 PKA most-significant-word of divide remainder.
 
#define PKA_SEQ_CTRL   ( *(cc2538_reg_t*)0x440040c8 )
 PKA sequencer control and status register.
 
#define PKA_OPTIONS   ( *(cc2538_reg_t*)0x440040f4 )
 PKA hardware options register.
 
#define PKA_SW_REV   ( *(cc2538_reg_t*)0x440040f8 )
 PKA firmware revision and capabilities register.
 
#define PKA_REVISION   ( *(cc2538_reg_t*)0x440040fc )
 PKA hardware revision register.
 
#define CCTEST_IO   ( *(cc2538_reg_t*)0x44010000 )
 Output strength control.
 
#define CCTEST_OBSSEL0   ( *(cc2538_reg_t*)0x44010014 )
 CCTEST Select output signal on observation output 0.
 
#define CCTEST_OBSSEL1   ( *(cc2538_reg_t*)0x44010018 )
 CCTEST Select output signal on observation output 1.
 
#define CCTEST_OBSSEL2   ( *(cc2538_reg_t*)0x4401001c )
 CCTEST Select output signal on observation output 2.
 
#define CCTEST_OBSSEL3   ( *(cc2538_reg_t*)0x44010020 )
 CCTEST Select output signal on observation output 3.
 
#define CCTEST_OBSSEL4   ( *(cc2538_reg_t*)0x44010024 )
 CCTEST Select output signal on observation output 4.
 
#define CCTEST_OBSSEL5   ( *(cc2538_reg_t*)0x44010028 )
 CCTEST Select output signal on observation output 5.
 
#define CCTEST_OBSSEL6   ( *(cc2538_reg_t*)0x4401002c )
 CCTEST Select output signal on observation output 6.
 
#define CCTEST_OBSSEL7   ( *(cc2538_reg_t*)0x44010030 )
 CCTEST Select output signal on observation output 7.
 
#define CCTEST_TR0   ( *(cc2538_reg_t*)0x44010034 )
 CCTEST Test register 0.
 
#define CCTEST_USBCTRL   ( *(cc2538_reg_t*)0x44010050 )
 CCTEST USB PHY stand-by control.
 
enum  IRQn {
  ResetHandler_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 ,
  BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = - 5 , DebugMonitor_IRQn = - 4 ,
  PendSV_IRQn = - 2 , SysTick_IRQn = - 1 , GPIO_PORT_A_IRQn = 0 , GPIO_PORT_B_IRQn = 1 ,
  GPIO_PORT_C_IRQn = 2 , GPIO_PORT_D_IRQn = 3 , UART0_IRQn = 5 , UART1_IRQn = 6 ,
  SSI0_IRQn = 7 , I2C_IRQn = 8 , ADC_IRQn = 14 , WDT_IRQn = 18 ,
  GPTIMER_0A_IRQn = 19 , GPTIMER_0B_IRQn = 20 , GPTIMER_1A_IRQn = 21 , GPTIMER_1B_IRQn = 22 ,
  GPTIMER_2A_IRQn = 23 , GPTIMER_2B_IRQn = 24 , ADC_CMP_IRQn = 25 , RF_RXTX_ALT_IRQn = 26 ,
  RF_ERR_ALT_IRQn = 27 , SYS_CTRL_IRQn = 28 , FLASH_CTRL_IRQn = 29 , AES_ALT_IRQn = 30 ,
  PKA_ALT_IRQn = 31 , SM_TIMER_ALT_IRQn = 32 , MAC_TIMER_ALT_IRQn = 33 , SSI1_IRQn = 34 ,
  GPTIMER_3A_IRQn = 35 , GPTIMER_3B_IRQn = 36 , UDMA_IRQn = 46 , UDMA_ERR_IRQn = 47 ,
  USB_IRQn = 140 , RF_RXTX_IRQn = 141 , RF_ERR_IRQn = 142 , AES_IRQn = 143 ,
  PKA_IRQn = 144 , SM_TIMER_IRQn = 145 , MACTIMER_IRQn = 146 , PERIPH_COUNT_IRQn = (MACTIMER_IRQn + 1)
}
 Interrupt Number Definition. More...
 
typedef enum IRQn IRQn_Type
 Interrupt Number Definition.
 

Cortex-M3 core interrupt handlers

void Reset_Handler (void)
 Reset handler.
 
void NMI_Handler (void)
 NMI handler.
 
void HardFault_Handler (void)
 Hard fault handler.
 
void MemManage_Handler (void)
 Memory management handler.
 
void BusFault_Handler (void)
 Bus fault handler.
 
void UsageFault_Handler (void)
 Usage fault handler.
 
void SVC_Handler (void)
 SVC handler.
 
void DebugMon_Handler (void)
 Debug monitor handler.
 
void PendSV_Handler (void)
 PendSV handler.
 
void SysTick_Handler (void)
 SysTick handler.
 

Macro Definition Documentation

◆ AES_AES_AUTH_LENGTH

#define AES_AES_AUTH_LENGTH   ( *(cc2538_reg_t*)0x4008b55c )

AES Authentication length register.

Definition at line 494 of file cc2538.h.

◆ AES_AES_C_LENGTH_0

#define AES_AES_C_LENGTH_0   ( *(cc2538_reg_t*)0x4008b554 )

AES crypto length registers (LSW)

Definition at line 492 of file cc2538.h.

◆ AES_AES_C_LENGTH_1

#define AES_AES_C_LENGTH_1   ( *(cc2538_reg_t*)0x4008b558 )

AES crypto length registers (MSW)

Definition at line 493 of file cc2538.h.

◆ AES_AES_CTRL

#define AES_AES_CTRL   ( *(cc2538_reg_t*)0x4008b550 )

AES input/output buffer control and mode register.

Definition at line 491 of file cc2538.h.

◆ AES_AES_DATA_IN_OUT_0

#define AES_AES_DATA_IN_OUT_0   ( *(cc2538_reg_t*)0x4008b560 )

AES Data input/output registers.

Definition at line 495 of file cc2538.h.

◆ AES_AES_DATA_IN_OUT_1

#define AES_AES_DATA_IN_OUT_1   ( *(cc2538_reg_t*)0x4008b564 )

AES Data Input/Output Registers.

Definition at line 496 of file cc2538.h.

◆ AES_AES_DATA_IN_OUT_2

#define AES_AES_DATA_IN_OUT_2   ( *(cc2538_reg_t*)0x4008b568 )

AES Data Input/Output Registers.

Definition at line 497 of file cc2538.h.

◆ AES_AES_DATA_IN_OUT_3

#define AES_AES_DATA_IN_OUT_3   ( *(cc2538_reg_t*)0x4008b56c )

AES Data Input/Output Registers.

Definition at line 498 of file cc2538.h.

◆ AES_AES_IV_0

#define AES_AES_IV_0   ( *(cc2538_reg_t*)0x4008b540 )

AES initialization vector registers.

Definition at line 487 of file cc2538.h.

◆ AES_AES_IV_1

#define AES_AES_IV_1   ( *(cc2538_reg_t*)0x4008b544 )

AES initialization vector registers.

Definition at line 488 of file cc2538.h.

◆ AES_AES_IV_2

#define AES_AES_IV_2   ( *(cc2538_reg_t*)0x4008b548 )

AES initialization vector registers.

Definition at line 489 of file cc2538.h.

◆ AES_AES_IV_3

#define AES_AES_IV_3   ( *(cc2538_reg_t*)0x4008b54c )

AES initialization vector registers.

Definition at line 490 of file cc2538.h.

◆ AES_AES_KEY2_0

#define AES_AES_KEY2_0   ( *(cc2538_reg_t*)0x4008b500 )

AES_KEY2_0 / AES_GHASH_H_IN_0.

Definition at line 479 of file cc2538.h.

◆ AES_AES_KEY2_1

#define AES_AES_KEY2_1   ( *(cc2538_reg_t*)0x4008b504 )

AES_KEY2_1 / AES_GHASH_H_IN_1.

Definition at line 480 of file cc2538.h.

◆ AES_AES_KEY2_2

#define AES_AES_KEY2_2   ( *(cc2538_reg_t*)0x4008b508 )

AES_KEY2_2 / AES_GHASH_H_IN_2.

Definition at line 481 of file cc2538.h.

◆ AES_AES_KEY2_3

#define AES_AES_KEY2_3   ( *(cc2538_reg_t*)0x4008b50c )

AES_KEY2_3 / AES_GHASH_H_IN_3.

Definition at line 482 of file cc2538.h.

◆ AES_AES_KEY3_0

#define AES_AES_KEY3_0   ( *(cc2538_reg_t*)0x4008b510 )

AES_KEY3_0 / AES_KEY2_4.

Definition at line 483 of file cc2538.h.

◆ AES_AES_KEY3_1

#define AES_AES_KEY3_1   ( *(cc2538_reg_t*)0x4008b514 )

AES_KEY3_1 / AES_KEY2_5.

Definition at line 484 of file cc2538.h.

◆ AES_AES_KEY3_2

#define AES_AES_KEY3_2   ( *(cc2538_reg_t*)0x4008b518 )

AES_KEY3_2 / AES_KEY2_6.

Definition at line 485 of file cc2538.h.

◆ AES_AES_KEY3_3

#define AES_AES_KEY3_3   ( *(cc2538_reg_t*)0x4008b51c )

AES_KEY3_3 / AES_KEY2_7.

Definition at line 486 of file cc2538.h.

◆ AES_AES_TAG_OUT_0

#define AES_AES_TAG_OUT_0   ( *(cc2538_reg_t*)0x4008b570 )

AES TAG register 0.

Definition at line 499 of file cc2538.h.

◆ AES_AES_TAG_OUT_1

#define AES_AES_TAG_OUT_1   ( *(cc2538_reg_t*)0x4008b574 )

AES TAG register 1.

Definition at line 500 of file cc2538.h.

◆ AES_AES_TAG_OUT_2

#define AES_AES_TAG_OUT_2   ( *(cc2538_reg_t*)0x4008b578 )

AES TAG register 2.

Definition at line 501 of file cc2538.h.

◆ AES_AES_TAG_OUT_3

#define AES_AES_TAG_OUT_3   ( *(cc2538_reg_t*)0x4008b57c )

AES TAG register 3.

Definition at line 502 of file cc2538.h.

◆ AES_CTRL_ALG_SEL

#define AES_CTRL_ALG_SEL   ( *(cc2538_reg_t*)0x4008b700 )

AES Algorithm select.

Definition at line 531 of file cc2538.h.

◆ AES_CTRL_INT_CFG

#define AES_CTRL_INT_CFG   ( *(cc2538_reg_t*)0x4008b780 )

AES Interrupt configuration.

Definition at line 534 of file cc2538.h.

◆ AES_CTRL_INT_CLR

#define AES_CTRL_INT_CLR   ( *(cc2538_reg_t*)0x4008b788 )

AES Interrupt clear.

Definition at line 536 of file cc2538.h.

◆ AES_CTRL_INT_EN

#define AES_CTRL_INT_EN   ( *(cc2538_reg_t*)0x4008b784 )

AES Interrupt enable.

Definition at line 535 of file cc2538.h.

◆ AES_CTRL_INT_SET

#define AES_CTRL_INT_SET   ( *(cc2538_reg_t*)0x4008b78c )

AES Interrupt set.

Definition at line 537 of file cc2538.h.

◆ AES_CTRL_INT_STAT

#define AES_CTRL_INT_STAT   ( *(cc2538_reg_t*)0x4008b790 )

AES Interrupt status.

Definition at line 538 of file cc2538.h.

◆ AES_CTRL_OPTIONS

#define AES_CTRL_OPTIONS   ( *(cc2538_reg_t*)0x4008b7f8 )

AES Options register.

Definition at line 539 of file cc2538.h.

◆ AES_CTRL_PROT_EN

#define AES_CTRL_PROT_EN   ( *(cc2538_reg_t*)0x4008b704 )

AES Master PROT privileged access enable.

Definition at line 532 of file cc2538.h.

◆ AES_CTRL_SW_RESET

#define AES_CTRL_SW_RESET   ( *(cc2538_reg_t*)0x4008b740 )

AES Software reset.

Definition at line 533 of file cc2538.h.

◆ AES_CTRL_VERSION

#define AES_CTRL_VERSION   ( *(cc2538_reg_t*)0x4008b7fc )

AES Version register.

Definition at line 540 of file cc2538.h.

◆ AES_DMAC_CH0_CTRL

#define AES_DMAC_CH0_CTRL   ( *(cc2538_reg_t*)0x4008b000 )

AES Channel control.

Definition at line 463 of file cc2538.h.

◆ AES_DMAC_CH0_DMALENGTH

#define AES_DMAC_CH0_DMALENGTH   ( *(cc2538_reg_t*)0x4008b00c )

AES Channel DMA length.

Definition at line 465 of file cc2538.h.

◆ AES_DMAC_CH0_EXTADDR

#define AES_DMAC_CH0_EXTADDR   ( *(cc2538_reg_t*)0x4008b004 )

AES Channel external address.

Definition at line 464 of file cc2538.h.

◆ AES_DMAC_CH1_CTRL

#define AES_DMAC_CH1_CTRL   ( *(cc2538_reg_t*)0x4008b020 )

AES Channel control.

Definition at line 468 of file cc2538.h.

◆ AES_DMAC_CH1_DMALENGTH

#define AES_DMAC_CH1_DMALENGTH   ( *(cc2538_reg_t*)0x4008b02c )

AES Channel DMA length.

Definition at line 470 of file cc2538.h.

◆ AES_DMAC_CH1_EXTADDR

#define AES_DMAC_CH1_EXTADDR   ( *(cc2538_reg_t*)0x4008b024 )

AES Channel external address.

Definition at line 469 of file cc2538.h.

◆ AES_DMAC_MST_RUNPARAMS

#define AES_DMAC_MST_RUNPARAMS   ( *(cc2538_reg_t*)0x4008b078 )

AES DMAC master run-time parameters.

Definition at line 471 of file cc2538.h.

◆ AES_DMAC_OPTIONS

#define AES_DMAC_OPTIONS   ( *(cc2538_reg_t*)0x4008b0f8 )

AES DMAC options register.

Definition at line 473 of file cc2538.h.

◆ AES_DMAC_PERSR

#define AES_DMAC_PERSR   ( *(cc2538_reg_t*)0x4008b07c )

AES DMAC port error raw status register.

Definition at line 472 of file cc2538.h.

◆ AES_DMAC_STATUS

#define AES_DMAC_STATUS   ( *(cc2538_reg_t*)0x4008b018 )

AES DMAC status.

Definition at line 466 of file cc2538.h.

◆ AES_DMAC_SWRES

#define AES_DMAC_SWRES   ( *(cc2538_reg_t*)0x4008b01c )

AES DMAC software reset register.

Definition at line 467 of file cc2538.h.

◆ AES_DMAC_VERSION

#define AES_DMAC_VERSION   ( *(cc2538_reg_t*)0x4008b0fc )

AES DMAC version register.

Definition at line 474 of file cc2538.h.

◆ AES_HASH_DATA_IN_0

#define AES_HASH_DATA_IN_0   ( *(cc2538_reg_t*)0x4008b600 )

AES HASH data input register 0

Definition at line 503 of file cc2538.h.

◆ AES_HASH_DATA_IN_1

#define AES_HASH_DATA_IN_1   ( *(cc2538_reg_t*)0x4008b604 )

AES HASH data input register 1

Definition at line 504 of file cc2538.h.

◆ AES_HASH_DATA_IN_10

#define AES_HASH_DATA_IN_10   ( *(cc2538_reg_t*)0x4008b628 )

AES HASH data input register 10.

Definition at line 513 of file cc2538.h.

◆ AES_HASH_DATA_IN_11

#define AES_HASH_DATA_IN_11   ( *(cc2538_reg_t*)0x4008b62c )

AES HASH data input register 11.

Definition at line 514 of file cc2538.h.

◆ AES_HASH_DATA_IN_12

#define AES_HASH_DATA_IN_12   ( *(cc2538_reg_t*)0x4008b630 )

AES HASH data input register 12.

Definition at line 515 of file cc2538.h.

◆ AES_HASH_DATA_IN_13

#define AES_HASH_DATA_IN_13   ( *(cc2538_reg_t*)0x4008b634 )

AES HASH data input register 13.

Definition at line 516 of file cc2538.h.

◆ AES_HASH_DATA_IN_14

#define AES_HASH_DATA_IN_14   ( *(cc2538_reg_t*)0x4008b638 )

AES HASH data input register 14.

Definition at line 517 of file cc2538.h.

◆ AES_HASH_DATA_IN_15

#define AES_HASH_DATA_IN_15   ( *(cc2538_reg_t*)0x4008b63c )

AES HASH data input register 15.

Definition at line 518 of file cc2538.h.

◆ AES_HASH_DATA_IN_2

#define AES_HASH_DATA_IN_2   ( *(cc2538_reg_t*)0x4008b608 )

AES HASH data input register 2

Definition at line 505 of file cc2538.h.

◆ AES_HASH_DATA_IN_3

#define AES_HASH_DATA_IN_3   ( *(cc2538_reg_t*)0x4008b60c )

AES HASH data input register 3

Definition at line 506 of file cc2538.h.

◆ AES_HASH_DATA_IN_4

#define AES_HASH_DATA_IN_4   ( *(cc2538_reg_t*)0x4008b610 )

AES HASH data input register 4

Definition at line 507 of file cc2538.h.

◆ AES_HASH_DATA_IN_5

#define AES_HASH_DATA_IN_5   ( *(cc2538_reg_t*)0x4008b614 )

AES HASH data input register 5

Definition at line 508 of file cc2538.h.

◆ AES_HASH_DATA_IN_6

#define AES_HASH_DATA_IN_6   ( *(cc2538_reg_t*)0x4008b618 )

AES HASH data input register 6

Definition at line 509 of file cc2538.h.

◆ AES_HASH_DATA_IN_7

#define AES_HASH_DATA_IN_7   ( *(cc2538_reg_t*)0x4008b61c )

AES HASH data input register 7

Definition at line 510 of file cc2538.h.

◆ AES_HASH_DATA_IN_8

#define AES_HASH_DATA_IN_8   ( *(cc2538_reg_t*)0x4008b620 )

AES HASH data input register 8

Definition at line 511 of file cc2538.h.

◆ AES_HASH_DATA_IN_9

#define AES_HASH_DATA_IN_9   ( *(cc2538_reg_t*)0x4008b624 )

AES HASH data input register 9

Definition at line 512 of file cc2538.h.

◆ AES_HASH_DIGEST_A

#define AES_HASH_DIGEST_A   ( *(cc2538_reg_t*)0x4008b650 )

AES Hash digest registers.

Definition at line 523 of file cc2538.h.

◆ AES_HASH_DIGEST_B

#define AES_HASH_DIGEST_B   ( *(cc2538_reg_t*)0x4008b654 )

AES Hash digest registers.

Definition at line 524 of file cc2538.h.

◆ AES_HASH_DIGEST_C

#define AES_HASH_DIGEST_C   ( *(cc2538_reg_t*)0x4008b658 )

AES Hash digest registers.

Definition at line 525 of file cc2538.h.

◆ AES_HASH_DIGEST_D

#define AES_HASH_DIGEST_D   ( *(cc2538_reg_t*)0x4008b65c )

AES Hash digest registers.

Definition at line 526 of file cc2538.h.

◆ AES_HASH_DIGEST_E

#define AES_HASH_DIGEST_E   ( *(cc2538_reg_t*)0x4008b660 )

AES Hash digest registers.

Definition at line 527 of file cc2538.h.

◆ AES_HASH_DIGEST_F

#define AES_HASH_DIGEST_F   ( *(cc2538_reg_t*)0x4008b664 )

AES Hash digest registers.

Definition at line 528 of file cc2538.h.

◆ AES_HASH_DIGEST_G

#define AES_HASH_DIGEST_G   ( *(cc2538_reg_t*)0x4008b668 )

AES Hash digest registers.

Definition at line 529 of file cc2538.h.

◆ AES_HASH_DIGEST_H

#define AES_HASH_DIGEST_H   ( *(cc2538_reg_t*)0x4008b66c )

AES Hash digest registers.

Definition at line 530 of file cc2538.h.

◆ AES_HASH_IO_BUF_CTRL

#define AES_HASH_IO_BUF_CTRL   ( *(cc2538_reg_t*)0x4008b640 )

AES Input/output buffer control and status register.

Definition at line 519 of file cc2538.h.

◆ AES_HASH_LENGTH_IN_H

#define AES_HASH_LENGTH_IN_H   ( *(cc2538_reg_t*)0x4008b64c )

AES Hash length register.

Definition at line 522 of file cc2538.h.

◆ AES_HASH_LENGTH_IN_L

#define AES_HASH_LENGTH_IN_L   ( *(cc2538_reg_t*)0x4008b648 )

AES Hash length register.

Definition at line 521 of file cc2538.h.

◆ AES_HASH_MODE_IN

#define AES_HASH_MODE_IN   ( *(cc2538_reg_t*)0x4008b644 )

AES Hash mode register.

Definition at line 520 of file cc2538.h.

◆ AES_KEY_STORE_READ_AREA

#define AES_KEY_STORE_READ_AREA   ( *(cc2538_reg_t*)0x4008b40c )

AES Key store read area register.

Definition at line 478 of file cc2538.h.

◆ AES_KEY_STORE_SIZE

#define AES_KEY_STORE_SIZE   ( *(cc2538_reg_t*)0x4008b408 )

AES Key store size register.

Definition at line 477 of file cc2538.h.

◆ AES_KEY_STORE_WRITE_AREA

#define AES_KEY_STORE_WRITE_AREA   ( *(cc2538_reg_t*)0x4008b400 )

AES Key store write area register.

Definition at line 475 of file cc2538.h.

◆ AES_KEY_STORE_WRITTEN_AREA

#define AES_KEY_STORE_WRITTEN_AREA   ( *(cc2538_reg_t*)0x4008b404 )

AES Key store written area register.

Definition at line 476 of file cc2538.h.

◆ ANA_REGS_IVCTRL

#define ANA_REGS_IVCTRL   ( *(cc2538_reg_t*)0x400d6004 )

Analog control register.

Definition at line 676 of file cc2538.h.

◆ CC2538_VTOR_ALIGN

#define CC2538_VTOR_ALIGN   512

CC2538 Vector Table alignment.

Definition at line 806 of file cc2538.h.

◆ CCTEST_IO

#define CCTEST_IO   ( *(cc2538_reg_t*)0x44010000 )

Output strength control.

Definition at line 787 of file cc2538.h.

◆ CCTEST_OBSSEL0

#define CCTEST_OBSSEL0   ( *(cc2538_reg_t*)0x44010014 )

CCTEST Select output signal on observation output 0.

Definition at line 788 of file cc2538.h.

◆ CCTEST_OBSSEL1

#define CCTEST_OBSSEL1   ( *(cc2538_reg_t*)0x44010018 )

CCTEST Select output signal on observation output 1.

Definition at line 789 of file cc2538.h.

◆ CCTEST_OBSSEL2

#define CCTEST_OBSSEL2   ( *(cc2538_reg_t*)0x4401001c )

CCTEST Select output signal on observation output 2.

Definition at line 790 of file cc2538.h.

◆ CCTEST_OBSSEL3

#define CCTEST_OBSSEL3   ( *(cc2538_reg_t*)0x44010020 )

CCTEST Select output signal on observation output 3.

Definition at line 791 of file cc2538.h.

◆ CCTEST_OBSSEL4

#define CCTEST_OBSSEL4   ( *(cc2538_reg_t*)0x44010024 )

CCTEST Select output signal on observation output 4.

Definition at line 792 of file cc2538.h.

◆ CCTEST_OBSSEL5

#define CCTEST_OBSSEL5   ( *(cc2538_reg_t*)0x44010028 )

CCTEST Select output signal on observation output 5.

Definition at line 793 of file cc2538.h.

◆ CCTEST_OBSSEL6

#define CCTEST_OBSSEL6   ( *(cc2538_reg_t*)0x4401002c )

CCTEST Select output signal on observation output 6.

Definition at line 794 of file cc2538.h.

◆ CCTEST_OBSSEL7

#define CCTEST_OBSSEL7   ( *(cc2538_reg_t*)0x44010030 )

CCTEST Select output signal on observation output 7.

Definition at line 795 of file cc2538.h.

◆ CCTEST_TR0

#define CCTEST_TR0   ( *(cc2538_reg_t*)0x44010034 )

CCTEST Test register 0.

Definition at line 796 of file cc2538.h.

◆ CCTEST_USBCTRL

#define CCTEST_USBCTRL   ( *(cc2538_reg_t*)0x44010050 )

CCTEST USB PHY stand-by control.

Definition at line 797 of file cc2538.h.

◆ FLASH_CTRL_DIECFG0

#define FLASH_CTRL_DIECFG0   ( *(cc2538_reg_t*)0x400d3014 )

Flash Die Configuration 0.

Definition at line 576 of file cc2538.h.

◆ FLASH_CTRL_DIECFG1

#define FLASH_CTRL_DIECFG1   ( *(cc2538_reg_t*)0x400d3018 )

Flash Die Configuration 1.

Definition at line 577 of file cc2538.h.

◆ FLASH_CTRL_DIECFG2

#define FLASH_CTRL_DIECFG2   ( *(cc2538_reg_t*)0x400d301c )

Flash Die Configuration 2.

Definition at line 578 of file cc2538.h.

◆ FLASH_CTRL_FADDR

#define FLASH_CTRL_FADDR   ( *(cc2538_reg_t*)0x400d300c )

Flash address.

Definition at line 574 of file cc2538.h.

◆ FLASH_CTRL_FCTL

#define FLASH_CTRL_FCTL   ( *(cc2538_reg_t*)0x400d3008 )

Flash control.

Definition at line 573 of file cc2538.h.

◆ FLASH_CTRL_FWDATA

#define FLASH_CTRL_FWDATA   ( *(cc2538_reg_t*)0x400d3010 )

Flash data.

Definition at line 575 of file cc2538.h.

◆ GPIO_A_AFSEL

#define GPIO_A_AFSEL   ( *(cc2538_reg_t*)0x400d9420 )

GPIO_A Alternate Function / mode control select register.

Definition at line 686 of file cc2538.h.

◆ GPIO_A_DATA

#define GPIO_A_DATA   ( *(cc2538_reg_t*)0x400d9000 )

GPIO_A Data Register.

Definition at line 677 of file cc2538.h.

◆ GPIO_A_DIR

#define GPIO_A_DIR   ( *(cc2538_reg_t*)0x400d9400 )

GPIO_A data direction register.

Definition at line 678 of file cc2538.h.

◆ GPIO_A_GPIOCR

#define GPIO_A_GPIOCR   ( *(cc2538_reg_t*)0x400d9524 )

GPIO_A Commit Register.

Definition at line 688 of file cc2538.h.

◆ GPIO_A_GPIOLOCK

#define GPIO_A_GPIOLOCK   ( *(cc2538_reg_t*)0x400d9520 )

GPIO_A Lock register.

Definition at line 687 of file cc2538.h.

◆ GPIO_A_IBE

#define GPIO_A_IBE   ( *(cc2538_reg_t*)0x400d9408 )

GPIO_A Interrupt Both-Edges register.

Definition at line 680 of file cc2538.h.

◆ GPIO_A_IC

#define GPIO_A_IC   ( *(cc2538_reg_t*)0x400d941c )

GPIO_A Interrupt Clear register.

Definition at line 685 of file cc2538.h.

◆ GPIO_A_IE

#define GPIO_A_IE   ( *(cc2538_reg_t*)0x400d9410 )

GPIO_A Interrupt mask register.

Definition at line 682 of file cc2538.h.

◆ GPIO_A_IEV

#define GPIO_A_IEV   ( *(cc2538_reg_t*)0x400d940c )

GPIO_A Interrupt Event Register.

Definition at line 681 of file cc2538.h.

◆ GPIO_A_IRQ_DETECT_ACK

#define GPIO_A_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400d9718 )

GPIO_A IRQ Detect ACK register.

Definition at line 692 of file cc2538.h.

◆ GPIO_A_IRQ_DETECT_UNMASK

#define GPIO_A_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400d9720 )

GPIO_A IRQ Detect ACK for masked interrupts.

Definition at line 694 of file cc2538.h.

◆ GPIO_A_IS

#define GPIO_A_IS   ( *(cc2538_reg_t*)0x400d9404 )

GPIO_A Interrupt Sense register.

Definition at line 679 of file cc2538.h.

◆ GPIO_A_MIS

#define GPIO_A_MIS   ( *(cc2538_reg_t*)0x400d9418 )

GPIO_A Masked Interrupt Status register.

Definition at line 684 of file cc2538.h.

◆ GPIO_A_P_EDGE_CTRL

#define GPIO_A_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400d9704 )

GPIO_A The Port Edge Control register.

Definition at line 690 of file cc2538.h.

◆ GPIO_A_PI_IEN

#define GPIO_A_PI_IEN   ( *(cc2538_reg_t*)0x400d9710 )

GPIO_A The Power-up Interrupt Enable register.

Definition at line 691 of file cc2538.h.

◆ GPIO_A_PMUX

#define GPIO_A_PMUX   ( *(cc2538_reg_t*)0x400d9700 )

GPIO_A The PMUX register.

Definition at line 689 of file cc2538.h.

◆ GPIO_A_RIS

#define GPIO_A_RIS   ( *(cc2538_reg_t*)0x400d9414 )

GPIO_A Raw Interrupt Status register.

Definition at line 683 of file cc2538.h.

◆ GPIO_A_USB_IRQ_ACK

#define GPIO_A_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400d971c )

GPIO_A IRQ Detect ACK for USB.

Definition at line 693 of file cc2538.h.

◆ GPIO_B_AFSEL

#define GPIO_B_AFSEL   ( *(cc2538_reg_t*)0x400da420 )

GPIO_B Alternate Function / mode control select register.

Definition at line 704 of file cc2538.h.

◆ GPIO_B_DATA

#define GPIO_B_DATA   ( *(cc2538_reg_t*)0x400da000 )

GPIO Data Register.

Definition at line 695 of file cc2538.h.

◆ GPIO_B_DIR

#define GPIO_B_DIR   ( *(cc2538_reg_t*)0x400da400 )

GPIO_B data direction register.

Definition at line 696 of file cc2538.h.

◆ GPIO_B_GPIOCR

#define GPIO_B_GPIOCR   ( *(cc2538_reg_t*)0x400da524 )

GPIO_B Commit Register.

Definition at line 706 of file cc2538.h.

◆ GPIO_B_GPIOLOCK

#define GPIO_B_GPIOLOCK   ( *(cc2538_reg_t*)0x400da520 )

GPIO_B Lock register.

Definition at line 705 of file cc2538.h.

◆ GPIO_B_IBE

#define GPIO_B_IBE   ( *(cc2538_reg_t*)0x400da408 )

GPIO_B Interrupt Both-Edges register.

Definition at line 698 of file cc2538.h.

◆ GPIO_B_IC

#define GPIO_B_IC   ( *(cc2538_reg_t*)0x400da41c )

GPIO_B Interrupt Clear register.

Definition at line 703 of file cc2538.h.

◆ GPIO_B_IE

#define GPIO_B_IE   ( *(cc2538_reg_t*)0x400da410 )

GPIO_B Interrupt mask register.

Definition at line 700 of file cc2538.h.

◆ GPIO_B_IEV

#define GPIO_B_IEV   ( *(cc2538_reg_t*)0x400da40c )

GPIO_B Interrupt Event Register.

Definition at line 699 of file cc2538.h.

◆ GPIO_B_IRQ_DETECT_ACK

#define GPIO_B_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400da718 )

GPIO_B IRQ Detect ACK register.

Definition at line 710 of file cc2538.h.

◆ GPIO_B_IRQ_DETECT_UNMASK

#define GPIO_B_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400da720 )

GPIO_B IRQ Detect ACK for masked interrupts.

Definition at line 712 of file cc2538.h.

◆ GPIO_B_IS

#define GPIO_B_IS   ( *(cc2538_reg_t*)0x400da404 )

GPIO_B Interrupt Sense register.

Definition at line 697 of file cc2538.h.

◆ GPIO_B_MIS

#define GPIO_B_MIS   ( *(cc2538_reg_t*)0x400da418 )

GPIO_B Masked Interrupt Status register.

Definition at line 702 of file cc2538.h.

◆ GPIO_B_P_EDGE_CTRL

#define GPIO_B_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400da704 )

GPIO_B The Port Edge Control register.

Definition at line 708 of file cc2538.h.

◆ GPIO_B_PI_IEN

#define GPIO_B_PI_IEN   ( *(cc2538_reg_t*)0x400da710 )

GPIO_B The Power-up Interrupt Enable register.

Definition at line 709 of file cc2538.h.

◆ GPIO_B_PMUX

#define GPIO_B_PMUX   ( *(cc2538_reg_t*)0x400da700 )

GPIO_B The PMUX register.

Definition at line 707 of file cc2538.h.

◆ GPIO_B_RIS

#define GPIO_B_RIS   ( *(cc2538_reg_t*)0x400da414 )

GPIO_B Raw Interrupt Status register.

Definition at line 701 of file cc2538.h.

◆ GPIO_B_USB_IRQ_ACK

#define GPIO_B_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400da71c )

GPIO_B IRQ Detect ACK for USB.

Definition at line 711 of file cc2538.h.

◆ GPIO_C_AFSEL

#define GPIO_C_AFSEL   ( *(cc2538_reg_t*)0x400db420 )

GPIO_C Alternate Function / mode control select register.

Definition at line 722 of file cc2538.h.

◆ GPIO_C_DATA

#define GPIO_C_DATA   ( *(cc2538_reg_t*)0x400db000 )

GPIO_C Data Register.

Definition at line 713 of file cc2538.h.

◆ GPIO_C_DIR

#define GPIO_C_DIR   ( *(cc2538_reg_t*)0x400db400 )

GPIO_C data direction register.

Definition at line 714 of file cc2538.h.

◆ GPIO_C_GPIOCR

#define GPIO_C_GPIOCR   ( *(cc2538_reg_t*)0x400db524 )

GPIO_C Commit Register.

Definition at line 724 of file cc2538.h.

◆ GPIO_C_GPIOLOCK

#define GPIO_C_GPIOLOCK   ( *(cc2538_reg_t*)0x400db520 )

GPIO_C Lock register.

Definition at line 723 of file cc2538.h.

◆ GPIO_C_IBE

#define GPIO_C_IBE   ( *(cc2538_reg_t*)0x400db408 )

GPIO_C Interrupt Both-Edges register.

Definition at line 716 of file cc2538.h.

◆ GPIO_C_IC

#define GPIO_C_IC   ( *(cc2538_reg_t*)0x400db41c )

GPIO_C Interrupt Clear register.

Definition at line 721 of file cc2538.h.

◆ GPIO_C_IE

#define GPIO_C_IE   ( *(cc2538_reg_t*)0x400db410 )

GPIO_C Interrupt mask register.

Definition at line 718 of file cc2538.h.

◆ GPIO_C_IEV

#define GPIO_C_IEV   ( *(cc2538_reg_t*)0x400db40c )

GPIO_C Interrupt Event Register.

Definition at line 717 of file cc2538.h.

◆ GPIO_C_IRQ_DETECT_ACK

#define GPIO_C_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400db718 )

GPIO_C IRQ Detect ACK register.

Definition at line 728 of file cc2538.h.

◆ GPIO_C_IRQ_DETECT_UNMASK

#define GPIO_C_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400db720 )

GPIO_C IRQ Detect ACK for masked interrupts.

Definition at line 730 of file cc2538.h.

◆ GPIO_C_IS

#define GPIO_C_IS   ( *(cc2538_reg_t*)0x400db404 )

GPIO_C Interrupt Sense register.

Definition at line 715 of file cc2538.h.

◆ GPIO_C_MIS

#define GPIO_C_MIS   ( *(cc2538_reg_t*)0x400db418 )

GPIO_C Masked Interrupt Status register.

Definition at line 720 of file cc2538.h.

◆ GPIO_C_P_EDGE_CTRL

#define GPIO_C_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400db704 )

GPIO_C The Port Edge Control register.

Definition at line 726 of file cc2538.h.

◆ GPIO_C_PI_IEN

#define GPIO_C_PI_IEN   ( *(cc2538_reg_t*)0x400db710 )

GPIO_C The Power-up Interrupt Enable register.

Definition at line 727 of file cc2538.h.

◆ GPIO_C_PMUX

#define GPIO_C_PMUX   ( *(cc2538_reg_t*)0x400db700 )

GPIO_C The PMUX register.

Definition at line 725 of file cc2538.h.

◆ GPIO_C_RIS

#define GPIO_C_RIS   ( *(cc2538_reg_t*)0x400db414 )

GPIO_C Raw Interrupt Status register.

Definition at line 719 of file cc2538.h.

◆ GPIO_C_USB_IRQ_ACK

#define GPIO_C_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400db71c )

GPIO_C IRQ Detect ACK for USB.

Definition at line 729 of file cc2538.h.

◆ GPIO_D_AFSEL

#define GPIO_D_AFSEL   ( *(cc2538_reg_t*)0x400dc420 )

GPIO_D Alternate Function / mode control select register.

Definition at line 740 of file cc2538.h.

◆ GPIO_D_DATA

#define GPIO_D_DATA   ( *(cc2538_reg_t*)0x400dc000 )

GPIO_D Data Register.

Definition at line 731 of file cc2538.h.

◆ GPIO_D_DIR

#define GPIO_D_DIR   ( *(cc2538_reg_t*)0x400dc400 )

GPIO_D data direction register.

Definition at line 732 of file cc2538.h.

◆ GPIO_D_GPIOCR

#define GPIO_D_GPIOCR   ( *(cc2538_reg_t*)0x400dc524 )

GPIO_D Commit Register.

Definition at line 742 of file cc2538.h.

◆ GPIO_D_GPIOLOCK

#define GPIO_D_GPIOLOCK   ( *(cc2538_reg_t*)0x400dc520 )

GPIO_D Lock register.

Definition at line 741 of file cc2538.h.

◆ GPIO_D_IBE

#define GPIO_D_IBE   ( *(cc2538_reg_t*)0x400dc408 )

GPIO_D Interrupt Both-Edges register.

Definition at line 734 of file cc2538.h.

◆ GPIO_D_IC

#define GPIO_D_IC   ( *(cc2538_reg_t*)0x400dc41c )

GPIO_D Interrupt Clear register.

Definition at line 739 of file cc2538.h.

◆ GPIO_D_IE

#define GPIO_D_IE   ( *(cc2538_reg_t*)0x400dc410 )

GPIO_D Interrupt mask register.

Definition at line 736 of file cc2538.h.

◆ GPIO_D_IEV

#define GPIO_D_IEV   ( *(cc2538_reg_t*)0x400dc40c )

GPIO_D Interrupt Event Register.

Definition at line 735 of file cc2538.h.

◆ GPIO_D_IRQ_DETECT_ACK

#define GPIO_D_IRQ_DETECT_ACK   ( *(cc2538_reg_t*)0x400dc718 )

GPIO_D IRQ Detect ACK register.

Definition at line 746 of file cc2538.h.

◆ GPIO_D_IRQ_DETECT_UNMASK

#define GPIO_D_IRQ_DETECT_UNMASK   ( *(cc2538_reg_t*)0x400dc720 )

GPIO_D IRQ Detect ACK for masked interrupts.

Definition at line 748 of file cc2538.h.

◆ GPIO_D_IS

#define GPIO_D_IS   ( *(cc2538_reg_t*)0x400dc404 )

GPIO_D Interrupt Sense register.

Definition at line 733 of file cc2538.h.

◆ GPIO_D_MIS

#define GPIO_D_MIS   ( *(cc2538_reg_t*)0x400dc418 )

GPIO_D Masked Interrupt Status register.

Definition at line 738 of file cc2538.h.

◆ GPIO_D_P_EDGE_CTRL

#define GPIO_D_P_EDGE_CTRL   ( *(cc2538_reg_t*)0x400dc704 )

GPIO_D The Port Edge Control register.

Definition at line 744 of file cc2538.h.

◆ GPIO_D_PI_IEN

#define GPIO_D_PI_IEN   ( *(cc2538_reg_t*)0x400dc710 )

GPIO_D The Power-up Interrupt Enable register.

Definition at line 745 of file cc2538.h.

◆ GPIO_D_PMUX

#define GPIO_D_PMUX   ( *(cc2538_reg_t*)0x400dc700 )

GPIO_D The PMUX register.

Definition at line 743 of file cc2538.h.

◆ GPIO_D_RIS

#define GPIO_D_RIS   ( *(cc2538_reg_t*)0x400dc414 )

GPIO_D Raw Interrupt Status register.

Definition at line 737 of file cc2538.h.

◆ GPIO_D_USB_IRQ_ACK

#define GPIO_D_USB_IRQ_ACK   ( *(cc2538_reg_t*)0x400dc71c )

GPIO_D IRQ Detect ACK for USB.

Definition at line 747 of file cc2538.h.

◆ GPTIMER0_CFG

#define GPTIMER0_CFG   ( *(cc2538_reg_t*)0x40030000 )

GPTM0 configuration.

Definition at line 224 of file cc2538.h.

◆ GPTIMER0_CTL

#define GPTIMER0_CTL   ( *(cc2538_reg_t*)0x4003000c )

GPTM0 control.

Definition at line 227 of file cc2538.h.

◆ GPTIMER0_ICR

#define GPTIMER0_ICR   ( *(cc2538_reg_t*)0x40030024 )

GPTM0 interrupt clear.

Definition at line 232 of file cc2538.h.

◆ GPTIMER0_IMR

#define GPTIMER0_IMR   ( *(cc2538_reg_t*)0x40030018 )

GPTM0 interrupt mask.

Definition at line 229 of file cc2538.h.

◆ GPTIMER0_MIS

#define GPTIMER0_MIS   ( *(cc2538_reg_t*)0x40030020 )

GPTM0 masked interrupt status.

Definition at line 231 of file cc2538.h.

◆ GPTIMER0_PP

#define GPTIMER0_PP   ( *(cc2538_reg_t*)0x40030fc0 )

GPTM0 peripheral properties.

Definition at line 249 of file cc2538.h.

◆ GPTIMER0_RIS

#define GPTIMER0_RIS   ( *(cc2538_reg_t*)0x4003001c )

GPTM0 raw interrupt status.

Definition at line 230 of file cc2538.h.

◆ GPTIMER0_SYNC

#define GPTIMER0_SYNC   ( *(cc2538_reg_t*)0x40030010 )

GPTM0 synchronize.

Definition at line 228 of file cc2538.h.

◆ GPTIMER0_TAILR

#define GPTIMER0_TAILR   ( *(cc2538_reg_t*)0x40030028 )

GPTM0 Timer A interval load.

Definition at line 233 of file cc2538.h.

◆ GPTIMER0_TAMATCHR

#define GPTIMER0_TAMATCHR   ( *(cc2538_reg_t*)0x40030030 )

GPTM0 Timer A match.

Definition at line 235 of file cc2538.h.

◆ GPTIMER0_TAMR

#define GPTIMER0_TAMR   ( *(cc2538_reg_t*)0x40030004 )

GPTM0 Timer A mode.

Definition at line 225 of file cc2538.h.

◆ GPTIMER0_TAPMR

#define GPTIMER0_TAPMR   ( *(cc2538_reg_t*)0x40030040 )

GPTM0 Timer A prescale match.

Definition at line 239 of file cc2538.h.

◆ GPTIMER0_TAPR

#define GPTIMER0_TAPR   ( *(cc2538_reg_t*)0x40030038 )

GPTM0 Timer A prescale.

Definition at line 237 of file cc2538.h.

◆ GPTIMER0_TAPS

#define GPTIMER0_TAPS   ( *(cc2538_reg_t*)0x4003005c )

GPTM0 Timer A prescale snapshot.

Definition at line 245 of file cc2538.h.

◆ GPTIMER0_TAPV

#define GPTIMER0_TAPV   ( *(cc2538_reg_t*)0x40030064 )

GPTM0 Timer A prescale value.

Definition at line 247 of file cc2538.h.

◆ GPTIMER0_TAR

#define GPTIMER0_TAR   ( *(cc2538_reg_t*)0x40030048 )

GPTM0 Timer A.

Definition at line 241 of file cc2538.h.

◆ GPTIMER0_TAV

#define GPTIMER0_TAV   ( *(cc2538_reg_t*)0x40030050 )

GPTM0 Timer A value.

Definition at line 243 of file cc2538.h.

◆ GPTIMER0_TBILR

#define GPTIMER0_TBILR   ( *(cc2538_reg_t*)0x4003002c )

GPTM0 Timer B interval load.

Definition at line 234 of file cc2538.h.

◆ GPTIMER0_TBMATCHR

#define GPTIMER0_TBMATCHR   ( *(cc2538_reg_t*)0x40030034 )

GPTM0 Timer B match.

Definition at line 236 of file cc2538.h.

◆ GPTIMER0_TBMR

#define GPTIMER0_TBMR   ( *(cc2538_reg_t*)0x40030008 )

GPTM0 Timer B mode.

Definition at line 226 of file cc2538.h.

◆ GPTIMER0_TBPMR

#define GPTIMER0_TBPMR   ( *(cc2538_reg_t*)0x40030044 )

GPTM0 Timer B prescale match.

Definition at line 240 of file cc2538.h.

◆ GPTIMER0_TBPR

#define GPTIMER0_TBPR   ( *(cc2538_reg_t*)0x4003003c )

GPTM0 Timer B prescale.

Definition at line 238 of file cc2538.h.

◆ GPTIMER0_TBPS

#define GPTIMER0_TBPS   ( *(cc2538_reg_t*)0x40030060 )

GPTM0 Timer B prescale snapshot.

Definition at line 246 of file cc2538.h.

◆ GPTIMER0_TBPV

#define GPTIMER0_TBPV   ( *(cc2538_reg_t*)0x40030068 )

GPTM0 Timer B prescale value.

Definition at line 248 of file cc2538.h.

◆ GPTIMER0_TBR

#define GPTIMER0_TBR   ( *(cc2538_reg_t*)0x4003004c )

GPTM0 Timer B.

Definition at line 242 of file cc2538.h.

◆ GPTIMER0_TBV

#define GPTIMER0_TBV   ( *(cc2538_reg_t*)0x40030054 )

GPTM0 Timer B value.

Definition at line 244 of file cc2538.h.

◆ GPTIMER1_CFG

#define GPTIMER1_CFG   ( *(cc2538_reg_t*)0x40031000 )

GPTM1 configuration.

Definition at line 250 of file cc2538.h.

◆ GPTIMER1_CTL

#define GPTIMER1_CTL   ( *(cc2538_reg_t*)0x4003100c )

GPTM1 control.

Definition at line 253 of file cc2538.h.

◆ GPTIMER1_ICR

#define GPTIMER1_ICR   ( *(cc2538_reg_t*)0x40031024 )

GPTM1 interrupt clear.

Definition at line 258 of file cc2538.h.

◆ GPTIMER1_IMR

#define GPTIMER1_IMR   ( *(cc2538_reg_t*)0x40031018 )

GPTM1 interrupt mask.

Definition at line 255 of file cc2538.h.

◆ GPTIMER1_MIS

#define GPTIMER1_MIS   ( *(cc2538_reg_t*)0x40031020 )

GPTM1 masked interrupt status.

Definition at line 257 of file cc2538.h.

◆ GPTIMER1_PP

#define GPTIMER1_PP   ( *(cc2538_reg_t*)0x40031fc0 )

GPTM1 peripheral properties.

Definition at line 275 of file cc2538.h.

◆ GPTIMER1_RIS

#define GPTIMER1_RIS   ( *(cc2538_reg_t*)0x4003101c )

GPTM1 raw interrupt status.

Definition at line 256 of file cc2538.h.

◆ GPTIMER1_SYNC

#define GPTIMER1_SYNC   ( *(cc2538_reg_t*)0x40031010 )

GPTM1 synchronize.

Definition at line 254 of file cc2538.h.

◆ GPTIMER1_TAILR

#define GPTIMER1_TAILR   ( *(cc2538_reg_t*)0x40031028 )

GPTM1 Timer A interval load.

Definition at line 259 of file cc2538.h.

◆ GPTIMER1_TAMATCHR

#define GPTIMER1_TAMATCHR   ( *(cc2538_reg_t*)0x40031030 )

GPTM1 Timer A match.

Definition at line 261 of file cc2538.h.

◆ GPTIMER1_TAMR

#define GPTIMER1_TAMR   ( *(cc2538_reg_t*)0x40031004 )

GPTM1 Timer A mode.

Definition at line 251 of file cc2538.h.

◆ GPTIMER1_TAPMR

#define GPTIMER1_TAPMR   ( *(cc2538_reg_t*)0x40031040 )

GPTM1 Timer A prescale match.

Definition at line 265 of file cc2538.h.

◆ GPTIMER1_TAPR

#define GPTIMER1_TAPR   ( *(cc2538_reg_t*)0x40031038 )

GPTM1 Timer A prescale.

Definition at line 263 of file cc2538.h.

◆ GPTIMER1_TAPS

#define GPTIMER1_TAPS   ( *(cc2538_reg_t*)0x4003105c )

GPTM1 Timer A prescale snapshot.

Definition at line 271 of file cc2538.h.

◆ GPTIMER1_TAPV

#define GPTIMER1_TAPV   ( *(cc2538_reg_t*)0x40031064 )

GPTM1 Timer A prescale value.

Definition at line 273 of file cc2538.h.

◆ GPTIMER1_TAR

#define GPTIMER1_TAR   ( *(cc2538_reg_t*)0x40031048 )

GPTM1 Timer A.

Definition at line 267 of file cc2538.h.

◆ GPTIMER1_TAV

#define GPTIMER1_TAV   ( *(cc2538_reg_t*)0x40031050 )

GPTM1 Timer A value.

Definition at line 269 of file cc2538.h.

◆ GPTIMER1_TBILR

#define GPTIMER1_TBILR   ( *(cc2538_reg_t*)0x4003102c )

GPTM1 Timer B interval load.

Definition at line 260 of file cc2538.h.

◆ GPTIMER1_TBMATCHR

#define GPTIMER1_TBMATCHR   ( *(cc2538_reg_t*)0x40031034 )

GPTM1 Timer B match.

Definition at line 262 of file cc2538.h.

◆ GPTIMER1_TBMR

#define GPTIMER1_TBMR   ( *(cc2538_reg_t*)0x40031008 )

GPTM1 Timer B mode.

Definition at line 252 of file cc2538.h.

◆ GPTIMER1_TBPMR

#define GPTIMER1_TBPMR   ( *(cc2538_reg_t*)0x40031044 )

GPTM1 Timer B prescale match.

Definition at line 266 of file cc2538.h.

◆ GPTIMER1_TBPR

#define GPTIMER1_TBPR   ( *(cc2538_reg_t*)0x4003103c )

GPTM1 Timer B prescale.

Definition at line 264 of file cc2538.h.

◆ GPTIMER1_TBPS

#define GPTIMER1_TBPS   ( *(cc2538_reg_t*)0x40031060 )

GPTM1 Timer B prescale snapshot.

Definition at line 272 of file cc2538.h.

◆ GPTIMER1_TBPV

#define GPTIMER1_TBPV   ( *(cc2538_reg_t*)0x40031068 )

GPTM1 Timer B prescale value.

Definition at line 274 of file cc2538.h.

◆ GPTIMER1_TBR

#define GPTIMER1_TBR   ( *(cc2538_reg_t*)0x4003104c )

GPTM1 Timer B.

Definition at line 268 of file cc2538.h.

◆ GPTIMER1_TBV

#define GPTIMER1_TBV   ( *(cc2538_reg_t*)0x40031054 )

GPTM1 Timer B value.

Definition at line 270 of file cc2538.h.

◆ GPTIMER2_CFG

#define GPTIMER2_CFG   ( *(cc2538_reg_t*)0x40032000 )

GPTM2 configuration.

Definition at line 276 of file cc2538.h.

◆ GPTIMER2_CTL

#define GPTIMER2_CTL   ( *(cc2538_reg_t*)0x4003200c )

GPTM2 control.

Definition at line 279 of file cc2538.h.

◆ GPTIMER2_ICR

#define GPTIMER2_ICR   ( *(cc2538_reg_t*)0x40032024 )

GPTM2 interrupt clear.

Definition at line 284 of file cc2538.h.

◆ GPTIMER2_IMR

#define GPTIMER2_IMR   ( *(cc2538_reg_t*)0x40032018 )

GPTM2 interrupt mask.

Definition at line 281 of file cc2538.h.

◆ GPTIMER2_MIS

#define GPTIMER2_MIS   ( *(cc2538_reg_t*)0x40032020 )

GPTM2 masked interrupt status.

Definition at line 283 of file cc2538.h.

◆ GPTIMER2_PP

#define GPTIMER2_PP   ( *(cc2538_reg_t*)0x40032fc0 )

GPTM2 peripheral properties.

Definition at line 301 of file cc2538.h.

◆ GPTIMER2_RIS

#define GPTIMER2_RIS   ( *(cc2538_reg_t*)0x4003201c )

GPTM2 raw interrupt status.

Definition at line 282 of file cc2538.h.

◆ GPTIMER2_SYNC

#define GPTIMER2_SYNC   ( *(cc2538_reg_t*)0x40032010 )

GPTM2 synchronize.

Definition at line 280 of file cc2538.h.

◆ GPTIMER2_TAILR

#define GPTIMER2_TAILR   ( *(cc2538_reg_t*)0x40032028 )

GPTM2 Timer A interval load.

Definition at line 285 of file cc2538.h.

◆ GPTIMER2_TAMATCHR

#define GPTIMER2_TAMATCHR   ( *(cc2538_reg_t*)0x40032030 )

GPTM2 Timer A match.

Definition at line 287 of file cc2538.h.

◆ GPTIMER2_TAMR

#define GPTIMER2_TAMR   ( *(cc2538_reg_t*)0x40032004 )

GPTM2 Timer A mode.

Definition at line 277 of file cc2538.h.

◆ GPTIMER2_TAPMR

#define GPTIMER2_TAPMR   ( *(cc2538_reg_t*)0x40032040 )

GPTM2 Timer A prescale match.

Definition at line 291 of file cc2538.h.

◆ GPTIMER2_TAPR

#define GPTIMER2_TAPR   ( *(cc2538_reg_t*)0x40032038 )

GPTM2 Timer A prescale.

Definition at line 289 of file cc2538.h.

◆ GPTIMER2_TAPS

#define GPTIMER2_TAPS   ( *(cc2538_reg_t*)0x4003205c )

GPTM2 Timer A prescale snapshot.

Definition at line 297 of file cc2538.h.

◆ GPTIMER2_TAPV

#define GPTIMER2_TAPV   ( *(cc2538_reg_t*)0x40032064 )

GPTM2 Timer A prescale value.

Definition at line 299 of file cc2538.h.

◆ GPTIMER2_TAR

#define GPTIMER2_TAR   ( *(cc2538_reg_t*)0x40032048 )

GPTM2 Timer A.

Definition at line 293 of file cc2538.h.

◆ GPTIMER2_TAV

#define GPTIMER2_TAV   ( *(cc2538_reg_t*)0x40032050 )

GPTM2 Timer A value.

Definition at line 295 of file cc2538.h.

◆ GPTIMER2_TBILR

#define GPTIMER2_TBILR   ( *(cc2538_reg_t*)0x4003202c )

GPTM2 Timer B interval load.

Definition at line 286 of file cc2538.h.

◆ GPTIMER2_TBMATCHR

#define GPTIMER2_TBMATCHR   ( *(cc2538_reg_t*)0x40032034 )

GPTM2 Timer B match.

Definition at line 288 of file cc2538.h.

◆ GPTIMER2_TBMR

#define GPTIMER2_TBMR   ( *(cc2538_reg_t*)0x40032008 )

GPTM2 Timer B mode.

Definition at line 278 of file cc2538.h.

◆ GPTIMER2_TBPMR

#define GPTIMER2_TBPMR   ( *(cc2538_reg_t*)0x40032044 )

GPTM2 Timer B prescale match.

Definition at line 292 of file cc2538.h.

◆ GPTIMER2_TBPR

#define GPTIMER2_TBPR   ( *(cc2538_reg_t*)0x4003203c )

GPTM2 Timer B prescale.

Definition at line 290 of file cc2538.h.

◆ GPTIMER2_TBPS

#define GPTIMER2_TBPS   ( *(cc2538_reg_t*)0x40032060 )

GPTM2 Timer B prescale snapshot.

Definition at line 298 of file cc2538.h.

◆ GPTIMER2_TBPV

#define GPTIMER2_TBPV   ( *(cc2538_reg_t*)0x40032068 )

GPTM2 Timer B prescale value.

Definition at line 300 of file cc2538.h.

◆ GPTIMER2_TBR

#define GPTIMER2_TBR   ( *(cc2538_reg_t*)0x4003204c )

GPTM2 Timer B.

Definition at line 294 of file cc2538.h.

◆ GPTIMER2_TBV

#define GPTIMER2_TBV   ( *(cc2538_reg_t*)0x40032054 )

GPTM2 Timer B value.

Definition at line 296 of file cc2538.h.

◆ GPTIMER3_CFG

#define GPTIMER3_CFG   ( *(cc2538_reg_t*)0x40033000 )

GPTM3 configuration.

Definition at line 302 of file cc2538.h.

◆ GPTIMER3_CTL

#define GPTIMER3_CTL   ( *(cc2538_reg_t*)0x4003300c )

GPTM3 control.

Definition at line 305 of file cc2538.h.

◆ GPTIMER3_ICR

#define GPTIMER3_ICR   ( *(cc2538_reg_t*)0x40033024 )

GPTM3 interrupt clear.

Definition at line 310 of file cc2538.h.

◆ GPTIMER3_IMR

#define GPTIMER3_IMR   ( *(cc2538_reg_t*)0x40033018 )

GPTM3 interrupt mask.

Definition at line 307 of file cc2538.h.

◆ GPTIMER3_MIS

#define GPTIMER3_MIS   ( *(cc2538_reg_t*)0x40033020 )

GPTM3 masked interrupt status.

Definition at line 309 of file cc2538.h.

◆ GPTIMER3_PP

#define GPTIMER3_PP   ( *(cc2538_reg_t*)0x40033fc0 )

GPTM3 peripheral properties.

Definition at line 327 of file cc2538.h.

◆ GPTIMER3_RIS

#define GPTIMER3_RIS   ( *(cc2538_reg_t*)0x4003301c )

GPTM3 raw interrupt status.

Definition at line 308 of file cc2538.h.

◆ GPTIMER3_SYNC

#define GPTIMER3_SYNC   ( *(cc2538_reg_t*)0x40033010 )

GPTM3 synchronize.

Definition at line 306 of file cc2538.h.

◆ GPTIMER3_TAILR

#define GPTIMER3_TAILR   ( *(cc2538_reg_t*)0x40033028 )

GPTM3 Timer A interval load.

Definition at line 311 of file cc2538.h.

◆ GPTIMER3_TAMATCHR

#define GPTIMER3_TAMATCHR   ( *(cc2538_reg_t*)0x40033030 )

GPTM3 Timer A match.

Definition at line 313 of file cc2538.h.

◆ GPTIMER3_TAMR

#define GPTIMER3_TAMR   ( *(cc2538_reg_t*)0x40033004 )

GPTM3 Timer A mode.

Definition at line 303 of file cc2538.h.

◆ GPTIMER3_TAPMR

#define GPTIMER3_TAPMR   ( *(cc2538_reg_t*)0x40033040 )

GPTM3 Timer A prescale match.

Definition at line 317 of file cc2538.h.

◆ GPTIMER3_TAPR

#define GPTIMER3_TAPR   ( *(cc2538_reg_t*)0x40033038 )

GPTM3 Timer A prescale.

Definition at line 315 of file cc2538.h.

◆ GPTIMER3_TAPS

#define GPTIMER3_TAPS   ( *(cc2538_reg_t*)0x4003305c )

GPTM3 Timer A prescale snapshot.

Definition at line 323 of file cc2538.h.

◆ GPTIMER3_TAPV

#define GPTIMER3_TAPV   ( *(cc2538_reg_t*)0x40033064 )

GPTM3 Timer A prescale value.

Definition at line 325 of file cc2538.h.

◆ GPTIMER3_TAR

#define GPTIMER3_TAR   ( *(cc2538_reg_t*)0x40033048 )

GPTM3 Timer A.

Definition at line 319 of file cc2538.h.

◆ GPTIMER3_TAV

#define GPTIMER3_TAV   ( *(cc2538_reg_t*)0x40033050 )

GPTM3 Timer A value.

Definition at line 321 of file cc2538.h.

◆ GPTIMER3_TBILR

#define GPTIMER3_TBILR   ( *(cc2538_reg_t*)0x4003302c )

GPTM3 Timer B interval load.

Definition at line 312 of file cc2538.h.

◆ GPTIMER3_TBMATCHR

#define GPTIMER3_TBMATCHR   ( *(cc2538_reg_t*)0x40033034 )

GPTM3 Timer B match.

Definition at line 314 of file cc2538.h.

◆ GPTIMER3_TBMR

#define GPTIMER3_TBMR   ( *(cc2538_reg_t*)0x40033008 )

GPTM3 Timer B mode.

Definition at line 304 of file cc2538.h.

◆ GPTIMER3_TBPMR

#define GPTIMER3_TBPMR   ( *(cc2538_reg_t*)0x40033044 )

GPTM3 Timer B prescale match.

Definition at line 318 of file cc2538.h.

◆ GPTIMER3_TBPR

#define GPTIMER3_TBPR   ( *(cc2538_reg_t*)0x4003303c )

GPTM3 Timer B prescale.

Definition at line 316 of file cc2538.h.

◆ GPTIMER3_TBPS

#define GPTIMER3_TBPS   ( *(cc2538_reg_t*)0x40033060 )

GPTM3 Timer B prescale snapshot.

Definition at line 324 of file cc2538.h.

◆ GPTIMER3_TBPV

#define GPTIMER3_TBPV   ( *(cc2538_reg_t*)0x40033068 )

GPTM3 Timer B prescale value.

Definition at line 326 of file cc2538.h.

◆ GPTIMER3_TBR

#define GPTIMER3_TBR   ( *(cc2538_reg_t*)0x4003304c )

GPTM3 Timer B.

Definition at line 320 of file cc2538.h.

◆ GPTIMER3_TBV

#define GPTIMER3_TBV   ( *(cc2538_reg_t*)0x40033054 )

GPTM3 Timer B value.

Definition at line 322 of file cc2538.h.

◆ I2CM_CR

#define I2CM_CR   ( *(cc2538_reg_t*)0x40020020 )

I2C Master Configuration.

Definition at line 215 of file cc2538.h.

◆ I2CM_CTRL

#define I2CM_CTRL   ( *(cc2538_reg_t*)0x40020004 )

I2C Master Control and status.

Definition at line 207 of file cc2538.h.

◆ I2CM_DR

#define I2CM_DR   ( *(cc2538_reg_t*)0x40020008 )

I2C Master Data.

Definition at line 209 of file cc2538.h.

◆ I2CM_ICR

#define I2CM_ICR   ( *(cc2538_reg_t*)0x4002001c )

I2C Master Interrupt clear.

Definition at line 214 of file cc2538.h.

◆ I2CM_IMR

#define I2CM_IMR   ( *(cc2538_reg_t*)0x40020010 )

I2C Master Interrupt mask.

Definition at line 211 of file cc2538.h.

◆ I2CM_MIS

#define I2CM_MIS   ( *(cc2538_reg_t*)0x40020018 )

I2C Master Masked interrupt status.

Definition at line 213 of file cc2538.h.

◆ I2CM_RIS

#define I2CM_RIS   ( *(cc2538_reg_t*)0x40020014 )

I2C Master Raw interrupt status.

Definition at line 212 of file cc2538.h.

◆ I2CM_SA

#define I2CM_SA   ( *(cc2538_reg_t*)0x40020000 )

I2C Master Slave address.

Definition at line 206 of file cc2538.h.

◆ I2CM_STAT

#define I2CM_STAT   ( *(cc2538_reg_t*)0x40020004 )

I2C Master Control and status.

Definition at line 208 of file cc2538.h.

◆ I2CM_TPR

#define I2CM_TPR   ( *(cc2538_reg_t*)0x4002000c )

I2C Master Timer period.

Definition at line 210 of file cc2538.h.

◆ I2CS_CTRL

#define I2CS_CTRL   ( *(cc2538_reg_t*)0x40020804 )

I2C Slave Control and status.

Definition at line 217 of file cc2538.h.

◆ I2CS_DR

#define I2CS_DR   ( *(cc2538_reg_t*)0x40020808 )

I2C Slave Data.

Definition at line 219 of file cc2538.h.

◆ I2CS_ICR

#define I2CS_ICR   ( *(cc2538_reg_t*)0x40020818 )

I2C Slave Interrupt clear.

Definition at line 223 of file cc2538.h.

◆ I2CS_IMR

#define I2CS_IMR   ( *(cc2538_reg_t*)0x4002080c )

I2C Slave Interrupt mask.

Definition at line 220 of file cc2538.h.

◆ I2CS_MIS

#define I2CS_MIS   ( *(cc2538_reg_t*)0x40020814 )

I2C Slave Masked interrupt status.

Definition at line 222 of file cc2538.h.

◆ I2CS_OAR

#define I2CS_OAR   ( *(cc2538_reg_t*)0x40020800 )

I2C Slave own address.

Definition at line 216 of file cc2538.h.

◆ I2CS_RIS

#define I2CS_RIS   ( *(cc2538_reg_t*)0x40020810 )

I2C Slave Raw interrupt status.

Definition at line 221 of file cc2538.h.

◆ I2CS_STAT

#define I2CS_STAT   ( *(cc2538_reg_t*)0x40020804 )

I2C Slave Control and status.

Definition at line 218 of file cc2538.h.

◆ IEEE_ADDR_LSWORD

#define IEEE_ADDR_LSWORD   ( *(const uint32_t*)0x0028002c )

Least-significant 32 bits of the IEEE address.

Definition at line 122 of file cc2538.h.

◆ IEEE_ADDR_MSWORD

#define IEEE_ADDR_MSWORD   ( *(const uint32_t*)0x00280028 )

CMSIS includes.

Most-significant 32 bits of the IEEE address

Definition at line 121 of file cc2538.h.

◆ IOC_CLK_SSI_SSI0

#define IOC_CLK_SSI_SSI0   ( *(cc2538_reg_t*)0x400d410c )

Pin selection for SSI0 CLK.

Definition at line 646 of file cc2538.h.

◆ IOC_CLK_SSI_SSI1

#define IOC_CLK_SSI_SSI1   ( *(cc2538_reg_t*)0x400d411c )

Pin selection for SSI1 CLK.

Definition at line 650 of file cc2538.h.

◆ IOC_CLK_SSIIN_SSI0

#define IOC_CLK_SSIIN_SSI0   ( *(cc2538_reg_t*)0x400d4118 )

Pin selection for SSI0 CLK_SSIN.

Definition at line 649 of file cc2538.h.

◆ IOC_CLK_SSIIN_SSI1

#define IOC_CLK_SSIIN_SSI1   ( *(cc2538_reg_t*)0x400d4128 )

Pin selection for SSI1 CLK_SSIN.

Definition at line 653 of file cc2538.h.

◆ IOC_GPT0OCP1

#define IOC_GPT0OCP1   ( *(cc2538_reg_t*)0x400d4134 )

Pin selection for GPT0OCP1.

Definition at line 656 of file cc2538.h.

◆ IOC_GPT0OCP2

#define IOC_GPT0OCP2   ( *(cc2538_reg_t*)0x400d4138 )

Pin selection for GPT0OCP2.

Definition at line 657 of file cc2538.h.

◆ IOC_GPT1OCP1

#define IOC_GPT1OCP1   ( *(cc2538_reg_t*)0x400d413c )

Pin selection for GPT1OCP1.

Definition at line 658 of file cc2538.h.

◆ IOC_GPT1OCP2

#define IOC_GPT1OCP2   ( *(cc2538_reg_t*)0x400d4140 )

Pin selection for GPT1OCP2.

Definition at line 659 of file cc2538.h.

◆ IOC_GPT2OCP1

#define IOC_GPT2OCP1   ( *(cc2538_reg_t*)0x400d4144 )

Pin selection for GPT2OCP1.

Definition at line 660 of file cc2538.h.

◆ IOC_GPT2OCP2

#define IOC_GPT2OCP2   ( *(cc2538_reg_t*)0x400d4148 )

Pin selection for GPT2OCP2.

Definition at line 661 of file cc2538.h.

◆ IOC_GPT3OCP1

#define IOC_GPT3OCP1   ( *(cc2538_reg_t*)0x400d414c )

Pin selection for GPT3OCP1.

Definition at line 662 of file cc2538.h.

◆ IOC_GPT3OCP2

#define IOC_GPT3OCP2   ( *(cc2538_reg_t*)0x400d4150 )

Pin selection for GPT3OCP2.

Definition at line 663 of file cc2538.h.

◆ IOC_I2CMSSCL

#define IOC_I2CMSSCL   ( *(cc2538_reg_t*)0x400d4130 )

Pin selection for I2C SCL.

Definition at line 655 of file cc2538.h.

◆ IOC_I2CMSSDA

#define IOC_I2CMSSDA   ( *(cc2538_reg_t*)0x400d412c )

Pin selection for I2C SDA.

Definition at line 654 of file cc2538.h.

◆ IOC_PA0_OVER

#define IOC_PA0_OVER   ( *(cc2538_reg_t*)0x400d4080 )

Override configuration register for PA0.

Definition at line 611 of file cc2538.h.

◆ IOC_PA0_SEL

#define IOC_PA0_SEL   ( *(cc2538_reg_t*)0x400d4000 )

Peripheral select control for PA0.

Definition at line 579 of file cc2538.h.

◆ IOC_PA1_OVER

#define IOC_PA1_OVER   ( *(cc2538_reg_t*)0x400d4084 )

Override configuration register for PA1.

Definition at line 612 of file cc2538.h.

◆ IOC_PA1_SEL

#define IOC_PA1_SEL   ( *(cc2538_reg_t*)0x400d4004 )

Peripheral select control for PA1.

Definition at line 580 of file cc2538.h.

◆ IOC_PA2_OVER

#define IOC_PA2_OVER   ( *(cc2538_reg_t*)0x400d4088 )

Override configuration register for PA2.

Definition at line 613 of file cc2538.h.

◆ IOC_PA2_SEL

#define IOC_PA2_SEL   ( *(cc2538_reg_t*)0x400d4008 )

Peripheral select control for PA2.

Definition at line 581 of file cc2538.h.

◆ IOC_PA3_OVER

#define IOC_PA3_OVER   ( *(cc2538_reg_t*)0x400d408c )

Override configuration register for PA3.

Definition at line 614 of file cc2538.h.

◆ IOC_PA3_SEL

#define IOC_PA3_SEL   ( *(cc2538_reg_t*)0x400d400c )

Peripheral select control for PA3.

Definition at line 582 of file cc2538.h.

◆ IOC_PA4_OVER

#define IOC_PA4_OVER   ( *(cc2538_reg_t*)0x400d4090 )

Override configuration register for PA4.

Definition at line 615 of file cc2538.h.

◆ IOC_PA4_SEL

#define IOC_PA4_SEL   ( *(cc2538_reg_t*)0x400d4010 )

Peripheral select control for PA4.

Definition at line 583 of file cc2538.h.

◆ IOC_PA5_OVER

#define IOC_PA5_OVER   ( *(cc2538_reg_t*)0x400d4094 )

Override configuration register for PA5.

Definition at line 616 of file cc2538.h.

◆ IOC_PA5_SEL

#define IOC_PA5_SEL   ( *(cc2538_reg_t*)0x400d4014 )

Peripheral select control for PA5.

Definition at line 584 of file cc2538.h.

◆ IOC_PA6_OVER

#define IOC_PA6_OVER   ( *(cc2538_reg_t*)0x400d4098 )

Override configuration register for PA6.

Definition at line 617 of file cc2538.h.

◆ IOC_PA6_SEL

#define IOC_PA6_SEL   ( *(cc2538_reg_t*)0x400d4018 )

Peripheral select control for PA6.

Definition at line 585 of file cc2538.h.

◆ IOC_PA7_OVER

#define IOC_PA7_OVER   ( *(cc2538_reg_t*)0x400d409c )

Override configuration register for PA7.

Definition at line 618 of file cc2538.h.

◆ IOC_PA7_SEL

#define IOC_PA7_SEL   ( *(cc2538_reg_t*)0x400d401c )

Peripheral select control for PA7.

Definition at line 586 of file cc2538.h.

◆ IOC_PB0_OVER

#define IOC_PB0_OVER   ( *(cc2538_reg_t*)0x400d40a0 )

Override configuration register for PB0.

Definition at line 619 of file cc2538.h.

◆ IOC_PB0_SEL

#define IOC_PB0_SEL   ( *(cc2538_reg_t*)0x400d4020 )

Peripheral select control for PB0.

Definition at line 587 of file cc2538.h.

◆ IOC_PB1_OVER

#define IOC_PB1_OVER   ( *(cc2538_reg_t*)0x400d40a4 )

Override configuration register for PB1.

Definition at line 620 of file cc2538.h.

◆ IOC_PB1_SEL

#define IOC_PB1_SEL   ( *(cc2538_reg_t*)0x400d4024 )

Peripheral select control for PB1.

Definition at line 588 of file cc2538.h.

◆ IOC_PB2_OVER

#define IOC_PB2_OVER   ( *(cc2538_reg_t*)0x400d40a8 )

Override configuration register for PB2.

Definition at line 621 of file cc2538.h.

◆ IOC_PB2_SEL

#define IOC_PB2_SEL   ( *(cc2538_reg_t*)0x400d4028 )

Peripheral select control for PB2.

Definition at line 589 of file cc2538.h.

◆ IOC_PB3_OVER

#define IOC_PB3_OVER   ( *(cc2538_reg_t*)0x400d40ac )

Override configuration register for PB3.

Definition at line 622 of file cc2538.h.

◆ IOC_PB3_SEL

#define IOC_PB3_SEL   ( *(cc2538_reg_t*)0x400d402c )

Peripheral select control for PB3.

Definition at line 590 of file cc2538.h.

◆ IOC_PB4_OVER

#define IOC_PB4_OVER   ( *(cc2538_reg_t*)0x400d40b0 )

Override configuration register for PB4.

Definition at line 623 of file cc2538.h.

◆ IOC_PB4_SEL

#define IOC_PB4_SEL   ( *(cc2538_reg_t*)0x400d4030 )

Peripheral select control for PB4.

Definition at line 591 of file cc2538.h.

◆ IOC_PB5_OVER

#define IOC_PB5_OVER   ( *(cc2538_reg_t*)0x400d40b4 )

Override configuration register for PB5.

Definition at line 624 of file cc2538.h.

◆ IOC_PB5_SEL

#define IOC_PB5_SEL   ( *(cc2538_reg_t*)0x400d4034 )

Peripheral select control for PB5.

Definition at line 592 of file cc2538.h.

◆ IOC_PB6_OVER

#define IOC_PB6_OVER   ( *(cc2538_reg_t*)0x400d40b8 )

Override configuration register for PB6.

Definition at line 625 of file cc2538.h.

◆ IOC_PB6_SEL

#define IOC_PB6_SEL   ( *(cc2538_reg_t*)0x400d4038 )

Peripheral select control for PB6.

Definition at line 593 of file cc2538.h.

◆ IOC_PB7_OVER

#define IOC_PB7_OVER   ( *(cc2538_reg_t*)0x400d40bc )

Override configuration register for PB7.

Definition at line 626 of file cc2538.h.

◆ IOC_PB7_SEL

#define IOC_PB7_SEL   ( *(cc2538_reg_t*)0x400d403c )

Peripheral select control for PB7.

Definition at line 594 of file cc2538.h.

◆ IOC_PC0_OVER

#define IOC_PC0_OVER   ( *(cc2538_reg_t*)0x400d40c0 )

Override configuration register for PC0.

PC0 has high drive capability.

Definition at line 627 of file cc2538.h.

◆ IOC_PC0_SEL

#define IOC_PC0_SEL   ( *(cc2538_reg_t*)0x400d4040 )

Peripheral select control for PC0.

Definition at line 595 of file cc2538.h.

◆ IOC_PC1_OVER

#define IOC_PC1_OVER   ( *(cc2538_reg_t*)0x400d40c4 )

Override configuration register for PC1.

PC1 has high drive capability.

Definition at line 628 of file cc2538.h.

◆ IOC_PC1_SEL

#define IOC_PC1_SEL   ( *(cc2538_reg_t*)0x400d4044 )

Peripheral select control for PC1.

Definition at line 596 of file cc2538.h.

◆ IOC_PC2_OVER

#define IOC_PC2_OVER   ( *(cc2538_reg_t*)0x400d40c8 )

Override configuration register for PC2.

PC2 has high drive capability.

Definition at line 629 of file cc2538.h.

◆ IOC_PC2_SEL

#define IOC_PC2_SEL   ( *(cc2538_reg_t*)0x400d4048 )

Peripheral select control for PC2.

Definition at line 597 of file cc2538.h.

◆ IOC_PC3_OVER

#define IOC_PC3_OVER   ( *(cc2538_reg_t*)0x400d40cc )

Override configuration register for PC3.

PC3 has high drive capability.

Definition at line 630 of file cc2538.h.

◆ IOC_PC3_SEL

#define IOC_PC3_SEL   ( *(cc2538_reg_t*)0x400d404c )

Peripheral select control for PC3.

Definition at line 598 of file cc2538.h.

◆ IOC_PC4_OVER

#define IOC_PC4_OVER   ( *(cc2538_reg_t*)0x400d40d0 )

Override configuration register for PC4.

Definition at line 631 of file cc2538.h.

◆ IOC_PC4_SEL

#define IOC_PC4_SEL   ( *(cc2538_reg_t*)0x400d4050 )

Peripheral select control for PC4.

Definition at line 599 of file cc2538.h.

◆ IOC_PC5_OVER

#define IOC_PC5_OVER   ( *(cc2538_reg_t*)0x400d40d4 )

Override configuration register for PC5.

Definition at line 632 of file cc2538.h.

◆ IOC_PC5_SEL

#define IOC_PC5_SEL   ( *(cc2538_reg_t*)0x400d4054 )

Peripheral select control for PC5.

Definition at line 600 of file cc2538.h.

◆ IOC_PC6_OVER

#define IOC_PC6_OVER   ( *(cc2538_reg_t*)0x400d40d8 )

Override configuration register for PC6.

Definition at line 633 of file cc2538.h.

◆ IOC_PC6_SEL

#define IOC_PC6_SEL   ( *(cc2538_reg_t*)0x400d4058 )

Peripheral select control for PC6.

Definition at line 601 of file cc2538.h.

◆ IOC_PC7_OVER

#define IOC_PC7_OVER   ( *(cc2538_reg_t*)0x400d40dc )

Override configuration register for PC7.

Definition at line 634 of file cc2538.h.

◆ IOC_PC7_SEL

#define IOC_PC7_SEL   ( *(cc2538_reg_t*)0x400d405c )

Peripheral select control for PC7.

Definition at line 602 of file cc2538.h.

◆ IOC_PD0_OVER

#define IOC_PD0_OVER   ( *(cc2538_reg_t*)0x400d40e0 )

Override configuration register for PD0.

Definition at line 635 of file cc2538.h.

◆ IOC_PD0_SEL

#define IOC_PD0_SEL   ( *(cc2538_reg_t*)0x400d4060 )

Peripheral select control for PD0.

Definition at line 603 of file cc2538.h.

◆ IOC_PD1_OVER

#define IOC_PD1_OVER   ( *(cc2538_reg_t*)0x400d40e4 )

Override configuration register for PD1.

Definition at line 636 of file cc2538.h.

◆ IOC_PD1_SEL

#define IOC_PD1_SEL   ( *(cc2538_reg_t*)0x400d4064 )

Peripheral select control for PD1.

Definition at line 604 of file cc2538.h.

◆ IOC_PD2_OVER

#define IOC_PD2_OVER   ( *(cc2538_reg_t*)0x400d40e8 )

Override configuration register for PD2.

Definition at line 637 of file cc2538.h.

◆ IOC_PD2_SEL

#define IOC_PD2_SEL   ( *(cc2538_reg_t*)0x400d4068 )

Peripheral select control for PD2.

Definition at line 605 of file cc2538.h.

◆ IOC_PD3_OVER

#define IOC_PD3_OVER   ( *(cc2538_reg_t*)0x400d40ec )

Override configuration register for PD3.

Definition at line 638 of file cc2538.h.

◆ IOC_PD3_SEL

#define IOC_PD3_SEL   ( *(cc2538_reg_t*)0x400d406c )

Peripheral select control for PD3.

Definition at line 606 of file cc2538.h.

◆ IOC_PD4_OVER

#define IOC_PD4_OVER   ( *(cc2538_reg_t*)0x400d40f0 )

Override configuration register for PD4.

Definition at line 639 of file cc2538.h.

◆ IOC_PD4_SEL

#define IOC_PD4_SEL   ( *(cc2538_reg_t*)0x400d4070 )

Peripheral select control for PD4.

Definition at line 607 of file cc2538.h.

◆ IOC_PD5_OVER

#define IOC_PD5_OVER   ( *(cc2538_reg_t*)0x400d40f4 )

Override configuration register for PD5.

Definition at line 640 of file cc2538.h.

◆ IOC_PD5_SEL

#define IOC_PD5_SEL   ( *(cc2538_reg_t*)0x400d4074 )

Peripheral select control for PD5.

Definition at line 608 of file cc2538.h.

◆ IOC_PD6_OVER

#define IOC_PD6_OVER   ( *(cc2538_reg_t*)0x400d40f8 )

Override configuration register for PD6.

Definition at line 641 of file cc2538.h.

◆ IOC_PD6_SEL

#define IOC_PD6_SEL   ( *(cc2538_reg_t*)0x400d4078 )

Peripheral select control for PD6.

Definition at line 609 of file cc2538.h.

◆ IOC_PD7_OVER

#define IOC_PD7_OVER   ( *(cc2538_reg_t*)0x400d40fc )

Override configuration register for PD7.

Definition at line 642 of file cc2538.h.

◆ IOC_PD7_SEL

#define IOC_PD7_SEL   ( *(cc2538_reg_t*)0x400d407c )

Peripheral select control for PD7.

Definition at line 610 of file cc2538.h.

◆ IOC_SSIFSSIN_SSI0

#define IOC_SSIFSSIN_SSI0   ( *(cc2538_reg_t*)0x400d4114 )

Pin selection for SSI0 FSSIN.

Definition at line 648 of file cc2538.h.

◆ IOC_SSIFSSIN_SSI1

#define IOC_SSIFSSIN_SSI1   ( *(cc2538_reg_t*)0x400d4124 )

Pin selection for SSI1 FSSIN.

Definition at line 652 of file cc2538.h.

◆ IOC_SSIRXD_SSI0

#define IOC_SSIRXD_SSI0   ( *(cc2538_reg_t*)0x400d4110 )

Pin selection for SSI0 RX.

Definition at line 647 of file cc2538.h.

◆ IOC_SSIRXD_SSI1

#define IOC_SSIRXD_SSI1   ( *(cc2538_reg_t*)0x400d4120 )

Pin selection for SSI1 RX.

Definition at line 651 of file cc2538.h.

◆ IOC_UARTCTS_UART1

#define IOC_UARTCTS_UART1   ( *(cc2538_reg_t*)0x400d4104 )

Pin selection for UART1 CTS.

Definition at line 644 of file cc2538.h.

◆ IOC_UARTRXD_UART0

#define IOC_UARTRXD_UART0   ( *(cc2538_reg_t*)0x400d4100 )

Pin selection for UART0 RX.

Definition at line 643 of file cc2538.h.

◆ IOC_UARTRXD_UART1

#define IOC_UARTRXD_UART1   ( *(cc2538_reg_t*)0x400d4108 )

Pin selection for UART1 RX.

Definition at line 645 of file cc2538.h.

◆ PKA_ALENGTH

#define PKA_ALENGTH   ( *(cc2538_reg_t*)0x44004010 )

PKA vector A length.

Definition at line 776 of file cc2538.h.

◆ PKA_APTR

#define PKA_APTR   ( *(cc2538_reg_t*)0x44004000 )

PKA vector A address.

Definition at line 772 of file cc2538.h.

◆ PKA_BLENGTH

#define PKA_BLENGTH   ( *(cc2538_reg_t*)0x44004014 )

PKA vector B length.

Definition at line 777 of file cc2538.h.

◆ PKA_BPTR

#define PKA_BPTR   ( *(cc2538_reg_t*)0x44004004 )

PKA vector B address.

Definition at line 773 of file cc2538.h.

◆ PKA_COMPARE

#define PKA_COMPARE   ( *(cc2538_reg_t*)0x44004020 )

PKA compare result.

Definition at line 780 of file cc2538.h.

◆ PKA_CPTR

#define PKA_CPTR   ( *(cc2538_reg_t*)0x44004008 )

PKA vector C address.

Definition at line 774 of file cc2538.h.

◆ PKA_DIVMSW

#define PKA_DIVMSW   ( *(cc2538_reg_t*)0x44004028 )

PKA most-significant-word of divide remainder.

Definition at line 782 of file cc2538.h.

◆ PKA_DPTR

#define PKA_DPTR   ( *(cc2538_reg_t*)0x4400400c )

PKA vector D address.

Definition at line 775 of file cc2538.h.

◆ PKA_FUNCTION

#define PKA_FUNCTION   ( *(cc2538_reg_t*)0x4400401c )

PKA function.

Definition at line 779 of file cc2538.h.

◆ PKA_MSW

#define PKA_MSW   ( *(cc2538_reg_t*)0x44004024 )

PKA most-significant-word of result vector.

Definition at line 781 of file cc2538.h.

◆ PKA_OPTIONS

#define PKA_OPTIONS   ( *(cc2538_reg_t*)0x440040f4 )

PKA hardware options register.

Definition at line 784 of file cc2538.h.

◆ PKA_REVISION

#define PKA_REVISION   ( *(cc2538_reg_t*)0x440040fc )

PKA hardware revision register.

Definition at line 786 of file cc2538.h.

◆ PKA_SEQ_CTRL

#define PKA_SEQ_CTRL   ( *(cc2538_reg_t*)0x440040c8 )

PKA sequencer control and status register.

Definition at line 783 of file cc2538.h.

◆ PKA_SHIFT

#define PKA_SHIFT   ( *(cc2538_reg_t*)0x44004018 )

PKA bit shift value.

Definition at line 778 of file cc2538.h.

◆ PKA_SW_REV

#define PKA_SW_REV   ( *(cc2538_reg_t*)0x440040f8 )

PKA firmware revision and capabilities register.

Definition at line 785 of file cc2538.h.

◆ RCOSC16M_FREQ

#define RCOSC16M_FREQ   16000000U

16 MHz internal RC oscillator frequency

Definition at line 801 of file cc2538.h.

◆ RCOSC32K_FREQ

#define RCOSC32K_FREQ   32753U

32 KHz internal RC oscillator frequency

Definition at line 804 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR0

#define RFCORE_FFSM_EXT_ADDR0   ( *(cc2538_reg_t*)0x400885a8 )

RF Local address information.

Definition at line 338 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR1

#define RFCORE_FFSM_EXT_ADDR1   ( *(cc2538_reg_t*)0x400885ac )

RF Local address information.

Definition at line 339 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR2

#define RFCORE_FFSM_EXT_ADDR2   ( *(cc2538_reg_t*)0x400885b0 )

RF Local address information.

Definition at line 340 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR3

#define RFCORE_FFSM_EXT_ADDR3   ( *(cc2538_reg_t*)0x400885b4 )

RF Local address information.

Definition at line 341 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR4

#define RFCORE_FFSM_EXT_ADDR4   ( *(cc2538_reg_t*)0x400885b8 )

RF Local address information.

Definition at line 342 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR5

#define RFCORE_FFSM_EXT_ADDR5   ( *(cc2538_reg_t*)0x400885bc )

RF Local address information.

Definition at line 343 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR6

#define RFCORE_FFSM_EXT_ADDR6   ( *(cc2538_reg_t*)0x400885c0 )

RF Local address information.

Definition at line 344 of file cc2538.h.

◆ RFCORE_FFSM_EXT_ADDR7

#define RFCORE_FFSM_EXT_ADDR7   ( *(cc2538_reg_t*)0x400885c4 )

RF Local address information.

Definition at line 345 of file cc2538.h.

◆ RFCORE_FFSM_PAN_ID0

#define RFCORE_FFSM_PAN_ID0   ( *(cc2538_reg_t*)0x400885c8 )

RF Local address information.

Definition at line 346 of file cc2538.h.

◆ RFCORE_FFSM_PAN_ID1

#define RFCORE_FFSM_PAN_ID1   ( *(cc2538_reg_t*)0x400885cc )

RF Local address information.

Definition at line 347 of file cc2538.h.

◆ RFCORE_FFSM_SHORT_ADDR0

#define RFCORE_FFSM_SHORT_ADDR0   ( *(cc2538_reg_t*)0x400885d0 )

RF Local address information.

Definition at line 348 of file cc2538.h.

◆ RFCORE_FFSM_SHORT_ADDR1

#define RFCORE_FFSM_SHORT_ADDR1   ( *(cc2538_reg_t*)0x400885d4 )

RF Local address information.

Definition at line 349 of file cc2538.h.

◆ RFCORE_FFSM_SRCEXTPENDEN0

#define RFCORE_FFSM_SRCEXTPENDEN0   ( *(cc2538_reg_t*)0x40088590 )

RF Source address matching control.

Definition at line 332 of file cc2538.h.

◆ RFCORE_FFSM_SRCEXTPENDEN1

#define RFCORE_FFSM_SRCEXTPENDEN1   ( *(cc2538_reg_t*)0x40088594 )

RF Source address matching control.

Definition at line 333 of file cc2538.h.

◆ RFCORE_FFSM_SRCEXTPENDEN2

#define RFCORE_FFSM_SRCEXTPENDEN2   ( *(cc2538_reg_t*)0x40088598 )

RF Source address matching control.

Definition at line 334 of file cc2538.h.

◆ RFCORE_FFSM_SRCRESINDEX

#define RFCORE_FFSM_SRCRESINDEX   ( *(cc2538_reg_t*)0x4008858c )

RF Source address matching result.

Definition at line 331 of file cc2538.h.

◆ RFCORE_FFSM_SRCRESMASK0

#define RFCORE_FFSM_SRCRESMASK0   ( *(cc2538_reg_t*)0x40088580 )

RF Source address matching result.

Definition at line 328 of file cc2538.h.

◆ RFCORE_FFSM_SRCRESMASK1

#define RFCORE_FFSM_SRCRESMASK1   ( *(cc2538_reg_t*)0x40088584 )

RF Source address matching result.

Definition at line 329 of file cc2538.h.

◆ RFCORE_FFSM_SRCRESMASK2

#define RFCORE_FFSM_SRCRESMASK2   ( *(cc2538_reg_t*)0x40088588 )

RF Source address matching result.

Definition at line 330 of file cc2538.h.

◆ RFCORE_FFSM_SRCSHORTPENDEN0

#define RFCORE_FFSM_SRCSHORTPENDEN0   ( *(cc2538_reg_t*)0x4008859c )

RF Source address matching control.

Definition at line 335 of file cc2538.h.

◆ RFCORE_FFSM_SRCSHORTPENDEN1

#define RFCORE_FFSM_SRCSHORTPENDEN1   ( *(cc2538_reg_t*)0x400885a0 )

RF Source address matching control.

Definition at line 336 of file cc2538.h.

◆ RFCORE_FFSM_SRCSHORTPENDEN2

#define RFCORE_FFSM_SRCSHORTPENDEN2   ( *(cc2538_reg_t*)0x400885a4 )

RF Source address matching control.

Definition at line 337 of file cc2538.h.

◆ RFCORE_SFR_MTCSPCFG

#define RFCORE_SFR_MTCSPCFG   ( *(cc2538_reg_t*)0x40088800 )

RF MAC Timer event configuration.

Definition at line 422 of file cc2538.h.

◆ RFCORE_SFR_MTCTRL

#define RFCORE_SFR_MTCTRL   ( *(cc2538_reg_t*)0x40088804 )

RF MAC Timer control register.

Definition at line 423 of file cc2538.h.

◆ RFCORE_SFR_MTIRQF

#define RFCORE_SFR_MTIRQF   ( *(cc2538_reg_t*)0x4008880c )

RF MAC Timer interrupt flags.

Definition at line 425 of file cc2538.h.

◆ RFCORE_SFR_MTIRQM

#define RFCORE_SFR_MTIRQM   ( *(cc2538_reg_t*)0x40088808 )

RF MAC Timer interrupt mask.

Definition at line 424 of file cc2538.h.

◆ RFCORE_SFR_MTM0

#define RFCORE_SFR_MTM0   ( *(cc2538_reg_t*)0x40088814 )

RF MAC Timer multiplexed register 0.

Definition at line 427 of file cc2538.h.

◆ RFCORE_SFR_MTM1

#define RFCORE_SFR_MTM1   ( *(cc2538_reg_t*)0x40088818 )

RF MAC Timer multiplexed register 1.

Definition at line 428 of file cc2538.h.

◆ RFCORE_SFR_MTMOVF0

#define RFCORE_SFR_MTMOVF0   ( *(cc2538_reg_t*)0x40088824 )

RF MAC Timer multiplexed overflow register 0.

Definition at line 431 of file cc2538.h.

◆ RFCORE_SFR_MTMOVF1

#define RFCORE_SFR_MTMOVF1   ( *(cc2538_reg_t*)0x40088820 )

RF MAC Timer multiplexed overflow register 1.

Definition at line 430 of file cc2538.h.

◆ RFCORE_SFR_MTMOVF2

#define RFCORE_SFR_MTMOVF2   ( *(cc2538_reg_t*)0x4008881c )

RF MAC Timer multiplexed overflow register 2.

Definition at line 429 of file cc2538.h.

◆ RFCORE_SFR_MTMSEL

#define RFCORE_SFR_MTMSEL   ( *(cc2538_reg_t*)0x40088810 )

RF MAC Timer multiplex select.

Definition at line 426 of file cc2538.h.

◆ RFCORE_SFR_RFDATA

#define RFCORE_SFR_RFDATA   ( *(cc2538_reg_t*)0x40088828 )

RF Tx/Rx FIFO.

Definition at line 432 of file cc2538.h.

◆ RFCORE_SFR_RFERRF

#define RFCORE_SFR_RFERRF   ( *(cc2538_reg_t*)0x4008882c )

RF error interrupt flags.

Definition at line 433 of file cc2538.h.

◆ RFCORE_SFR_RFIRQF0

#define RFCORE_SFR_RFIRQF0   ( *(cc2538_reg_t*)0x40088834 )

RF interrupt flags.

Definition at line 435 of file cc2538.h.

◆ RFCORE_SFR_RFIRQF1

#define RFCORE_SFR_RFIRQF1   ( *(cc2538_reg_t*)0x40088830 )

RF interrupt flags.

Definition at line 434 of file cc2538.h.

◆ RFCORE_SFR_RFST

#define RFCORE_SFR_RFST   ( *(cc2538_reg_t*)0x40088838 )

RF CSMA-CA/strobe processor.

Definition at line 436 of file cc2538.h.

◆ RFCORE_XREG_ADCTEST0

#define RFCORE_XREG_ADCTEST0   ( *(cc2538_reg_t*)0x400886d4 )

RF ADC tuning.

Definition at line 401 of file cc2538.h.

◆ RFCORE_XREG_ADCTEST1

#define RFCORE_XREG_ADCTEST1   ( *(cc2538_reg_t*)0x400886d8 )

RF ADC tuning.

Definition at line 402 of file cc2538.h.

◆ RFCORE_XREG_ADCTEST2

#define RFCORE_XREG_ADCTEST2   ( *(cc2538_reg_t*)0x400886dc )

RF ADC tuning.

Definition at line 403 of file cc2538.h.

◆ RFCORE_XREG_AGCCTRL0

#define RFCORE_XREG_AGCCTRL0   ( *(cc2538_reg_t*)0x400886c4 )

RF AGC dynamic range control.

Definition at line 397 of file cc2538.h.

◆ RFCORE_XREG_AGCCTRL1

#define RFCORE_XREG_AGCCTRL1   ( *(cc2538_reg_t*)0x400886c8 )

RF AGC reference level.

Definition at line 398 of file cc2538.h.

◆ RFCORE_XREG_AGCCTRL2

#define RFCORE_XREG_AGCCTRL2   ( *(cc2538_reg_t*)0x400886cc )

RF AGC gain override.

Definition at line 399 of file cc2538.h.

◆ RFCORE_XREG_AGCCTRL3

#define RFCORE_XREG_AGCCTRL3   ( *(cc2538_reg_t*)0x400886d0 )

RF AGC control.

Definition at line 400 of file cc2538.h.

◆ RFCORE_XREG_ATEST

#define RFCORE_XREG_ATEST   ( *(cc2538_reg_t*)0x400886f4 )

RF Analog test control.

Definition at line 409 of file cc2538.h.

◆ RFCORE_XREG_CCACTRL0

#define RFCORE_XREG_CCACTRL0   ( *(cc2538_reg_t*)0x40088658 )

RF CCA threshold.

Definition at line 372 of file cc2538.h.

◆ RFCORE_XREG_CCACTRL1

#define RFCORE_XREG_CCACTRL1   ( *(cc2538_reg_t*)0x4008865c )

RF Other CCA Options.

Definition at line 373 of file cc2538.h.

◆ RFCORE_XREG_CSPCTRL

#define RFCORE_XREG_CSPCTRL   ( *(cc2538_reg_t*)0x40088780 )

RF CSP control bit.

Definition at line 412 of file cc2538.h.

◆ RFCORE_XREG_CSPSTAT

#define RFCORE_XREG_CSPSTAT   ( *(cc2538_reg_t*)0x40088784 )

RF CSP status register.

Definition at line 413 of file cc2538.h.

◆ RFCORE_XREG_CSPT

#define RFCORE_XREG_CSPT   ( *(cc2538_reg_t*)0x40088794 )

RF CSP T data register.

Definition at line 417 of file cc2538.h.

◆ RFCORE_XREG_CSPX

#define RFCORE_XREG_CSPX   ( *(cc2538_reg_t*)0x40088788 )

RF CSP X data register.

Definition at line 414 of file cc2538.h.

◆ RFCORE_XREG_CSPY

#define RFCORE_XREG_CSPY   ( *(cc2538_reg_t*)0x4008878c )

RF CSP Y data register.

Definition at line 415 of file cc2538.h.

◆ RFCORE_XREG_CSPZ

#define RFCORE_XREG_CSPZ   ( *(cc2538_reg_t*)0x40088790 )

RF CSP Z data register.

Definition at line 416 of file cc2538.h.

◆ RFCORE_XREG_DACTEST0

#define RFCORE_XREG_DACTEST0   ( *(cc2538_reg_t*)0x400886e8 )

RF DAC override value.

Definition at line 406 of file cc2538.h.

◆ RFCORE_XREG_DACTEST1

#define RFCORE_XREG_DACTEST1   ( *(cc2538_reg_t*)0x400886ec )

RF DAC override value.

Definition at line 407 of file cc2538.h.

◆ RFCORE_XREG_DACTEST2

#define RFCORE_XREG_DACTEST2   ( *(cc2538_reg_t*)0x400886f0 )

RF DAC test setting.

Definition at line 408 of file cc2538.h.

◆ RFCORE_XREG_FIFOPCTRL

#define RFCORE_XREG_FIFOPCTRL   ( *(cc2538_reg_t*)0x40088650 )

RF FIFOP threshold.

Definition at line 370 of file cc2538.h.

◆ RFCORE_XREG_FREQCTRL

#define RFCORE_XREG_FREQCTRL   ( *(cc2538_reg_t*)0x4008863c )

RF Controls the RF frequency.

Definition at line 365 of file cc2538.h.

◆ RFCORE_XREG_FREQEST

#define RFCORE_XREG_FREQEST   ( *(cc2538_reg_t*)0x400886a8 )

RF Estimated RF frequency offset.

Definition at line 390 of file cc2538.h.

◆ RFCORE_XREG_FREQTUNE

#define RFCORE_XREG_FREQTUNE   ( *(cc2538_reg_t*)0x40088638 )

RF Crystal oscillator frequency tuning.

Definition at line 364 of file cc2538.h.

◆ RFCORE_XREG_FRMCTRL0

#define RFCORE_XREG_FRMCTRL0   ( *(cc2538_reg_t*)0x40088624 )

RF Frame handling.

Definition at line 359 of file cc2538.h.

◆ RFCORE_XREG_FRMCTRL1

#define RFCORE_XREG_FRMCTRL1   ( *(cc2538_reg_t*)0x40088628 )

RF Frame handling.

Definition at line 360 of file cc2538.h.

◆ RFCORE_XREG_FRMFILT0

#define RFCORE_XREG_FRMFILT0   ( *(cc2538_reg_t*)0x40088600 )

RF Frame Filter 0.

Definition at line 350 of file cc2538.h.

◆ RFCORE_XREG_FRMFILT1

#define RFCORE_XREG_FRMFILT1   ( *(cc2538_reg_t*)0x40088604 )

RF Frame Filter 1.

Definition at line 351 of file cc2538.h.

◆ RFCORE_XREG_FSCAL0

#define RFCORE_XREG_FSCAL0   ( *(cc2538_reg_t*)0x400886b4 )

RF Tune frequency calibration.

Definition at line 393 of file cc2538.h.

◆ RFCORE_XREG_FSCAL1

#define RFCORE_XREG_FSCAL1   ( *(cc2538_reg_t*)0x400886b8 )

RF Tune frequency calibration.

Definition at line 394 of file cc2538.h.

◆ RFCORE_XREG_FSCAL2

#define RFCORE_XREG_FSCAL2   ( *(cc2538_reg_t*)0x400886bc )

RF Tune frequency calibration.

Definition at line 395 of file cc2538.h.

◆ RFCORE_XREG_FSCAL3

#define RFCORE_XREG_FSCAL3   ( *(cc2538_reg_t*)0x400886c0 )

RF Tune frequency calibration.

Definition at line 396 of file cc2538.h.

◆ RFCORE_XREG_FSCTRL

#define RFCORE_XREG_FSCTRL   ( *(cc2538_reg_t*)0x400886b0 )

RF Tune frequency synthesizer.

Definition at line 392 of file cc2538.h.

◆ RFCORE_XREG_FSMCTRL

#define RFCORE_XREG_FSMCTRL   ( *(cc2538_reg_t*)0x40088654 )

RF FSM options.

Definition at line 371 of file cc2538.h.

◆ RFCORE_XREG_FSMSTAT0

#define RFCORE_XREG_FSMSTAT0   ( *(cc2538_reg_t*)0x40088648 )

RF Radio status register.

Definition at line 368 of file cc2538.h.

◆ RFCORE_XREG_FSMSTAT1

#define RFCORE_XREG_FSMSTAT1   ( *(cc2538_reg_t*)0x4008864c )

RF Radio status register.

Definition at line 369 of file cc2538.h.

◆ RFCORE_XREG_MDMCTRL0

#define RFCORE_XREG_MDMCTRL0   ( *(cc2538_reg_t*)0x400886a0 )

RF Controls modem.

Definition at line 388 of file cc2538.h.

◆ RFCORE_XREG_MDMCTRL1

#define RFCORE_XREG_MDMCTRL1   ( *(cc2538_reg_t*)0x400886a4 )

RF Controls modem.

Definition at line 389 of file cc2538.h.

◆ RFCORE_XREG_MDMTEST0

#define RFCORE_XREG_MDMTEST0   ( *(cc2538_reg_t*)0x400886e0 )

RF Test register for modem.

Definition at line 404 of file cc2538.h.

◆ RFCORE_XREG_MDMTEST1

#define RFCORE_XREG_MDMTEST1   ( *(cc2538_reg_t*)0x400886e4 )

RF Test Register for Modem.

Definition at line 405 of file cc2538.h.

◆ RFCORE_XREG_PTEST0

#define RFCORE_XREG_PTEST0   ( *(cc2538_reg_t*)0x400886f8 )

RF Override power-down register.

Definition at line 410 of file cc2538.h.

◆ RFCORE_XREG_PTEST1

#define RFCORE_XREG_PTEST1   ( *(cc2538_reg_t*)0x400886fc )

RF Override power-down register.

Definition at line 411 of file cc2538.h.

◆ RFCORE_XREG_RFC_OBS_CTRL0

#define RFCORE_XREG_RFC_OBS_CTRL0   ( *(cc2538_reg_t*)0x400887ac )

RF observation mux control.

Definition at line 418 of file cc2538.h.

◆ RFCORE_XREG_RFC_OBS_CTRL1

#define RFCORE_XREG_RFC_OBS_CTRL1   ( *(cc2538_reg_t*)0x400887b0 )

RF observation mux control.

Definition at line 419 of file cc2538.h.

◆ RFCORE_XREG_RFC_OBS_CTRL2

#define RFCORE_XREG_RFC_OBS_CTRL2   ( *(cc2538_reg_t*)0x400887b4 )

RF observation mux control.

Definition at line 420 of file cc2538.h.

◆ RFCORE_XREG_RFERRM

#define RFCORE_XREG_RFERRM   ( *(cc2538_reg_t*)0x40088694 )

RF error interrupt mask.

Definition at line 386 of file cc2538.h.

◆ RFCORE_XREG_RFIRQM0

#define RFCORE_XREG_RFIRQM0   ( *(cc2538_reg_t*)0x4008868c )

RF interrupt masks.

Definition at line 384 of file cc2538.h.

◆ RFCORE_XREG_RFIRQM1

#define RFCORE_XREG_RFIRQM1   ( *(cc2538_reg_t*)0x40088690 )

RF interrupt masks.

Definition at line 385 of file cc2538.h.

◆ RFCORE_XREG_RFRND

#define RFCORE_XREG_RFRND   ( *(cc2538_reg_t*)0x4008869c )

RF Random data.

Definition at line 387 of file cc2538.h.

◆ RFCORE_XREG_RSSI

#define RFCORE_XREG_RSSI   ( *(cc2538_reg_t*)0x40088660 )

RF RSSI status register.

Definition at line 374 of file cc2538.h.

◆ RFCORE_XREG_RSSISTAT

#define RFCORE_XREG_RSSISTAT   ( *(cc2538_reg_t*)0x40088664 )

RF RSSI valid status register.

Definition at line 375 of file cc2538.h.

◆ RFCORE_XREG_RXCTRL

#define RFCORE_XREG_RXCTRL   ( *(cc2538_reg_t*)0x400886ac )

RF Tune receive section.

Definition at line 391 of file cc2538.h.

◆ RFCORE_XREG_RXENABLE

#define RFCORE_XREG_RXENABLE   ( *(cc2538_reg_t*)0x4008862c )

RF RX enabling.

Definition at line 361 of file cc2538.h.

◆ RFCORE_XREG_RXFIFOCNT

#define RFCORE_XREG_RXFIFOCNT   ( *(cc2538_reg_t*)0x4008866c )

RF Number of bytes in RX FIFO.

Definition at line 377 of file cc2538.h.

◆ RFCORE_XREG_RXFIRST

#define RFCORE_XREG_RXFIRST   ( *(cc2538_reg_t*)0x40088668 )

RF First byte in RX FIFO.

Definition at line 376 of file cc2538.h.

◆ RFCORE_XREG_RXFIRST_PTR

#define RFCORE_XREG_RXFIRST_PTR   ( *(cc2538_reg_t*)0x40088674 )

RF RX FIFO pointer.

Definition at line 379 of file cc2538.h.

◆ RFCORE_XREG_RXLAST_PTR

#define RFCORE_XREG_RXLAST_PTR   ( *(cc2538_reg_t*)0x40088678 )

RF RX FIFO pointer.

Definition at line 380 of file cc2538.h.

◆ RFCORE_XREG_RXMASKCLR

#define RFCORE_XREG_RXMASKCLR   ( *(cc2538_reg_t*)0x40088634 )

RF RX disabling.

Definition at line 363 of file cc2538.h.

◆ RFCORE_XREG_RXMASKSET

#define RFCORE_XREG_RXMASKSET   ( *(cc2538_reg_t*)0x40088630 )

RF RX enabling.

Definition at line 362 of file cc2538.h.

◆ RFCORE_XREG_RXP1_PTR

#define RFCORE_XREG_RXP1_PTR   ( *(cc2538_reg_t*)0x4008867c )

RF RX FIFO pointer.

Definition at line 381 of file cc2538.h.

◆ RFCORE_XREG_SRCEXTEN0

#define RFCORE_XREG_SRCEXTEN0   ( *(cc2538_reg_t*)0x40088618 )

RF Extended address matching.

Definition at line 356 of file cc2538.h.

◆ RFCORE_XREG_SRCEXTEN1

#define RFCORE_XREG_SRCEXTEN1   ( *(cc2538_reg_t*)0x4008861c )

RF Extended address matching.

Definition at line 357 of file cc2538.h.

◆ RFCORE_XREG_SRCEXTEN2

#define RFCORE_XREG_SRCEXTEN2   ( *(cc2538_reg_t*)0x40088620 )

RF Extended address matching.

Definition at line 358 of file cc2538.h.

◆ RFCORE_XREG_SRCMATCH

#define RFCORE_XREG_SRCMATCH   ( *(cc2538_reg_t*)0x40088608 )

RF Source address matching and pending bits.

Definition at line 352 of file cc2538.h.

◆ RFCORE_XREG_SRCSHORTEN0

#define RFCORE_XREG_SRCSHORTEN0   ( *(cc2538_reg_t*)0x4008860c )

RF Short address matching.

Definition at line 353 of file cc2538.h.

◆ RFCORE_XREG_SRCSHORTEN1

#define RFCORE_XREG_SRCSHORTEN1   ( *(cc2538_reg_t*)0x40088610 )

RF Short address matching.

Definition at line 354 of file cc2538.h.

◆ RFCORE_XREG_SRCSHORTEN2

#define RFCORE_XREG_SRCSHORTEN2   ( *(cc2538_reg_t*)0x40088614 )

RF Short address matching.

Definition at line 355 of file cc2538.h.

◆ RFCORE_XREG_TXCTRL

#define RFCORE_XREG_TXCTRL   ( *(cc2538_reg_t*)0x40088644 )

RF Controls the TX settings.

Definition at line 367 of file cc2538.h.

◆ RFCORE_XREG_TXFIFOCNT

#define RFCORE_XREG_TXFIFOCNT   ( *(cc2538_reg_t*)0x40088670 )

RF Number of bytes in TX FIFO.

Definition at line 378 of file cc2538.h.

◆ RFCORE_XREG_TXFILTCFG

#define RFCORE_XREG_TXFILTCFG   ( *(cc2538_reg_t*)0x400887e8 )

RF TX filter configuration.

Definition at line 421 of file cc2538.h.

◆ RFCORE_XREG_TXFIRST_PTR

#define RFCORE_XREG_TXFIRST_PTR   ( *(cc2538_reg_t*)0x40088684 )

RF TX FIFO pointer.

Definition at line 382 of file cc2538.h.

◆ RFCORE_XREG_TXLAST_PTR

#define RFCORE_XREG_TXLAST_PTR   ( *(cc2538_reg_t*)0x40088688 )

RF TX FIFO pointer.

Definition at line 383 of file cc2538.h.

◆ RFCORE_XREG_TXPOWER

#define RFCORE_XREG_TXPOWER   ( *(cc2538_reg_t*)0x40088640 )

RF Controls the output power.

Definition at line 366 of file cc2538.h.

◆ SMWDTHROSC_ST0

#define SMWDTHROSC_ST0   ( *(cc2538_reg_t*)0x400d5040 )

Sleep Timer 0 count and compare.

Definition at line 665 of file cc2538.h.

◆ SMWDTHROSC_ST1

#define SMWDTHROSC_ST1   ( *(cc2538_reg_t*)0x400d5044 )

Sleep Timer 1 count and compare.

Definition at line 666 of file cc2538.h.

◆ SMWDTHROSC_ST2

#define SMWDTHROSC_ST2   ( *(cc2538_reg_t*)0x400d5048 )

Sleep Timer 2 count and compare.

Definition at line 667 of file cc2538.h.

◆ SMWDTHROSC_ST3

#define SMWDTHROSC_ST3   ( *(cc2538_reg_t*)0x400d504c )

Sleep Timer 3 count and compare.

Definition at line 668 of file cc2538.h.

◆ SMWDTHROSC_STCC

#define SMWDTHROSC_STCC   ( *(cc2538_reg_t*)0x400d5054 )

Sleep Timer Capture control.

Definition at line 670 of file cc2538.h.

◆ SMWDTHROSC_STCS

#define SMWDTHROSC_STCS   ( *(cc2538_reg_t*)0x400d5058 )

Sleep Timer Capture status.

Definition at line 671 of file cc2538.h.

◆ SMWDTHROSC_STCV0

#define SMWDTHROSC_STCV0   ( *(cc2538_reg_t*)0x400d505c )

Sleep Timer Capture value byte 0.

Definition at line 672 of file cc2538.h.

◆ SMWDTHROSC_STCV1

#define SMWDTHROSC_STCV1   ( *(cc2538_reg_t*)0x400d5060 )

Sleep Timer Capture value byte 1.

Definition at line 673 of file cc2538.h.

◆ SMWDTHROSC_STCV2

#define SMWDTHROSC_STCV2   ( *(cc2538_reg_t*)0x400d5064 )

Sleep Timer Capture value byte 2.

Definition at line 674 of file cc2538.h.

◆ SMWDTHROSC_STCV3

#define SMWDTHROSC_STCV3   ( *(cc2538_reg_t*)0x400d5068 )

Sleep Timer Capture value byte 3.

Definition at line 675 of file cc2538.h.

◆ SMWDTHROSC_STLOAD

#define SMWDTHROSC_STLOAD   ( *(cc2538_reg_t*)0x400d5050 )

Sleep Timer load status.

Definition at line 669 of file cc2538.h.

◆ SMWDTHROSC_WDCTL

#define SMWDTHROSC_WDCTL   ( *(cc2538_reg_t*)0x400d5000 )

Watchdog Timer Control.

Definition at line 664 of file cc2538.h.

◆ SSI0_CC

#define SSI0_CC   ( *(cc2538_reg_t*)0x40008fc8 )

SSI0 clock configuration.

Definition at line 150 of file cc2538.h.

◆ SSI0_CPSR

#define SSI0_CPSR   ( *(cc2538_reg_t*)0x40008010 )

SSI0 Clock Register.

Definition at line 144 of file cc2538.h.

◆ SSI0_CR0

#define SSI0_CR0   ( *(cc2538_reg_t*)0x40008000 )

SSI0 Control Register 0.

Definition at line 140 of file cc2538.h.

◆ SSI0_CR1

#define SSI0_CR1   ( *(cc2538_reg_t*)0x40008004 )

SSI0 Control Register 1.

Definition at line 141 of file cc2538.h.

◆ SSI0_DMACTL

#define SSI0_DMACTL   ( *(cc2538_reg_t*)0x40008024 )

SSI0 uDMA Control Register.

Definition at line 149 of file cc2538.h.

◆ SSI0_DR

#define SSI0_DR   ( *(cc2538_reg_t*)0x40008008 )

SSI0 Data register.

Definition at line 142 of file cc2538.h.

◆ SSI0_ICR

#define SSI0_ICR   ( *(cc2538_reg_t*)0x40008020 )

SSI0 Interrupt Clear Register.

Definition at line 148 of file cc2538.h.

◆ SSI0_IM

#define SSI0_IM   ( *(cc2538_reg_t*)0x40008014 )

SSI0 Interrupt Mask register.

Definition at line 145 of file cc2538.h.

◆ SSI0_MIS

#define SSI0_MIS   ( *(cc2538_reg_t*)0x4000801c )

SSI0 Masked Interrupt Status register.

Definition at line 147 of file cc2538.h.

◆ SSI0_RIS

#define SSI0_RIS   ( *(cc2538_reg_t*)0x40008018 )

SSI0 Raw Interrupt Status register.

Definition at line 146 of file cc2538.h.

◆ SSI0_SR

#define SSI0_SR   ( *(cc2538_reg_t*)0x4000800c )

SSI0 FIFO/busy Status Register.

Definition at line 143 of file cc2538.h.

◆ SSI1_CC

#define SSI1_CC   ( *(cc2538_reg_t*)0x40009fc8 )

SSI1 clock configuration.

Definition at line 161 of file cc2538.h.

◆ SSI1_CPSR

#define SSI1_CPSR   ( *(cc2538_reg_t*)0x40009010 )

SSI1 Clock Register.

Definition at line 155 of file cc2538.h.

◆ SSI1_CR0

#define SSI1_CR0   ( *(cc2538_reg_t*)0x40009000 )

SSI1 Control Register 0.

Definition at line 151 of file cc2538.h.

◆ SSI1_CR1

#define SSI1_CR1   ( *(cc2538_reg_t*)0x40009004 )

SSI1 Control Register 1.

Definition at line 152 of file cc2538.h.

◆ SSI1_DMACTL

#define SSI1_DMACTL   ( *(cc2538_reg_t*)0x40009024 )

SSI1 uDMA Control Register.

Definition at line 160 of file cc2538.h.

◆ SSI1_DR

#define SSI1_DR   ( *(cc2538_reg_t*)0x40009008 )

SSI1 Data register.

Definition at line 153 of file cc2538.h.

◆ SSI1_ICR

#define SSI1_ICR   ( *(cc2538_reg_t*)0x40009020 )

SSI1 Interrupt Clear Register.

Definition at line 159 of file cc2538.h.

◆ SSI1_IM

#define SSI1_IM   ( *(cc2538_reg_t*)0x40009014 )

SSI1 Interrupt Mask register.

Definition at line 156 of file cc2538.h.

◆ SSI1_MIS

#define SSI1_MIS   ( *(cc2538_reg_t*)0x4000901c )

SSI1 Masked Interrupt Status register.

Definition at line 158 of file cc2538.h.

◆ SSI1_RIS

#define SSI1_RIS   ( *(cc2538_reg_t*)0x40009018 )

SSI1 Raw Interrupt Status register.

Definition at line 157 of file cc2538.h.

◆ SSI1_SR

#define SSI1_SR   ( *(cc2538_reg_t*)0x4000900c )

SSI1 FIFO/busy Status Register.

Definition at line 154 of file cc2538.h.

◆ SYS_CTRL_CLD

#define SYS_CTRL_CLD   ( *(cc2538_reg_t*)0x400d2080 )

This register controls the clock loss detection feature.

Definition at line 566 of file cc2538.h.

◆ SYS_CTRL_CLOCK_CTRL

#define SYS_CTRL_CLOCK_CTRL   ( *(cc2538_reg_t*)0x400d2000 )

Clock control register.

Definition at line 541 of file cc2538.h.

◆ SYS_CTRL_CLOCK_STA

#define SYS_CTRL_CLOCK_STA   ( *(cc2538_reg_t*)0x400d2004 )

Clock status register.

Definition at line 542 of file cc2538.h.

◆ SYS_CTRL_DCGCGPT

#define SYS_CTRL_DCGCGPT   ( *(cc2538_reg_t*)0x400d2010 )

Module clocks for GPT[3:0] when the CPU is in PM0.

Definition at line 545 of file cc2538.h.

◆ SYS_CTRL_DCGCI2C

#define SYS_CTRL_DCGCI2C   ( *(cc2538_reg_t*)0x400d2040 )

Module clocks for I2C when the CPU is in PM0.

Definition at line 557 of file cc2538.h.

◆ SYS_CTRL_DCGCRFC

#define SYS_CTRL_DCGCRFC   ( *(cc2538_reg_t*)0x400d20b0 )

This register defines the module clocks for RF CORE when the CPU is in PM0.

Definition at line 571 of file cc2538.h.

◆ SYS_CTRL_DCGCSEC

#define SYS_CTRL_DCGCSEC   ( *(cc2538_reg_t*)0x400d2050 )

Module clocks for the security module when the CPU is in PM0.

Definition at line 561 of file cc2538.h.

◆ SYS_CTRL_DCGCSSI

#define SYS_CTRL_DCGCSSI   ( *(cc2538_reg_t*)0x400d2020 )

Module clocks for SSI[1:0] when the CPU is in PM0.

Definition at line 549 of file cc2538.h.

◆ SYS_CTRL_DCGCUART

#define SYS_CTRL_DCGCUART   ( *(cc2538_reg_t*)0x400d2030 )

Module clocks for UART[1:0] when the CPU is in PM0.

Definition at line 553 of file cc2538.h.

◆ SYS_CTRL_EMUOVR

#define SYS_CTRL_EMUOVR   ( *(cc2538_reg_t*)0x400d20b4 )

This register defines the emulator override controls for power mode and peripheral clock gate.

Definition at line 572 of file cc2538.h.

◆ SYS_CTRL_I_MAP

#define SYS_CTRL_I_MAP   ( *(cc2538_reg_t*)0x400d2098 )

This register selects which interrupt map to be used.

Definition at line 568 of file cc2538.h.

◆ SYS_CTRL_IWE

#define SYS_CTRL_IWE   ( *(cc2538_reg_t*)0x400d2094 )

This register controls interrupt wake-up.

Definition at line 567 of file cc2538.h.

◆ SYS_CTRL_PMCTL

#define SYS_CTRL_PMCTL   ( *(cc2538_reg_t*)0x400d2058 )

Power mode.

Definition at line 563 of file cc2538.h.

◆ SYS_CTRL_PWRDBG

#define SYS_CTRL_PWRDBG   ( *(cc2538_reg_t*)0x400d2074 )

Power debug register.

Definition at line 565 of file cc2538.h.

◆ SYS_CTRL_RCGCGPT

#define SYS_CTRL_RCGCGPT   ( *(cc2538_reg_t*)0x400d2008 )

Module clocks for GPT[3:0] when the CPU is in active (run) mode.

Definition at line 543 of file cc2538.h.

◆ SYS_CTRL_RCGCI2C

#define SYS_CTRL_RCGCI2C   ( *(cc2538_reg_t*)0x400d2038 )

Module clocks for I2C when the CPU is in active (run) mode.

Definition at line 555 of file cc2538.h.

◆ SYS_CTRL_RCGCRFC

#define SYS_CTRL_RCGCRFC   ( *(cc2538_reg_t*)0x400d20a8 )

This register defines the module clocks for RF CORE when the CPU is in active (run) mode.

Definition at line 569 of file cc2538.h.

◆ SYS_CTRL_RCGCSEC

#define SYS_CTRL_RCGCSEC   ( *(cc2538_reg_t*)0x400d2048 )

Module clocks for the security module when the CPU is in active (run) mode.

Definition at line 559 of file cc2538.h.

◆ SYS_CTRL_RCGCSSI

#define SYS_CTRL_RCGCSSI   ( *(cc2538_reg_t*)0x400d2018 )

Module clocks for SSI[1:0] when the CPU is in active (run) mode.

Definition at line 547 of file cc2538.h.

◆ SYS_CTRL_RCGCUART

#define SYS_CTRL_RCGCUART   ( *(cc2538_reg_t*)0x400d2028 )

Module clocks for UART[1:0] when the CPU is in active (run) mode.

Definition at line 551 of file cc2538.h.

◆ SYS_CTRL_SCGCGPT

#define SYS_CTRL_SCGCGPT   ( *(cc2538_reg_t*)0x400d200c )

Module clocks for GPT[3:0] when the CPU is in sleep mode.

Definition at line 544 of file cc2538.h.

◆ SYS_CTRL_SCGCI2C

#define SYS_CTRL_SCGCI2C   ( *(cc2538_reg_t*)0x400d203c )

Module clocks for I2C when the CPU is in sleep mode.

Definition at line 556 of file cc2538.h.

◆ SYS_CTRL_SCGCRFC

#define SYS_CTRL_SCGCRFC   ( *(cc2538_reg_t*)0x400d20ac )

This register defines the module clocks for RF CORE when the CPU is in sleep mode.

Definition at line 570 of file cc2538.h.

◆ SYS_CTRL_SCGCSEC

#define SYS_CTRL_SCGCSEC   ( *(cc2538_reg_t*)0x400d204c )

Module clocks for the security module when the CPU is in sleep mode.

Definition at line 560 of file cc2538.h.

◆ SYS_CTRL_SCGCSSI

#define SYS_CTRL_SCGCSSI   ( *(cc2538_reg_t*)0x400d201c )

Module clocks for SSI[1:0] when the CPU is insSleep mode.

Definition at line 548 of file cc2538.h.

◆ SYS_CTRL_SCGCUART

#define SYS_CTRL_SCGCUART   ( *(cc2538_reg_t*)0x400d202c )

Module clocks for UART[1:0] when the CPU is in sleep mode.

Definition at line 552 of file cc2538.h.

◆ SYS_CTRL_SRCRC

#define SYS_CTRL_SRCRC   ( *(cc2538_reg_t*)0x400d205c )

CRC on state retention.

Definition at line 564 of file cc2538.h.

◆ SYS_CTRL_SRGPT

#define SYS_CTRL_SRGPT   ( *(cc2538_reg_t*)0x400d2014 )

Reset for GPT[3:0].

Definition at line 546 of file cc2538.h.

◆ SYS_CTRL_SRI2C

#define SYS_CTRL_SRI2C   ( *(cc2538_reg_t*)0x400d2044 )

Reset for I2C.

Definition at line 558 of file cc2538.h.

◆ SYS_CTRL_SRSEC

#define SYS_CTRL_SRSEC   ( *(cc2538_reg_t*)0x400d2054 )

Reset for the security module.

Definition at line 562 of file cc2538.h.

◆ SYS_CTRL_SRSSI

#define SYS_CTRL_SRSSI   ( *(cc2538_reg_t*)0x400d2024 )

Reset for SSI[1:0].

Definition at line 550 of file cc2538.h.

◆ SYS_CTRL_SRUART

#define SYS_CTRL_SRUART   ( *(cc2538_reg_t*)0x400d2034 )

Reset for UART[1:0].

Definition at line 554 of file cc2538.h.

◆ UART0_CC

#define UART0_CC   ( *(cc2538_reg_t*)0x4000cfc8 )

UART0 clock configuration.

Definition at line 183 of file cc2538.h.

◆ UART0_CTL

#define UART0_CTL   ( *(cc2538_reg_t*)0x4000c030 )

UART0 control.

Definition at line 170 of file cc2538.h.

◆ UART0_DMACTL

#define UART0_DMACTL   ( *(cc2538_reg_t*)0x4000c048 )

UART0 DMA control.

Definition at line 176 of file cc2538.h.

◆ UART0_DR

#define UART0_DR   ( *(cc2538_reg_t*)0x4000c000 )

UART0 Data Register.

Definition at line 162 of file cc2538.h.

◆ UART0_ECR

#define UART0_ECR   ( *(cc2538_reg_t*)0x4000c004 )

UART0 receive status and error clear.

Definition at line 163 of file cc2538.h.

◆ UART0_FBRD

#define UART0_FBRD   ( *(cc2538_reg_t*)0x4000c028 )

UART0 fractional baud-rate divisor.

Definition at line 168 of file cc2538.h.

◆ UART0_FR

#define UART0_FR   ( *(cc2538_reg_t*)0x4000c018 )

UART0 flag.

Definition at line 165 of file cc2538.h.

◆ UART0_IBRD

#define UART0_IBRD   ( *(cc2538_reg_t*)0x4000c024 )

UART0 integer baud-rate divisor.

Definition at line 167 of file cc2538.h.

◆ UART0_ICR

#define UART0_ICR   ( *(cc2538_reg_t*)0x4000c044 )

UART0 interrupt clear.

Definition at line 175 of file cc2538.h.

◆ UART0_IFLS

#define UART0_IFLS   ( *(cc2538_reg_t*)0x4000c034 )

UART0 interrupt FIFO level select.

Definition at line 171 of file cc2538.h.

◆ UART0_ILPR

#define UART0_ILPR   ( *(cc2538_reg_t*)0x4000c020 )

UART0 IrDA low-power register.

Definition at line 166 of file cc2538.h.

◆ UART0_IM

#define UART0_IM   ( *(cc2538_reg_t*)0x4000c038 )

UART0 interrupt mask.

Definition at line 172 of file cc2538.h.

◆ UART0_LCRH

#define UART0_LCRH   ( *(cc2538_reg_t*)0x4000c02c )

UART0 line control.

Definition at line 169 of file cc2538.h.

◆ UART0_LCTL

#define UART0_LCTL   ( *(cc2538_reg_t*)0x4000c090 )

UART0 LIN control.

Definition at line 177 of file cc2538.h.

◆ UART0_LSS

#define UART0_LSS   ( *(cc2538_reg_t*)0x4000c094 )

UART0 LIN snap shot.

Definition at line 178 of file cc2538.h.

◆ UART0_LTIM

#define UART0_LTIM   ( *(cc2538_reg_t*)0x4000c098 )

UART0 LIN timer.

Definition at line 179 of file cc2538.h.

◆ UART0_MIS

#define UART0_MIS   ( *(cc2538_reg_t*)0x4000c040 )

UART0 masked interrupt status.

Definition at line 174 of file cc2538.h.

◆ UART0_NINEBITADDR

#define UART0_NINEBITADDR   ( *(cc2538_reg_t*)0x4000c0a4 )

UART0 9-bit self address.

Definition at line 180 of file cc2538.h.

◆ UART0_NINEBITAMASK

#define UART0_NINEBITAMASK   ( *(cc2538_reg_t*)0x4000c0a8 )

UART0 9-bit self address mask.

Definition at line 181 of file cc2538.h.

◆ UART0_PP

#define UART0_PP   ( *(cc2538_reg_t*)0x4000cfc0 )

UART0 peripheral properties.

Definition at line 182 of file cc2538.h.

◆ UART0_RIS

#define UART0_RIS   ( *(cc2538_reg_t*)0x4000c03c )

UART0 raw interrupt status.

Definition at line 173 of file cc2538.h.

◆ UART0_RSR

#define UART0_RSR   ( *(cc2538_reg_t*)0x4000c004 )

UART0 receive status and error clear.

Definition at line 164 of file cc2538.h.

◆ UART1_CC

#define UART1_CC   ( *(cc2538_reg_t*)0x4000dfc8 )

UART1 clock configuration.

Definition at line 205 of file cc2538.h.

◆ UART1_CTL

#define UART1_CTL   ( *(cc2538_reg_t*)0x4000d030 )

UART1 control.

Definition at line 192 of file cc2538.h.

◆ UART1_DMACTL

#define UART1_DMACTL   ( *(cc2538_reg_t*)0x4000d048 )

UART1 DMA control.

Definition at line 198 of file cc2538.h.

◆ UART1_DR

#define UART1_DR   ( *(cc2538_reg_t*)0x4000d000 )

UART1 Data Register.

Definition at line 184 of file cc2538.h.

◆ UART1_ECR

#define UART1_ECR   ( *(cc2538_reg_t*)0x4000d004 )

UART1 receive status and error clear.

Definition at line 185 of file cc2538.h.

◆ UART1_FBRD

#define UART1_FBRD   ( *(cc2538_reg_t*)0x4000d028 )

UART1 fractional baud-rate divisor.

Definition at line 190 of file cc2538.h.

◆ UART1_FR

#define UART1_FR   ( *(cc2538_reg_t*)0x4000d018 )

UART1 flag.

Definition at line 187 of file cc2538.h.

◆ UART1_IBRD

#define UART1_IBRD   ( *(cc2538_reg_t*)0x4000d024 )

UART1 integer baud-rate divisor.

Definition at line 189 of file cc2538.h.

◆ UART1_ICR

#define UART1_ICR   ( *(cc2538_reg_t*)0x4000d044 )

UART1 interrupt clear.

Definition at line 197 of file cc2538.h.

◆ UART1_IFLS

#define UART1_IFLS   ( *(cc2538_reg_t*)0x4000d034 )

UART1 interrupt FIFO level select.

Definition at line 193 of file cc2538.h.

◆ UART1_ILPR

#define UART1_ILPR   ( *(cc2538_reg_t*)0x4000d020 )

UART1 IrDA low-power register.

Definition at line 188 of file cc2538.h.

◆ UART1_IM

#define UART1_IM   ( *(cc2538_reg_t*)0x4000d038 )

UART1 interrupt mask.

Definition at line 194 of file cc2538.h.

◆ UART1_LCRH

#define UART1_LCRH   ( *(cc2538_reg_t*)0x4000d02c )

UART1 line control.

Definition at line 191 of file cc2538.h.

◆ UART1_LCTL

#define UART1_LCTL   ( *(cc2538_reg_t*)0x4000d090 )

UART1 LIN control.

Definition at line 199 of file cc2538.h.

◆ UART1_LSS

#define UART1_LSS   ( *(cc2538_reg_t*)0x4000d094 )

UART1 LIN snap shot.

Definition at line 200 of file cc2538.h.

◆ UART1_LTIM

#define UART1_LTIM   ( *(cc2538_reg_t*)0x4000d098 )

UART1 LIN timer.

Definition at line 201 of file cc2538.h.

◆ UART1_MIS

#define UART1_MIS   ( *(cc2538_reg_t*)0x4000d040 )

UART1 masked interrupt status.

Definition at line 196 of file cc2538.h.

◆ UART1_NINEBITADDR

#define UART1_NINEBITADDR   ( *(cc2538_reg_t*)0x4000d0a4 )

UART1 9-bit self address.

Definition at line 202 of file cc2538.h.

◆ UART1_NINEBITAMASK

#define UART1_NINEBITAMASK   ( *(cc2538_reg_t*)0x4000d0a8 )

UART1 9-bit self address mask.

Definition at line 203 of file cc2538.h.

◆ UART1_PP

#define UART1_PP   ( *(cc2538_reg_t*)0x4000dfc0 )

UART1 peripheral properties.

Definition at line 204 of file cc2538.h.

◆ UART1_RIS

#define UART1_RIS   ( *(cc2538_reg_t*)0x4000d03c )

UART1 raw interrupt status.

Definition at line 195 of file cc2538.h.

◆ UART1_RSR

#define UART1_RSR   ( *(cc2538_reg_t*)0x4000d004 )

UART1 receive status and error clear.

Definition at line 186 of file cc2538.h.

◆ UDMA_ALTBASE

#define UDMA_ALTBASE   ( *(cc2538_reg_t*)0x400ff00c )

DMA alternate channel control base pointer.

Definition at line 752 of file cc2538.h.

◆ UDMA_ALTCLR

#define UDMA_ALTCLR   ( *(cc2538_reg_t*)0x400ff034 )

DMA channel primary alternate clear.

Definition at line 762 of file cc2538.h.

◆ UDMA_ALTSET

#define UDMA_ALTSET   ( *(cc2538_reg_t*)0x400ff030 )

DMA channel primary alternate set.

Definition at line 761 of file cc2538.h.

◆ UDMA_CFG

#define UDMA_CFG   ( *(cc2538_reg_t*)0x400ff004 )

DMA configuration.

Definition at line 750 of file cc2538.h.

◆ UDMA_CHASGN

#define UDMA_CHASGN   ( *(cc2538_reg_t*)0x400ff500 )

DMA channel assignment.

Definition at line 766 of file cc2538.h.

◆ UDMA_CHIS

#define UDMA_CHIS   ( *(cc2538_reg_t*)0x400ff504 )

DMA channel interrupt status.

Definition at line 767 of file cc2538.h.

◆ UDMA_CHMAP0

#define UDMA_CHMAP0   ( *(cc2538_reg_t*)0x400ff510 )

DMA channel map select 0.

Definition at line 768 of file cc2538.h.

◆ UDMA_CHMAP1

#define UDMA_CHMAP1   ( *(cc2538_reg_t*)0x400ff514 )

DMA channel map select 1.

Definition at line 769 of file cc2538.h.

◆ UDMA_CHMAP2

#define UDMA_CHMAP2   ( *(cc2538_reg_t*)0x400ff518 )

DMA channel map select 2.

Definition at line 770 of file cc2538.h.

◆ UDMA_CHMAP3

#define UDMA_CHMAP3   ( *(cc2538_reg_t*)0x400ff51c )

DMA channel map select 3.

Definition at line 771 of file cc2538.h.

◆ UDMA_CTLBASE

#define UDMA_CTLBASE   ( *(cc2538_reg_t*)0x400ff008 )

DMA channel control base pointer.

Definition at line 751 of file cc2538.h.

◆ UDMA_ENACLR

#define UDMA_ENACLR   ( *(cc2538_reg_t*)0x400ff02c )

DMA channel enable clear.

Definition at line 760 of file cc2538.h.

◆ UDMA_ENASET

#define UDMA_ENASET   ( *(cc2538_reg_t*)0x400ff028 )

DMA channel enable set.

Definition at line 759 of file cc2538.h.

◆ UDMA_ERRCLR

#define UDMA_ERRCLR   ( *(cc2538_reg_t*)0x400ff04c )

DMA bus error clear.

Definition at line 765 of file cc2538.h.

◆ UDMA_PRIOCLR

#define UDMA_PRIOCLR   ( *(cc2538_reg_t*)0x400ff03c )

DMA channel priority clear.

Definition at line 764 of file cc2538.h.

◆ UDMA_PRIOSET

#define UDMA_PRIOSET   ( *(cc2538_reg_t*)0x400ff038 )

DMA channel priority set.

Definition at line 763 of file cc2538.h.

◆ UDMA_REQMASKCLR

#define UDMA_REQMASKCLR   ( *(cc2538_reg_t*)0x400ff024 )

DMA channel request mask clear.

Definition at line 758 of file cc2538.h.

◆ UDMA_REQMASKSET

#define UDMA_REQMASKSET   ( *(cc2538_reg_t*)0x400ff020 )

DMA channel request mask set.

Definition at line 757 of file cc2538.h.

◆ UDMA_STAT

#define UDMA_STAT   ( *(cc2538_reg_t*)0x400ff000 )

DMA status.

Definition at line 749 of file cc2538.h.

◆ UDMA_SWREQ

#define UDMA_SWREQ   ( *(cc2538_reg_t*)0x400ff014 )

DMA channel software request.

Definition at line 754 of file cc2538.h.

◆ UDMA_USEBURSTCLR

#define UDMA_USEBURSTCLR   ( *(cc2538_reg_t*)0x400ff01c )

DMA channel useburst clear.

Definition at line 756 of file cc2538.h.

◆ UDMA_USEBURSTSET

#define UDMA_USEBURSTSET   ( *(cc2538_reg_t*)0x400ff018 )

DMA channel useburst set.

Definition at line 755 of file cc2538.h.

◆ UDMA_WAITSTAT

#define UDMA_WAITSTAT   ( *(cc2538_reg_t*)0x400ff010 )

DMA channel wait-on-request status.

Definition at line 753 of file cc2538.h.

◆ USB_ADDR

#define USB_ADDR   ( *(cc2538_reg_t*)0x40089000 )

USB Function address.

Definition at line 437 of file cc2538.h.

◆ USB_CIE

#define USB_CIE   ( *(cc2538_reg_t*)0x4008902c )

USB Common USB interrupt enable mask.

Definition at line 444 of file cc2538.h.

◆ USB_CIF

#define USB_CIF   ( *(cc2538_reg_t*)0x40089018 )

USB Common USB interrupt flags.

Definition at line 441 of file cc2538.h.

◆ USB_CNT0_CNTL

#define USB_CNT0_CNTL   ( *(cc2538_reg_t*)0x40089058 )

USB Indexed register:

Definition at line 455 of file cc2538.h.

◆ USB_CNTH

#define USB_CNTH   ( *(cc2538_reg_t*)0x4008905c )

USB Indexed register:

Definition at line 456 of file cc2538.h.

◆ USB_CS0_CSIL

#define USB_CS0_CSIL   ( *(cc2538_reg_t*)0x40089044 )

USB Indexed register:

Definition at line 450 of file cc2538.h.

◆ USB_CSIH

#define USB_CSIH   ( *(cc2538_reg_t*)0x40089048 )

USB Indexed register:

Definition at line 451 of file cc2538.h.

◆ USB_CSOH

#define USB_CSOH   ( *(cc2538_reg_t*)0x40089054 )

USB Indexed register:

Definition at line 454 of file cc2538.h.

◆ USB_CSOL

#define USB_CSOL   ( *(cc2538_reg_t*)0x40089050 )

USB Indexed register:

Definition at line 453 of file cc2538.h.

◆ USB_CTRL

#define USB_CTRL   ( *(cc2538_reg_t*)0x4008903c )

USB USB peripheral control register.

Definition at line 448 of file cc2538.h.

◆ USB_F0

#define USB_F0   ( *(cc2538_reg_t*)0x40089080 )

USB Endpoint 0 FIFO.

Definition at line 457 of file cc2538.h.

◆ USB_F1

#define USB_F1   ( *(cc2538_reg_t*)0x40089088 )

USB IN/OUT endpoint 1 FIFO.

Definition at line 458 of file cc2538.h.

◆ USB_F2

#define USB_F2   ( *(cc2538_reg_t*)0x40089090 )

USB IN/OUT endpoint 2 FIFO.

Definition at line 459 of file cc2538.h.

◆ USB_F3

#define USB_F3   ( *(cc2538_reg_t*)0x40089098 )

USB IN/OUT endpoint 3 FIFO.

Definition at line 460 of file cc2538.h.

◆ USB_F4

#define USB_F4   ( *(cc2538_reg_t*)0x400890a0 )

USB IN/OUT endpoint 4 FIFO.

Definition at line 461 of file cc2538.h.

◆ USB_F5

#define USB_F5   ( *(cc2538_reg_t*)0x400890a8 )

USB IN/OUT endpoint 5 FIFO.

Definition at line 462 of file cc2538.h.

◆ USB_FRMH

#define USB_FRMH   ( *(cc2538_reg_t*)0x40089034 )

USB Frame number (high byte)

Definition at line 446 of file cc2538.h.

◆ USB_FRML

#define USB_FRML   ( *(cc2538_reg_t*)0x40089030 )

USB Frame number (low byte)

Definition at line 445 of file cc2538.h.

◆ USB_IIE

#define USB_IIE   ( *(cc2538_reg_t*)0x4008901c )

USB Interrupt enable mask for IN endpoints 1-5 and endpoint 0.

Definition at line 442 of file cc2538.h.

◆ USB_IIF

#define USB_IIF   ( *(cc2538_reg_t*)0x40089008 )

USB Interrupt flags for endpoint 0 and IN endpoints 1-5.

Definition at line 439 of file cc2538.h.

◆ USB_INDEX

#define USB_INDEX   ( *(cc2538_reg_t*)0x40089038 )

USB Index register for selecting the endpoint status and control registers.

Definition at line 447 of file cc2538.h.

◆ USB_MAXI

#define USB_MAXI   ( *(cc2538_reg_t*)0x40089040 )

USB Indexed register:

Definition at line 449 of file cc2538.h.

◆ USB_MAXO

#define USB_MAXO   ( *(cc2538_reg_t*)0x4008904c )

USB Indexed register:

Definition at line 452 of file cc2538.h.

◆ USB_OIE

#define USB_OIE   ( *(cc2538_reg_t*)0x40089024 )

USB Interrupt enable mask for OUT endpoints 1-5.

Definition at line 443 of file cc2538.h.

◆ USB_OIF

#define USB_OIF   ( *(cc2538_reg_t*)0x40089010 )

USB Interrupt flags for OUT endpoints 1-5.

Definition at line 440 of file cc2538.h.

◆ USB_POW

#define USB_POW   ( *(cc2538_reg_t*)0x40089004 )

USB Power management and control register.

Definition at line 438 of file cc2538.h.

◆ XOSC32K_FREQ

#define XOSC32K_FREQ   32768U

32 KHz external oscillator/clock frequency

Definition at line 803 of file cc2538.h.

◆ XOSC32M_FREQ

#define XOSC32M_FREQ   32000000U

32 MHz external oscillator/clock frequency

Definition at line 800 of file cc2538.h.

Typedef Documentation

◆ cc2538_reg_t

typedef volatile uint32_t cc2538_reg_t

Least-significant 32 bits of the IEEE address.

Definition at line 124 of file cc2538.h.