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Nordic nRF51 MCU

Nordic nRF51 family of CPUs More...

Detailed Description

Nordic nRF51 family of CPUs

Files

file  cpu_conf.h
 Implementation specific CPU configuration options.
 
file  periph_cpu.h
 nRF51 specific definitions for handling peripherals
 
#define CPU_DEFAULT_IRQ_PRIO   (1U)
 ARM Cortex-M specific CPU configuration.
 
#define CPU_IRQ_NUMOF   (26U)
 
#define CPU_FLASH_BASE   (0x00000000)
 
#define FLASHPAGE_SIZE   (1024U)
 Flash page configuration.
 
#define FLASHPAGE_WRITE_BLOCK_SIZE   (4U)
 
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT   (4U)
 
#define CONFIG_GNRC_PKTBUF_SIZE   (2048)
 Due to RAM restrictions, we need to limit the default GNRC packet buffer size on these CPUs.
 
#define PWM_GPIOTE_CH   (2U)
 CPU specific PWM configuration.
 
#define PWM_PPI_A   (0U)
 
#define PWM_PPI_B   (1U)
 

Macro Definition Documentation

◆ CONFIG_GNRC_PKTBUF_SIZE

#define CONFIG_GNRC_PKTBUF_SIZE   (2048)

Due to RAM restrictions, we need to limit the default GNRC packet buffer size on these CPUs.

Definition at line 67 of file cpu_conf.h.

◆ CPU_DEFAULT_IRQ_PRIO

#define CPU_DEFAULT_IRQ_PRIO   (1U)

ARM Cortex-M specific CPU configuration.

Definition at line 37 of file cpu_conf.h.

◆ CPU_FLASH_BASE

#define CPU_FLASH_BASE   (0x00000000)

Definition at line 39 of file cpu_conf.h.

◆ CPU_IRQ_NUMOF

#define CPU_IRQ_NUMOF   (26U)

Definition at line 38 of file cpu_conf.h.

◆ FLASHPAGE_SIZE

#define FLASHPAGE_SIZE   (1024U)

Flash page configuration.

Definition at line 46 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_ALIGNMENT

#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT   (4U)

Definition at line 58 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_SIZE

#define FLASHPAGE_WRITE_BLOCK_SIZE   (4U)

Definition at line 56 of file cpu_conf.h.

◆ PWM_GPIOTE_CH

#define PWM_GPIOTE_CH   (2U)

CPU specific PWM configuration.

Definition at line 75 of file cpu_conf.h.

◆ PWM_PPI_A

#define PWM_PPI_A   (0U)

Definition at line 76 of file cpu_conf.h.

◆ PWM_PPI_B

#define PWM_PPI_B   (1U)

Definition at line 77 of file cpu_conf.h.