Common code for TI cc26xx/cc13xx family. More...

Detailed Description

Common code for TI cc26xx/cc13xx family.

This module contains code common to all cc26xx/cc13xx cpus supported by RIOT: TI CC26x0/CC13x0, TI CC26x2, CC13x2

RIOT-OS on CC26xx/CC13xx boards

Overview

The CC26xx/C13xx is a family of micro controllers fabricated by Texas Instruments for low-power communications, using protocols such as BLE, IEEE 802.15.4g-2012, and proprietary radio protocols.

These family of MCUs is divided in two generations, the cc26x0/cc13x0, and the cc26x2/cc13x2 family. The difference is that the later provides more ROM and RAM and improvements on various peripherals.

MCU family	RAM	Flash
CC26x0/CC13x0	20 K	128 K
CC26x2/CC13x2	80 K	352 K

Note: The actual flash size is the flash size minus 88 bytes, these 88 bytes are reserved for the CCFG, see also Flashing the CCFG.

Flashing the CCFG

Warning: Setting an incorrect CCFG configuration may lock out yourself out of the device.

Note: Blank chips from Texas Instruments come without a CCFG flashed, so any firmware flashed won't boot until the configuration is flashed. As this might be the case for custom boards remember flashing it.

RIOT provides built-in support to flash the Customer Configuration on the CC26xx/CC13xx MCUs. It can be done through Kconfig using make menuconfig.

For example:

make -C examples/hello-world menuconfig BOARD=cc1350-launchpad

It will open the Kconfig terminal configuration utility, you may see the Update CCFG option, selecting it will include the default configuration that Texas Instruments provides from their own SDK. You may change any further options available through Kconfig.

Once configuration is saved you may compile a new binary and flash it onto the device.

For example:

make -C examples/hello-world flash BOARD=cc1350-launchpad

Note: Once flashed, there's no need to flash it again, unless the configuration needs to be changed.

Debugging

Development kits from Texas Instruments come with an XDS110 on-board debug probe that provides programming, flashing and debugging capabilities.

It can either use proprietary Texas Instruments tools for programming, or OpenOCD.

Using Upstream OpenOCD

OpenOCD is the default programmer and debugger. Hence, flashing can be done by navigating to the application directory and running:

make flash BOARD=<CC26xx-or-CC13xx-based-board>

Warning: A reliable and robust sequence to reset the CC26xx / CC13xx from upstream OpenOCD is not yet implemented. As a result, OpenOCD will halt the MCU for flashing without reset. This may result in IRQ handlers being already set up and responding to IRQs that trigger while flashing. Hence, flashing is likely not 100% reliable.

Note: By default the XDS110 debug adapter is used, which is the debugger TI integrates into is developments boards. This can be overwritten by setting OPENOCD_DEBUG_ADAPTER to a different debugger.

Using TI's OpenOCD Fork

TI maintains an outdated fork of OpenOCD that contains patches and special handling that have not upstreamed yet. It can be build using:

# Clone into the openocd-ti folder
git clone https://git.ti.com/cgit/sdo-emu/openocd openocd-ti
 
# Change directory to the openocd source code
cd openocd-ti/openocd
 
# Configure, build, install
./configure
make
sudo make install

Warning: Sometimes OpenOCD may stop working when the firmware on the XDS110 is updated (when using Uniflash, happens without user intervention). With that in mind, it's encouraged to either enable the ROM bootloader backdoor to enable serial programming or the installation of TI Uniflash as a fallback. See Using Uniflash

Note: With ‘OPENOCD_CMD_RESET_HALT="-c 'reset halt’"` the default reset sequence can be restored. This may work with TI's OpenOCD fork.

Otherwise, usage is identical with the upstream version of OpenOCD.

using J-Link

By passing (or exporting) PROGRAMMER=jlink J-Link can be used to flash the board. This requires a J-Link compatible programmer / debugger. Since the XDS110 that TI's development boards use is not compatible, an external programmer has to be used. The upside is that flashing appears to be reliable with that.

Using Uniflash

The TI's Code Composer Studio provides the necessary tools to use the debug features of the XDS110; Uniflash provides flashing tools. Both programs can be found here:

Before using the XDS110 with the latest CCS/Uniflash versions the firmware for it needs to be updated. Texas Instruments has a guide to correctly update it here.

Setting up the environment

In order to make use of the programming and debugging capabilities of the XDS110 some environment variable needs to be set:

export CCS_PATH=<path to ti install folder>/ti/ccs930

export UNIFLASH_PATH<path to ti install folder>/ti/uniflash_5.2.0

That assumes you have CCS 9.3.0 (for the path name) and Uniflash 5.2.0, adjust accordingly.

After that you can flash using the RIOT make flash command on your application or to debug you first start the debug server:

make debug-server

And then on another terminal you can run:

make debug

It will open GDB and connect to the debug server automatically.

Note: By default LaunchPad boards on RIOT use uniflash as the default programmer, if it's not the case for an external board, you can always use uniflash by setting this environment variable PROGRAMMER=uniflash to change the default programmer.

Files
file	cc26xx_cc13xx_power.h
	CC26xx/CC13xx Power management.

file	cpu_conf_cc26xx_cc13xx.h
	Implementation specific CPU configuration options.

file	periph_cpu_common.h
	CPU specific definitions for internal peripheral handling.

#define	CPU_DEFAULT_IRQ_PRIO (1U)
	ARM Cortex-M specific CPU configuration.

#define	CPU_IRQ_NUMOF IRQN_COUNT

#define	CPU_FLASH_BASE FLASH_BASE

#define	CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0
	CC26xx/CC13xx specific CPU configuration.

#define	CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0
	Force VDDR high setting, enables higher output power but also higher power consumption.

#define	CONFIG_CC26XX_CC13XX_GPRAM 0
	Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache).

#define	CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
	This configures the level need to enter the bootloader backdoor at boot time.

#define	CONFIG_CC26XX_CC13XX_BL_PIN 0xFF
	DIO (pin) number used to enter the bootloader backdoor at boot time.

#define	SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1
	Disable GPRAM.

#define	NUM_HEAPS (2)

#define	SET_EXT_LF_CLK_DIO 0x01
	Customer Configuration (CCFG)

#define	SET_EXT_LF_CLK_RTC_INCREMENT 0x800000
	The input frequency of the external clock and is written to `AON_RTC:SUBSECINC.VALUEINC`.

#define	SET_MODE_CONF_1_TCXO_TYPE 0x01
	Selects the TCXO type.

#define	SET_MODE_CONF_1_TCXO_MAX_START 0x7F
	Maximum TCXO startup time in units of 100us.

#define	SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8
	Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled.

#define	SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0
	Enable DC/DC dithering if alternate DC/DC setting is enabled.

#define	SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0
	Inductor peak current if alternate DC/DC setting is enabled.

#define	SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0
	Signed delta value for IBIAS_INIT.

#define	SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0
	Signed delta value for IBIAS_OFFSET.

#define	SET_MODE_CONF_1_XOSC_MAX_START 0x10
	Maximum XOSC startup time (worst case) in units of 100us.

#define	SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
	Total size of the CCFG in bytes.

#define	SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS
	Reserved by Texas Instruments for future use.

#define	SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1
	Disable TCXO.

#define	SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0
	Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).

#define	SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1
	Disable XOSC override functionality.

#define	SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF
	Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one.

#define	SET_MODE_CONF_DCDC_RECHARGE 0x0
	DC/DC during recharge in powerdown.

#define	SET_MODE_CONF_DCDC_ACTIVE 0x0
	DC/DC in active mode.

#define	SET_MODE_CONF_VDDR_EXT_LOAD 0x0
	Reserved for future use byte TI.

#define	SET_MODE_CONF_VDDS_BOD_LEVEL 0x1
	VDDS BOD level.

#define	SET_MODE_CONF_SCLK_LF_OPTION 0x2
	LF clock option.

#define	SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1
	VDDR_TRIM_SLEEP_DELTA temperature compensation.

#define	SET_MODE_CONF_RTC_COMP 0x1
	Reserved for future use by TI.

#define	SET_MODE_CONF_XOSC_FREQ 0x2
	External crystal frequency.

#define	SET_MODE_CONF_XOSC_CAP_MOD 0x1
	Enable modification (delta) to XOSC cap-array.

#define	SET_MODE_CONF_HF_COMP 0x1
	Reserved for future use by TI.

#define	SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF
	Modifies trimmed XOSC cap-array step value.

#define	SET_MODE_CONF_VDDR_CAP 0x3A
	Represents the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF.

#define	SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00
	Bootloader enable.

#define	SET_BL_CONFIG_BL_LEVEL 0x1
	Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.

#define	SET_BL_CONFIG_BL_PIN_NUMBER 0xFF
	DIO number that is level checked if the boot loader backdoor is enabled by the SET_BL_CONFIG_BL_ENABLE setting.

#define	SET_BL_CONFIG_BL_ENABLE 0xFF
	Enables the boot loader backdoor.

#define	SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5
	Enable CPU DAP.

#define	SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5
	Enable PWRPROF TAP (PRCM on x0 CPUs).

#define	SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00
	Enable Test TAP.

Macro Definition Documentation

◆ CONFIG_CC26XX_CC13XX_BL_LEVEL

#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1

This configures the level need to enter the bootloader backdoor at boot time.

Definition at line 100 of file cpu_conf_cc26xx_cc13xx.h.

◆ CONFIG_CC26XX_CC13XX_BL_PIN

#define CONFIG_CC26XX_CC13XX_BL_PIN 0xFF

DIO (pin) number used to enter the bootloader backdoor at boot time.

Definition at line 108 of file cpu_conf_cc26xx_cc13xx.h.

◆ CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH

#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0

Force VDDR high setting, enables higher output power but also higher power consumption.

This is also called "boost mode".

Definition at line 74 of file cpu_conf_cc26xx_cc13xx.h.

◆ CONFIG_CC26XX_CC13XX_GPRAM

#define CONFIG_CC26XX_CC13XX_GPRAM 0

Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache).

Note: Enabling GPRAM disables CACHE and will reduce CPU execution speed (up to 60%).; GPRAM is 8KB in size and located at 0x11000000-0x11001FFF if enabled.

Definition at line 86 of file cpu_conf_cc26xx_cc13xx.h.

◆ CONFIG_CC26XX_CC13XX_UPDATE_CCFG

#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0

CC26xx/CC13xx specific CPU configuration.

This includes the CCFG configuration in the binary for flashing onto the micro-controller.

Definition at line 64 of file cpu_conf_cc26xx_cc13xx.h.

◆ CPU_DEFAULT_IRQ_PRIO

#define CPU_DEFAULT_IRQ_PRIO (1U)

ARM Cortex-M specific CPU configuration.

Definition at line 50 of file cpu_conf_cc26xx_cc13xx.h.

◆ CPU_FLASH_BASE

#define CPU_FLASH_BASE FLASH_BASE

Definition at line 52 of file cpu_conf_cc26xx_cc13xx.h.

◆ CPU_IRQ_NUMOF

#define CPU_IRQ_NUMOF IRQN_COUNT

Definition at line 51 of file cpu_conf_cc26xx_cc13xx.h.

◆ NUM_HEAPS

#define NUM_HEAPS (2)

Definition at line 143 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_BL_CONFIG_BL_ENABLE

#define SET_BL_CONFIG_BL_ENABLE 0xFF

Enables the boot loader backdoor.

C5h = Boot loader backdoor is enabled. Any other value = Boot loader backdoor is disabled.

Definition at line 502 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_BL_CONFIG_BL_LEVEL

#define SET_BL_CONFIG_BL_LEVEL 0x1

Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.

0h = Active low. 1h = Active high.

Definition at line 485 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_BL_CONFIG_BL_PIN_NUMBER

#define SET_BL_CONFIG_BL_PIN_NUMBER 0xFF

DIO number that is level checked if the boot loader backdoor is enabled by the SET_BL_CONFIG_BL_ENABLE setting.

Definition at line 493 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_BL_CONFIG_BOOTLOADER_ENABLE

#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00

Bootloader enable.

Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and conditions for boot loader backdoor are met).

C5h = Boot loader is enabled. Any other value = Boot loader is disabled.

Definition at line 475 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE

#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5

Enable CPU DAP.

C5h = Main CPU DAP access is enabled. Any other value = Main CPU DAP access will remain disabled.

Definition at line 511 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE

#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5

Enable PWRPROF TAP (PRCM on x0 CPUs).

C5h = PWRPROF TAP access is enabled. Any other value = PWRPROF TAP access will remain disabled.

Definition at line 520 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE

#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00

Enable Test TAP.

C5h = TEST TAP access is enabled. Any other value = TEST TAP access will remain disabled.

Definition at line 529 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_EXT_LF_CLK_DIO

#define SET_EXT_LF_CLK_DIO 0x01

Customer Configuration (CCFG)

Selects the DIO to supply external 32kHz clock as SCLK_LF when SET_MODE_CONF_SCLK_LF_OPTION is set to "external LF". The

Definition at line 156 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_EXT_LF_CLK_RTC_INCREMENT

#define SET_EXT_LF_CLK_RTC_INCREMENT 0x800000

The input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC.

Defined as follows:

EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz

For example:

RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz

Definition at line 172 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_ALT_DCDC_DITHER_EN

#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0

Enable DC/DC dithering if alternate DC/DC setting is enabled.

0h = Dither disable 1h = Dither enable

Definition at line 231 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_ALT_DCDC_IPEAK

#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0

Inductor peak current if alternate DC/DC setting is enabled.

Note: Assuming 10uH external inductor!; Values changes between x2 and x0 CPUs.

Definition at line 242 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_ALT_DCDC_VMIN

#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8

Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled.

The VMIN voltage is defnied as follows:

Voltage = (28 + ALT_DCDC_VMIN) / 16

For example:

0 = 1.75 V 1 = 1.8125 V ... 8 = 2.25 V ... 14 = 2.625 V 15 = 2.6875 V

Definition at line 222 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_DELTA_IBIAS_INIT

#define SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0

Signed delta value for IBIAS_INIT.

Definition at line 249 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_DELTA_IBIAS_OFFSET

#define SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0

Signed delta value for IBIAS_OFFSET.

Definition at line 256 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_TCXO_MAX_START

#define SET_MODE_CONF_1_TCXO_MAX_START 0x7F

Maximum TCXO startup time in units of 100us.

Note: x2 CPUs only.; Value is only valid if SET_MODE_CONF_XOSC_FREQ is equal to 0.

Definition at line 198 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_TCXO_TYPE

#define SET_MODE_CONF_1_TCXO_TYPE 0x01

Selects the TCXO type.

0h = CMOS type. Internal common-mode bias will not be enabled. 1h = Clipped-sine type. Internal common-mode bias will be enabled when TCXO is used.

Note: x2 CPUs only.; Value is only valid if SET_MODE_CONF_XOSC_FREQ is equal to 0.

Definition at line 187 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_1_XOSC_MAX_START

#define SET_MODE_CONF_1_XOSC_MAX_START 0x10

Maximum XOSC startup time (worst case) in units of 100us.

Definition at line 263 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_DCDC_ACTIVE

#define SET_MODE_CONF_DCDC_ACTIVE 0x0

DC/DC in active mode.

0h = Use the DC/DC during active mode. 1h = Do not use the DC/DC during active mode (default).

Definition at line 358 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_DCDC_RECHARGE

#define SET_MODE_CONF_DCDC_RECHARGE 0x0

DC/DC during recharge in powerdown.

0h = Use the DC/DC during recharge in powerdown. 1h = Do not use the DC/DC during recharge in powerdown (default).

Definition at line 349 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_HF_COMP

#define SET_MODE_CONF_HF_COMP 0x1

Reserved for future use by TI.

Definition at line 443 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_RTC_COMP

#define SET_MODE_CONF_RTC_COMP 0x1

Reserved for future use by TI.

Definition at line 414 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_SCLK_LF_OPTION

#define SET_MODE_CONF_SCLK_LF_OPTION 0x2

LF clock option.

0h = LF clock derived from HF clock. Note: using this configuration will block the device from entering Standby mode. 1h = External LF clock. 2h = LF XOSC. 3h = LF RCOSC.

Definition at line 389 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_VDDR_CAP

#define SET_MODE_CONF_VDDR_CAP 0x3A

Represents the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF.

This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby.

Definition at line 464 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_VDDR_EXT_LOAD

#define SET_MODE_CONF_VDDR_EXT_LOAD 0x0

Reserved for future use byte TI.

However it's used to enable VDDR_HH setting, with an "special value".

Definition at line 366 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA

#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF

Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one.

0x8 (-8) : Delta = -7 ... 0xF (-1) : Delta = 0 0x0 (0) : Delta = +1 ... 0x7 (7) : Delta = +8

Definition at line 340 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_VDDR_TRIM_SLEEP_TC

#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1

VDDR_TRIM_SLEEP_DELTA temperature compensation.

1h = VDDR_TRIM_SLEEP_DELTA is not temperature compensated. 0h = RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode.

When temperature compensation is performed, the delta is calculates this way:

Delta = max (delta, min(8, floor(62-temp)/8))

Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C.

Definition at line 407 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_VDDS_BOD_LEVEL

#define SET_MODE_CONF_VDDS_BOD_LEVEL 0x1

VDDS BOD level.

0h = VDDS BOD level is 2.0V (necessary for external load mode, or for maximum PA output power on CC13xx). 1h = VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default).

Definition at line 377 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_XOSC_CAP_MOD

#define SET_MODE_CONF_XOSC_CAP_MOD 0x1

Enable modification (delta) to XOSC cap-array.

Value specified in XOSC_CAPARRAY_DELTA.

0h = Apply cap-array delta. 1h = Do not apply cap-array delta (default).

Definition at line 436 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_XOSC_CAPARRAY_DELTA

#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF

Modifies trimmed XOSC cap-array step value.

Enabled by SET_MODE_CONF_XOSC_CAP_MOD.

Definition at line 452 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_MODE_CONF_XOSC_FREQ

#define SET_MODE_CONF_XOSC_FREQ 0x2

External crystal frequency.

1h = HPOSC 2h = 48 MHz 3h = 24 MHz

On x2 chips 48 MHz is the default, on x0 chips it's 24 MHz

Definition at line 426 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING

#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0

Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).

0h = GPRAM is enabled and hence CACHE disabled. 1h = GPRAM is disabled and instead CACHE is enabled (default).

Note: Disabling CACHE will reduce CPU execution speed (up to 60%).; GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if

Disable alternate DC/DC settings.

0h = Enable alternate DC/DC settings. 1h = Disable alternate DC/DC settings.

See also: SET_MODE_CONF_1_ALT_DCDC_VMIN; SET_MODE_CONF_1_ALT_DCDC_DITHER_EN; SET_MODE_CONF_1_ALT_DCDC_IPEAK

Definition at line 313 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM

#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1

Disable GPRAM.

Definition at line 122 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_DIS_TCXO

#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1

Disable TCXO.

0h = TCXO functionality enabled. 1h = TCXO functionality disabled.

Definition at line 288 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR

#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1

Disable XOSC override functionality.

0h = Enable XOSC override functionality. 1h = Disable XOSC override functionality.

See also: SET_MODE_CONF_1_DELTA_IBIAS_INIT; SET_MODE_CONF_1_DELTA_IBIAS_OFFSET; SET_MODE_CONF_1_XOSC_MAX_START

Definition at line 326 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS

#define SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS

Value:

(CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m >> \

CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s)

Reserved by Texas Instruments for future use.

Definition at line 277 of file cpu_conf_cc26xx_cc13xx.h.

◆ SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG

#define SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058

Total size of the CCFG in bytes.

Definition at line 270 of file cpu_conf_cc26xx_cc13xx.h.

Detailed Description

RIOT-OS on CC26xx/CC13xx boards

Overview

Flashing the CCFG

Debugging

Using Upstream OpenOCD

Using TI's OpenOCD Fork

using J-Link

Using Uniflash

Setting up the environment

Files

Macro Definition Documentation

◆ CONFIG_CC26XX_CC13XX_BL_LEVEL

◆ CONFIG_CC26XX_CC13XX_BL_PIN

◆ CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH

◆ CONFIG_CC26XX_CC13XX_GPRAM

◆ CONFIG_CC26XX_CC13XX_UPDATE_CCFG

◆ CPU_DEFAULT_IRQ_PRIO

◆ CPU_FLASH_BASE

◆ CPU_IRQ_NUMOF

◆ NUM_HEAPS

◆ SET_BL_CONFIG_BL_ENABLE

◆ SET_BL_CONFIG_BL_LEVEL

◆ SET_BL_CONFIG_BL_PIN_NUMBER

◆ SET_BL_CONFIG_BOOTLOADER_ENABLE

◆ SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE

◆ SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE

◆ SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE

◆ SET_EXT_LF_CLK_DIO

◆ SET_EXT_LF_CLK_RTC_INCREMENT

◆ SET_MODE_CONF_1_ALT_DCDC_DITHER_EN

◆ SET_MODE_CONF_1_ALT_DCDC_IPEAK

◆ SET_MODE_CONF_1_ALT_DCDC_VMIN

◆ SET_MODE_CONF_1_DELTA_IBIAS_INIT

◆ SET_MODE_CONF_1_DELTA_IBIAS_OFFSET

◆ SET_MODE_CONF_1_TCXO_MAX_START

◆ SET_MODE_CONF_1_TCXO_TYPE

◆ SET_MODE_CONF_1_XOSC_MAX_START

◆ SET_MODE_CONF_DCDC_ACTIVE

◆ SET_MODE_CONF_DCDC_RECHARGE

◆ SET_MODE_CONF_HF_COMP

◆ SET_MODE_CONF_RTC_COMP

◆ SET_MODE_CONF_SCLK_LF_OPTION

◆ SET_MODE_CONF_VDDR_CAP

◆ SET_MODE_CONF_VDDR_EXT_LOAD

◆ SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA

◆ SET_MODE_CONF_VDDR_TRIM_SLEEP_TC

◆ SET_MODE_CONF_VDDS_BOD_LEVEL

◆ SET_MODE_CONF_XOSC_CAP_MOD

◆ SET_MODE_CONF_XOSC_CAPARRAY_DELTA

◆ SET_MODE_CONF_XOSC_FREQ

◆ SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING

◆ SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM

◆ SET_SIZE_AND_DIS_FLAGS_DIS_TCXO

◆ SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR

◆ SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS

◆ SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG