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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2014 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19#include "clk_conf.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
29static const timer_conf_t timer_config[] = {
30 {
31 .dev = TIM2,
32 .max = 0x0000ffff,
33 .rcc_mask = RCC_APB1ENR_TIM2EN,
34 .bus = APB1,
35 .irqn = TIM2_IRQn
36 },
37 {
38 .dev = TIM3,
39 .max = 0x0000ffff,
40 .rcc_mask = RCC_APB1ENR_TIM3EN,
41 .bus = APB1,
42 .irqn = TIM3_IRQn
43 }
44};
45
46#define TIMER_0_ISR isr_tim2
47#define TIMER_1_ISR isr_tim3
48
49#define TIMER_NUMOF ARRAY_SIZE(timer_config)
51
56static const uart_conf_t uart_config[] = {
57 {
58 .dev = USART2,
59 .rcc_mask = RCC_APB1ENR_USART2EN,
60 .rx_pin = GPIO_PIN(PORT_A, 3),
61 .tx_pin = GPIO_PIN(PORT_A, 2),
62 .bus = APB1,
63 .irqn = USART2_IRQn
64 }
65};
66
67#define UART_0_ISR (isr_usart2)
68
69#define UART_NUMOF ARRAY_SIZE(uart_config)
71
76static const spi_conf_t spi_config[] = {
77 {
78 .dev = SPI1,
79 .mosi_pin = GPIO_PIN(PORT_B, 17),
80 .miso_pin = GPIO_PIN(PORT_B, 16),
81 .sclk_pin = GPIO_PIN(PORT_B, 15),
82 .cs_pin = SPI_CS_UNDEF,
83 .rccmask = RCC_APB2ENR_SPI1EN,
84 .apbbus = APB2
85 }
86};
87
88#define SPI_NUMOF ARRAY_SIZE(spi_config)
90
91#ifdef __cplusplus
92} /* end extern "C" */
93#endif
94
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217