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cfg_clock_default_120.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4 * SPDX-FileCopyrightText: 2018-2020 Inria
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
21
22#include "kernel_defines.h"
23#include "macros/units.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
33/* The following parameters configure a 120MHz system clock with HSE (8MHz or
34 16MHz) or HSI (16MHz) as PLL input clock */
35#ifndef CONFIG_CLOCK_PLL_M
36#define CONFIG_CLOCK_PLL_M (4)
37#endif
38#ifndef CONFIG_CLOCK_PLL_N
39#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
40#define CONFIG_CLOCK_PLL_N (120)
41#else
42#define CONFIG_CLOCK_PLL_N (60)
43#endif
44#endif
45#ifndef CONFIG_CLOCK_PLL_P
46#define CONFIG_CLOCK_PLL_P (2)
47#endif
48#ifndef CONFIG_CLOCK_PLL_Q
49#define CONFIG_CLOCK_PLL_Q (5)
50#endif
52
57#ifndef CONFIG_CLOCK_APB1_DIV
58#define CONFIG_CLOCK_APB1_DIV (4) /* max 30MHz */
59#endif
60#ifndef CONFIG_CLOCK_APB2_DIV
61#define CONFIG_CLOCK_APB2_DIV (2) /* max 60MHz */
62#endif
64
65#if CLOCK_CORECLOCK > MHZ(120)
66#error "SYSCLK cannot exceed 120MHz"
67#endif
68
69#ifdef __cplusplus
70}
71#endif
72
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.