Default STM32F4 clock configuration for 180MHz boards. More...
Default STM32F4 clock configuration for 180MHz boards.
Definition in file cfg_clock_default_180.h.
Go to the source code of this file.
Clock PLL settings (180MHz) | |
#define | CONFIG_CLOCK_PLL_M (4) |
#define | CONFIG_CLOCK_PLL_N (90) |
#define | CONFIG_CLOCK_PLL_P (2) |
#define | CONFIG_CLOCK_PLL_Q (8) |
#define | CONFIG_CLOCK_PLL_R (8) |
Clock bus settings (APB1 and APB2) | |
#define | CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */ |
#define | CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */ |
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */ |
Definition at line 100 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */ |
Definition at line 103 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_PLL_M (4) |
Definition at line 48 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_PLL_N (90) |
Definition at line 72 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_PLL_P (2) |
Definition at line 77 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_PLL_Q (8) |
Definition at line 87 of file cfg_clock_default_180.h.
#define CONFIG_CLOCK_PLL_R (8) |
Definition at line 91 of file cfg_clock_default_180.h.