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cfg_clock_default_180.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2018 Freie Universität Berlin
3 * 2017 OTA keys S.A.
4 * 2018-2020 Inria
5 *
6 * This file is subject to the terms and conditions of the GNU Lesser
7 * General Public License v2.1. See the file LICENSE in the top level
8 * directory for more details.
9 */
10
23#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
24#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
25
26#include "kernel_defines.h"
27#include "macros/units.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37/* The following parameters configure a 180MHz system clock with HSE (8MHz,
38 12MHz or 16MHz) or HSI (16MHz) as PLL input clock.
39 If USB is used and no alternative 48MHz is available, the clock frequency is
40 decreased to 168MHZ so the PLLQ can output 48MHz.
41 */
42#ifndef CONFIG_CLOCK_PLL_M
43#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12))
44#define CONFIG_CLOCK_PLL_M (12)
45#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))
46#define CONFIG_CLOCK_PLL_M (16)
47#else
48#define CONFIG_CLOCK_PLL_M (4)
49#endif
50#endif
51#ifndef CONFIG_CLOCK_PLL_N
52#if (IS_USED(MODULE_PERIPH_USBDEV_CLK) || IS_USED(MODULE_PERIPH_SDMMC_CLK)) && \
53 (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
54 defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
55 defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
56 defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
57#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
58#define CONFIG_CLOCK_PLL_N (168)
59#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
60 (CONFIG_CLOCK_HSE == MHZ(16)))
61#define CONFIG_CLOCK_PLL_N (336)
62#else
63#define CONFIG_CLOCK_PLL_N (84)
64#endif
65#else
66#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
67#define CONFIG_CLOCK_PLL_N (180)
68#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
69 (CONFIG_CLOCK_HSE == MHZ(16)))
70#define CONFIG_CLOCK_PLL_N (360)
71#else
72#define CONFIG_CLOCK_PLL_N (90)
73#endif
74#endif /* MODULE_PERIPH_USBDEV_CLK || MODULE_PERIPH_SDMMC_CLK */
75#endif
76#ifndef CONFIG_CLOCK_PLL_P
77#define CONFIG_CLOCK_PLL_P (2)
78#endif
79#ifndef CONFIG_CLOCK_PLL_Q
80#if (IS_USED(MODULE_PERIPH_USBDEV_CLK) || IS_USED(MODULE_PERIPH_SDMMC_CLK)) && \
81 (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
82 defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
83 defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
84 defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
85#define CONFIG_CLOCK_PLL_Q (7)
86#else
87#define CONFIG_CLOCK_PLL_Q (8)
88#endif
89#endif
90#ifndef CONFIG_CLOCK_PLL_R
91#define CONFIG_CLOCK_PLL_R (8)
92#endif
99#ifndef CONFIG_CLOCK_APB1_DIV
100#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
101#endif
102#ifndef CONFIG_CLOCK_APB2_DIV
103#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
104#endif
107#if CLOCK_CORECLOCK > MHZ(180)
108#error "SYSCLK cannot exceed 180MHz"
109#endif
110
111#ifdef __cplusplus
112}
113#endif
114
115#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H */
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.