Default STM32F7 clock configuration for 216MHz boards. More...
Default STM32F7 clock configuration for 216MHz boards.
Definition in file cfg_clock_default_216.h.
Go to the source code of this file.
Clock PLL settings (216MHz) | |
#define | CONFIG_CLOCK_PLL_M (4) |
#define | CONFIG_CLOCK_PLL_N (108) |
#define | CONFIG_CLOCK_PLL_P (2) |
#define | CONFIG_CLOCK_PLL_Q (9) |
#define | CONFIG_CLOCK_PLL_R (8) |
Clock bus settings (APB1 and APB2) | |
#define | CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */ |
#define | CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */ |
#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */ |
Definition at line 71 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */ |
Definition at line 74 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_PLL_M (4) |
Definition at line 43 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_PLL_N (108) |
Definition at line 52 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_PLL_P (2) |
Definition at line 56 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_PLL_Q (9) |
Definition at line 59 of file cfg_clock_default_216.h.
#define CONFIG_CLOCK_PLL_R (8) |
Definition at line 62 of file cfg_clock_default_216.h.