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cfg_clock_default_216.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4 * SPDX-FileCopyrightText: 2018-2020 Inria
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
21
22#include "kernel_defines.h"
23#include "macros/units.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
33/* The following parameters configure a 216MHz system clock with HSE (8MHz,
34 16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
35#ifndef CONFIG_CLOCK_PLL_M
36#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
37#define CONFIG_CLOCK_PLL_M (25)
38#else
39#define CONFIG_CLOCK_PLL_M (4)
40#endif
41#endif
42#ifndef CONFIG_CLOCK_PLL_N
43#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
44#define CONFIG_CLOCK_PLL_N (432)
45#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
46#define CONFIG_CLOCK_PLL_N (216)
47#else
48#define CONFIG_CLOCK_PLL_N (108)
49#endif
50#endif
51#ifndef CONFIG_CLOCK_PLL_P
52#define CONFIG_CLOCK_PLL_P (2)
53#endif
54#ifndef CONFIG_CLOCK_PLL_Q
55#define CONFIG_CLOCK_PLL_Q (9)
56#endif
57#ifndef CONFIG_CLOCK_PLL_R
58#define CONFIG_CLOCK_PLL_R (8)
59#endif
61
66#ifndef CONFIG_CLOCK_APB1_DIV
67#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
68#endif
69#ifndef CONFIG_CLOCK_APB2_DIV
70#define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
71#endif
73
74#if CLOCK_CORECLOCK > MHZ(216)
75#error "SYSCLK cannot exceed 216MHz"
76#endif
77
78#ifdef __cplusplus
79}
80#endif
81
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.