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cfg_usb_otg_fs_u5.h
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1/*
2 * Copyright (C) 2019 Koen Zandberg
3 * 2023 Gunar Schorcht
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef CFG_USB_OTG_FS_U5_H
22#define CFG_USB_OTG_FS_U5_H
23
24#include "periph_cpu.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
34#define DWC2_USB_OTG_FS_ENABLED
35
40 {
41 .periph = USB_OTG_FS_BASE,
42 .type = DWC2_USB_OTG_FS,
44 .rcc_mask = RCC_AHB2ENR1_OTGEN,
45 .irqn = OTG_FS_IRQn,
46 .ahb = AHB2,
47 .dm = GPIO_PIN(PORT_A, 11),
48 .dp = GPIO_PIN(PORT_A, 12),
49 .af = GPIO_AF10,
50 }
51};
52
56#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
57
58#ifdef __cplusplus
59}
60#endif
61
62#endif /* CFG_USB_OTG_FS_U5_H */
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_FS
Full speed peripheral.