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cfg_clock_default.h
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1/*
2 * SPDX-FileCopyrightText: 2020 Savoir-faire Linux
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "cfg_clock_common_fx_gx_mp1_c0.h"
19#include "kernel_defines.h"
20#include "macros/units.h"
21
26/* The following parameters configure a 208MHz system clock with HSE (24MHz)
27 * or HSI (16MHz) as PLL input clock */
28#ifndef CONFIG_CLOCK_PLL_M
29#define CONFIG_CLOCK_PLL_M (2)
30#endif
31#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(24))
32#ifndef CONFIG_CLOCK_PLL_N
33#define CONFIG_CLOCK_PLL_N (52)
34#endif
35#else /* HSI */
36#ifndef CONFIG_CLOCK_PLL_N
37#define CONFIG_CLOCK_PLL_N (78)
38#endif
39#endif
40#ifndef CONFIG_CLOCK_PLL_P
41#define CONFIG_CLOCK_PLL_P (3)
42#endif
43#ifndef CONFIG_CLOCK_PLL_Q
44#define CONFIG_CLOCK_PLL_Q (13)
45#endif
46#ifndef CONFIG_CLOCK_PLL_R
47#define CONFIG_CLOCK_PLL_R (3)
48#endif
50
55#ifndef CONFIG_CLOCK_MCU_DIV
56#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
57#endif
58#ifndef CONFIG_CLOCK_APB1_DIV
59#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
60#endif
61#ifndef CONFIG_CLOCK_APB2_DIV
62#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
63#endif
64#ifndef CONFIG_CLOCK_APB3_DIV
65#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
66#endif
68
69#if CLOCK_CORECLOCK > MHZ(208)
70#error "SYSCLK cannot exceed 208MHz"
71#endif
72
77#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
78#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
79#else /* CONFIG_CLOCK_HSI */
80#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
81#endif
82
83#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
84#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
85
86#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
87#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
88#error "The board doesn't provide an HSE oscillator"
89#endif
90#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
91
92#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
93#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
94 * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
95#endif /* CONFIG_USE_CLOCK_PLL */
96
97#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
98 * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
99
100#define CLOCK_APB1 (CLOCK_CORECLOCK \
101 / CONFIG_CLOCK_APB1_DIV)
102#define CLOCK_APB2 (CLOCK_CORECLOCK \
103 / CONFIG_CLOCK_APB2_DIV)
105
106#ifdef __cplusplus
107extern "C" {
108#endif
109
110#ifdef __cplusplus
111}
112#endif
113
cfg_clock_common_fx_gx_mp1_c0.h
Base STM32Fx/Gx/MP1/C0 clock configuration.
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.