cpu__conf__kinetis__w_8h_source.html

/*

 * SPDX-FileCopyrightText: 2017 Eistec AB

 * SPDX-License-Identifier: LGPL-2.1-only

 */


#pragma once


#if defined(KINETIS_CORE_D)

/* Kinetis KW2xD */

#if defined(CPU_MODEL_MKW21D256VHA5) || \

    defined(CPU_MODEL_MKW21D512VHA5)

#include "vendor/MKW21D5.h"

#elif defined(CPU_MODEL_MKW22D512VHA5)

#include "vendor/MKW22D5.h"

#elif defined(CPU_MODEL_MKW24D512VHA5)

#include "vendor/MKW24D5.h"

#endif


#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1

#define KW2XDRF_PORT_DEV        PORTB

#define KW2XDRF_PORT            PORT_B

#define KW2XDRF_GPIO            GPIOB

#define KW2XDRF_PORT_IRQn       PORTB_IRQn

#define KW2XDRF_PORT_CLKEN()    (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)

#define KW2XDRF_PIN_AF          2

#define KW2XDRF_PCS0_PIN        10

#define KW2XDRF_SCK_PIN         11

#define KW2XDRF_SOUT_PIN        16

#define KW2XDRF_SIN_PIN         17

#define KW2XDRF_RST_PIN         19

#define KW2XDRF_IRQ_PIN         3

#define KW2XDRF_CLK_CTRL_PORT   PORT_C

#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC

#define KW2XDRF_CLK_CTRL_GPIO   GPIOC

#define KW2XDRF_CLK_CTRL_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)

#define KW2XDRF_CLK_CTRL_PIN    0


#elif defined(KINETIS_CORE_Z)

/* Kinetis KWxxZ */

#if defined(CPU_MODEL_MKW21Z256VHT4) || \

    defined(CPU_MODEL_MKW21Z512VHT4)

#include "vendor/MKW21Z4.h"

#elif defined(CPU_MODEL_MKW31Z256VHT4) || \

    defined(CPU_MODEL_MKW31Z512CAT4) || \

    defined(CPU_MODEL_MKW31Z512VHT4)

#include "vendor/MKW31Z4.h"

#elif defined(CPU_MODEL_MKW41Z256VHT4) || \

    defined(CPU_MODEL_MKW41Z512CAT4) || \

    defined(CPU_MODEL_MKW41Z512VHT4)

#include "vendor/MKW41Z4.h"

#endif

#endif /* KINETIS_CORE_x */


#define FLASHPAGE_SIZE      (2048U)

#define FLASHPAGE_NUMOF     ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)


/* The minimum block size which can be written is 4B. However, the erase

 * block is always FLASHPAGE_SIZE.

 */

#define FLASHPAGE_WRITE_BLOCK_SIZE          (4U)

/* Writing should be always 4 bytes aligned */

#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT     (4U)

/* Section erase and programming must be 8 bytes aligned */

#define FLASHPAGE_BLOCK_SECTION_ALIGNMENT   (8U)


#ifdef __cplusplus

extern "C"

{

#endif


#ifdef __cplusplus

}

#endif