19#include "vendor/gd32vf103_core.h"
20#include "cpu_conf_common.h"
29#define CLIC_NUM_INTERRUPTS (ECLIC_NUM_INTERRUPTS)
30#define CLIC_BASE_ADDR (ECLIC_CTRL_ADDR)
31#define CPU_DEFAULT_IRQ_PRIO (0xFF)
36#define HAVE_CSR_MIE (0)
42#define FLASHPAGE_SIZE (1024U)
43#define FLASHPAGE_NUMOF (128U)
44#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
45#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
46#define CPU_FLASH_BASE 0x08000000
67#ifndef CONFIG_AFIO_PCF0_SWJ_CFG
74#define CONFIG_AFIO_PCF0_SWJ_CFG SWJ_CFG_NO_NJTRST
afio_pcf0_swj_cfg_t
Possible values of the SWJ_CFG field in the AFIO->PCF0 register.
@ SWJ_CFG_NO_NJTRST
JTAG enabled, but NJTRST disabled and pin PB4 usable as GPIO.
@ SWJ_CFG_FULL_JTAG
Full JTAG interface (reset value)
@ SWJ_CFG_NO_JTAG
JTAG disabled, all debug pins usable as GPIOs.