cpu_conf.h

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/*
 * SPDX-FileCopyrightText: 2020 Koen Zandberg <koen@bergzand.net>
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include "vendor/gd32vf103_core.h"
#include "cpu_conf_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CLIC_NUM_INTERRUPTS  (ECLIC_NUM_INTERRUPTS)
#define CLIC_BASE_ADDR       (ECLIC_CTRL_ADDR)
#define CPU_DEFAULT_IRQ_PRIO (0xFF)

#define HAVE_CSR_MIE                    (0)

#define FLASHPAGE_SIZE                  (1024U)
#define FLASHPAGE_NUMOF                 (128U)
#define FLASHPAGE_WRITE_BLOCK_SIZE      (2U)
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
#define CPU_FLASH_BASE                  0x08000000

typedef enum {
    SWJ_CFG_FULL_JTAG    = 0,
    SWJ_CFG_NO_NJTRST   = 1U << AFIO_PCF0_SWJ_CFG_Pos,
    SWJ_CFG_NO_JTAG     = 4U << AFIO_PCF0_SWJ_CFG_Pos,
} afio_pcf0_swj_cfg_t;
 
#ifndef CONFIG_AFIO_PCF0_SWJ_CFG
#define CONFIG_AFIO_PCF0_SWJ_CFG    SWJ_CFG_NO_NJTRST
#endif
 
#ifdef __cplusplus
}
#endif