Register definitions for ST L3Gxxxx 3-axis gyroscope sensor family. More...
Detailed Description
Register definitions for ST L3Gxxxx 3-axis gyroscope sensor family.
Definition in file l3gxxxx_regs.h.
This graph shows which files directly or indirectly include this file:Go to the source code of this file.
Register addresses | |
| #define | L3GXXXX_REG_WHO_AM_I (0x0f) |
| Register address WHO_AM_I. | |
| #define | L3GXXXX_REG_CTRL1 (0x20) |
| Register address CTRL1. | |
| #define | L3GXXXX_REG_CTRL2 (0x21) |
| Register address CTRL2. | |
| #define | L3GXXXX_REG_CTRL3 (0x22) |
| Register address CTRL3. | |
| #define | L3GXXXX_REG_CTRL4 (0x23) |
| Register address CTRL4. | |
| #define | L3GXXXX_REG_CTRL5 (0x24) |
| Register address CTRL5. | |
| #define | L3GXXXX_REG_REFERENCE (0x25) |
| Register address REFERENCE. | |
| #define | L3GXXXX_REG_OUT_TEMP (0x26) |
| Register address OUT_TEMP. | |
| #define | L3GXXXX_REG_STATUS (0x27) |
| Register address STATUS. | |
| #define | L3GXXXX_REG_OUT_X_L (0x28) |
| Register address OUT_X_L. | |
| #define | L3GXXXX_REG_OUT_X_H (0x29) |
| Register address OUT_X_H. | |
| #define | L3GXXXX_REG_OUT_Y_L (0x2a) |
| Register address OUT_Y_L. | |
| #define | L3GXXXX_REG_OUT_Y_H (0x2b) |
| Register address OUT_Y_H. | |
| #define | L3GXXXX_REG_OUT_Z_L (0x2c) |
| Register address OUT_Z_L. | |
| #define | L3GXXXX_REG_OUT_Z_H (0x2d) |
| Register address OUT_Z_H. | |
| #define | L3GXXXX_REG_FIFO_CTRL (0x2e) |
| Register address FIFO_CTRL. | |
| #define | L3GXXXX_REG_FIFO_SRC (0x2f) |
| Register address FIFO_SRC. | |
| #define | L3GXXXX_REG_IG_CFG (0x30) |
| Register address IG_CFG. | |
| #define | L3GXXXX_REG_IG_SRC (0x31) |
| Register address IG_SRC. | |
| #define | L3GXXXX_REG_IG_THS_XH (0x32) |
| Register address IG_THS_XH. | |
| #define | L3GXXXX_REG_IG_THS_XL (0x33) |
| Register address IG_THS_XL. | |
| #define | L3GXXXX_REG_IG_THS_YH (0x34) |
| Register address IG_THS_YH. | |
| #define | L3GXXXX_REG_IG_THS_YL (0x35) |
| Register address IG_THS_YL. | |
| #define | L3GXXXX_REG_IG_THS_ZH (0x36) |
| Register address IG_THS_ZH. | |
| #define | L3GXXXX_REG_IG_THS_ZL (0x37) |
| Register address IG_THS_ZL. | |
| #define | L3GXXXX_REG_IG_DURATION (0x38) |
| Register address IG_DURATION. | |
| #define | L3GXXXX_REG_LOW_ODR (0x39) |
| Register address LOW_ODR. | |
Register structure definitions | |
| #define | L3GXXXX_ZYXOR (0x80) |
| L3GXXXX_REG_STATUS<7> | |
| #define | L3GXXXX_ZOR (0x40) |
| L3GXXXX_REG_STATUS<6> | |
| #define | L3GXXXX_YOR (0x20) |
| L3GXXXX_REG_STATUS<5> | |
| #define | L3GXXXX_XOR (0x10) |
| L3GXXXX_REG_STATUS<4> | |
| #define | L3GXXXX_ZYXDA (0x08) |
| L3GXXXX_REG_STATUS<3> | |
| #define | L3GXXXX_ZDA (0x04) |
| L3GXXXX_REG_STATUS<2> | |
| #define | L3GXXXX_YDA (0x02) |
| L3GXXXX_REG_STATUS<1> | |
| #define | L3GXXXX_XDA (0x01) |
| L3GXXXX_REG_STATUS<0> | |
| #define | L3GXXXX_ANY_DATA_READY (0x07) |
| L3GXXXX_REG_STATUS<2:0> | |
| #define | L3GXXXX_ANY_DATA_READY_S (0) |
| L3GXXXX_REG_STATUS<2:0> | |
| #define | L3GXXXX_ODR (0xc0) |
| L3GXXXX_REG_CTRL1<7:6> | |
| #define | L3GXXXX_BW (0x30) |
| L3GXXXX_REG_CTRL1<5:4> | |
| #define | L3GXXXX_ODR_BW (0xf0) |
| L3GXXXX_REG_CTRL1<7:4> | |
| #define | L3GXXXX_POWER_MODE (0x08) |
| L3GXXXX_REG_CTRL1<3> | |
| #define | L3GXXXX_Z_ENABLED (0x04) |
| L3GXXXX_REG_CTRL1<2> | |
| #define | L3GXXXX_Y_ENABLED (0x02) |
| L3GXXXX_REG_CTRL1<1> | |
| #define | L3GXXXX_X_ENABLED (0x01) |
| L3GXXXX_REG_CTRL1<0> | |
| #define | L3GXXXX_XYZ_ENABLED (0x07) |
| L3GXXXX_REG_CTRL1<2:0> | |
| #define | L3GXXXX_ODR_S (6) |
| L3GXXXX_REG_CTRL1<7:6> | |
| #define | L3GXXXX_BW_S (4) |
| L3GXXXX_REG_CTRL1<5:4> | |
| #define | L3GXXXX_ODR_BW_S (4) |
| L3GXXXX_REG_CTRL1<7:4> | |
| #define | L3GXXXX_POWER_MODE_S (3) |
| L3GXXXX_REG_CTRL1<3> | |
| #define | L3GXXXX_Z_ENABLED_S (2) |
| L3GXXXX_REG_CTRL1<2> | |
| #define | L3GXXXX_Y_ENABLED_S (1) |
| L3GXXXX_REG_CTRL1<1> | |
| #define | L3GXXXX_X_ENABLED_S (1) |
| L3GXXXX_REG_CTRL1<0> | |
| #define | L3GXXXX_XYZ_ENABLED_S (0) |
| L3GXXXX_REG_CTRL1<2:0> | |
| #define | L3GXXXX_EXTR_EN (0x80) |
| L3GXXXX_REG_CTRL2<7> | |
| #define | L3GXXXX_LVL_EN (0x40) |
| L3GXXXX_REG_CTRL2<6> | |
| #define | L3GXXXX_HPF_MODE (0x30) |
| L3GXXXX_REG_CTRL2<5:4> | |
| #define | L3GXXXX_HPF_CUTOFF (0x0f) |
| L3GXXXX_REG_CTRL2<3:0> | |
| #define | L3GXXXX_EXTR_EN_S (7) |
| L3GXXXX_REG_CTRL2<7> | |
| #define | L3GXXXX_LVL_EN_S (6) |
| L3GXXXX_REG_CTRL2<6> | |
| #define | L3GXXXX_HPF_MODE_S (4) |
| L3GXXXX_REG_CTRL2<5:4> | |
| #define | L3GXXXX_INT1_IG (0x80) |
| L3GXXXX_REG_CTRL3<7> | |
| #define | L3GXXXX_INT1_BOOT (0x40) |
| L3GXXXX_REG_CTRL3<6> | |
| #define | L3GXXXX_HL_ACTIVE (0x20) |
| L3GXXXX_REG_CTRL3<5> | |
| #define | L3GXXXX_PP_OD (0x10) |
| L3GXXXX_REG_CTRL3<4> | |
| #define | L3GXXXX_INT2_DRDY (0x08) |
| L3GXXXX_REG_CTRL3<3> | |
| #define | L3GXXXX_INT2_WTM (0x04) |
| L3GXXXX_REG_CTRL3<2> | |
| #define | L3GXXXX_INT2_ORUN (0x02) |
| L3GXXXX_REG_CTRL3<1> | |
| #define | L3GXXXX_INT2_EMPTY (0x01) |
| L3GXXXX_REG_CTRL3<0> | |
| #define | L3GXXXX_INT1_IG_S (7) |
| L3GXXXX_REG_CTRL3<7> | |
| #define | L3GXXXX_INT1_BOOT_S (6) |
| L3GXXXX_REG_CTRL3<6> | |
| #define | L3GXXXX_HL_ACTIVE_S (5) |
| L3GXXXX_REG_CTRL3<5> | |
| #define | L3GXXXX_PP_OD_S (4) |
| L3GXXXX_REG_CTRL3<4> | |
| #define | L3GXXXX_INT2_DRDY_S (3) |
| L3GXXXX_REG_CTRL3<3> | |
| #define | L3GXXXX_INT2_WTM_S (2) |
| L3GXXXX_REG_CTRL3<2> | |
| #define | L3GXXXX_INT2_ORUN_S (1) |
| L3GXXXX_REG_CTRL3<1> | |
| #define | L3GXXXX_INT2_EMPTY_S (0) |
| L3GXXXX_REG_CTRL3<0> | |
| #define | L3GXXXX_BLOCK_DATA_UPDATE (0x80) |
| L3GXXXX_REG_CTRL4<7> | |
| #define | L3GXXXX_BIG_LITTLE_ENDIAN (0x40) |
| L3GXXXX_REG_CTRL4<6> | |
| #define | L3GXXXX_FULL_SCALE (0x30) |
| L3GXXXX_REG_CTRL4<5:4> | |
| #define | L3GXXXX_FULL_SCALE_S (4) |
| L3GXXXX_REG_CTRL4<5:4> | |
| #define | L3GXXXX_BOOT (0x80) |
| L3GXXXX_REG_CTRL5<7> | |
| #define | L3GXXXX_FIFO_EN (0x40) |
| L3GXXXX_REG_CTRL5<6> | |
| #define | L3GXXXX_STOP_ON_WTM (0x20) |
| L3GXXXX_REG_CTRL5<5> | |
| #define | L3GXXXX_HP_ENABLED (0x10) |
| L3GXXXX_REG_CTRL5<4> | |
| #define | L3GXXXX_IG_SEL (0x0c) |
| L3GXXXX_REG_CTRL5<3:2> | |
| #define | L3GXXXX_OUT_SEL (0x03) |
| L3GXXXX_REG_CTRL5<1:0> | |
| #define | L3GXXXX_BOOT_S (7) |
| L3GXXXX_REG_CTRL5<7> | |
| #define | L3GXXXX_FIFO_EN_S (6) |
| L3GXXXX_REG_CTRL5<6> | |
| #define | L3GXXXX_STOP_ON_WTM_S (5) |
| L3GXXXX_REG_CTRL5<5> | |
| #define | L3GXXXX_HP_ENABLED_S (4) |
| L3GXXXX_REG_CTRL5<4> | |
| #define | L3GXXXX_IG_SEL_S (2) |
| L3GXXXX_REG_CTRL5<3:2> | |
| #define | L3GXXXX_OUT_SEL_S (0) |
| L3GXXXX_REG_CTRL5<1:0> | |
| #define | L3GXXXX_FIFO_MODE (0xe0) |
| L3GXXXX_REG_FIFO_CTRL<7:5> | |
| #define | L3GXXXX_FIFO_WATERMARK (0x1f) |
| L3GXXXX_REG_FIFO_CTRL<4:0> | |
| #define | L3GXXXX_FIFO_MODE_S (5) |
| L3GXXXX_REG_FIFO_CTRL<7:5> | |
| #define | L3GXXXX_FIFO_WATERMARK_S (0) |
| L3GXXXX_REG_FIFO_CTRL<4:0> | |
| #define | L3GXXXX_FIFO_WTM (0x80) |
| L3GXXXX_REG_FIFO_SRC<7> | |
| #define | L3GXXXX_FIFO_OVR (0x40) |
| L3GXXXX_REG_FIFO_SRC<6> | |
| #define | L3GXXXX_FIFO_EMPTY (0x20) |
| L3GXXXX_REG_FIFO_SRC<5> | |
| #define | L3GXXXX_FIFO_FFS (0x1f) |
| L3GXXXX_REG_FIFO_SRC<4:0> | |
| #define | L3GXXXX_FIFO_WTM_S (7) |
| L3GXXXX_REG_FIFO_SRC<7> | |
| #define | L3GXXXX_FIFO_OVR_S (6) |
| L3GXXXX_REG_FIFO_SRC<6> | |
| #define | L3GXXXX_FIFO_EMPTY_S (5) |
| L3GXXXX_REG_FIFO_SRC<5> | |
| #define | L3GXXXX_FIFO_FFS_S (0) |
| L3GXXXX_REG_FIFO_SRC<4:0> | |
| #define | L3GXXXX_INT1_AND_OR (0x80) |
| L3GXXXX_REG_IG_CFG<7> | |
| #define | L3GXXXX_INT1_LATCH (0x40) |
| L3GXXXX_REG_IG_CFG<6> | |
| #define | L3GXXXX_INT1_Z_HIGH (0x20) |
| L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5> | |
| #define | L3GXXXX_INT1_Z_LOW (0x10) |
| L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4> | |
| #define | L3GXXXX_INT1_Y_HIGH (0x08) |
| L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3> | |
| #define | L3GXXXX_INT1_Y_LOW (0x04) |
| L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2> | |
| #define | L3GXXXX_INT1_X_HIGH (0x02) |
| L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1> | |
| #define | L3GXXXX_INT1_X_LOW (0x01) |
| L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0> | |
| #define | L3GXXXX_INT1_AND_OR_S (7) |
| L3GXXXX_REG_IG_CFG<7> | |
| #define | L3GXXXX_INT1_LATCH_S (6) |
| L3GXXXX_REG_IG_CFG<6> | |
| #define | L3GXXXX_INT1_Z_HIGH_S (5) |
| L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5> | |
| #define | L3GXXXX_INT1_Z_LOW_S (4) |
| L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4> | |
| #define | L3GXXXX_INT1_Y_HIGH_S (3) |
| L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3> | |
| #define | L3GXXXX_INT1_Y_LOW_S (2) |
| L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2> | |
| #define | L3GXXXX_INT1_X_HIGH_S (1) |
| L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1> | |
| #define | L3GXXXX_INT1_X_LOW_S (0) |
| L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0> | |
| #define | L3GXXXX_INT1_ACTIVE (0x40) |
| L3GXXXX_REG_IG_SRC<6> | |
| #define | L3GXXXX_INT1_WAIT (0x80) |
| L3GXXXX_REG_IG_DURATION<7> | |
| #define | L3GXXXX_INT1_DURATION (0x3f) |
| L3GXXXX_REG_IG_DURATION<6:0> | |
| #define | L3GXXXX_INT1_WAIT_S (7) |
| L3GXXXX_REG_IG_DURATION<7> | |
| #define | L3GXXXX_INT1_DURATION_S (0) |
| L3GXXXX_REG_IG_DURATION<6:0> | |
| #define | L3GXXXX_DRDY_HL (0x20) |
| L3GXXXX_REG_LOW_ODR<5> | |
| #define | L3GXXXX_SW_RESET (0x04) |
| L3GXXXX_REG_LOW_ODR<2> | |
| #define | L3GXXXX_LOW_ODR (0x01) |
| L3GXXXX_REG_LOW_ODR<0> | |
| #define | L3GXXXX_DRDY_HL_S (5) |
| L3GXXXX_REG_LOW_ODR<5> | |
| #define | L3GXXXX_SW_RESET_S (2) |
| L3GXXXX_REG_LOW_ODR<2> | |
| #define | L3GXXXX_LOW_ODR_S (0) |
| L3GXXXX_REG_LOW_ODR<0> | |
Macro Definition Documentation
◆ L3GXXXX_ANY_DATA_READY
| #define L3GXXXX_ANY_DATA_READY (0x07) |
L3GXXXX_REG_STATUS<2:0>
Definition at line 71 of file l3gxxxx_regs.h.
◆ L3GXXXX_ANY_DATA_READY_S
| #define L3GXXXX_ANY_DATA_READY_S (0) |
L3GXXXX_REG_STATUS<2:0>
Definition at line 72 of file l3gxxxx_regs.h.
◆ L3GXXXX_BIG_LITTLE_ENDIAN
| #define L3GXXXX_BIG_LITTLE_ENDIAN (0x40) |
L3GXXXX_REG_CTRL4<6>
Definition at line 120 of file l3gxxxx_regs.h.
◆ L3GXXXX_BLOCK_DATA_UPDATE
| #define L3GXXXX_BLOCK_DATA_UPDATE (0x80) |
L3GXXXX_REG_CTRL4<7>
Definition at line 119 of file l3gxxxx_regs.h.
◆ L3GXXXX_BOOT
| #define L3GXXXX_BOOT (0x80) |
L3GXXXX_REG_CTRL5<7>
Definition at line 125 of file l3gxxxx_regs.h.
◆ L3GXXXX_BOOT_S
| #define L3GXXXX_BOOT_S (7) |
L3GXXXX_REG_CTRL5<7>
Definition at line 132 of file l3gxxxx_regs.h.
◆ L3GXXXX_BW
| #define L3GXXXX_BW (0x30) |
L3GXXXX_REG_CTRL1<5:4>
Definition at line 75 of file l3gxxxx_regs.h.
◆ L3GXXXX_BW_S
| #define L3GXXXX_BW_S (4) |
L3GXXXX_REG_CTRL1<5:4>
Definition at line 84 of file l3gxxxx_regs.h.
◆ L3GXXXX_DRDY_HL
| #define L3GXXXX_DRDY_HL (0x20) |
L3GXXXX_REG_LOW_ODR<5>
Definition at line 181 of file l3gxxxx_regs.h.
◆ L3GXXXX_DRDY_HL_S
| #define L3GXXXX_DRDY_HL_S (5) |
L3GXXXX_REG_LOW_ODR<5>
Definition at line 185 of file l3gxxxx_regs.h.
◆ L3GXXXX_EXTR_EN
| #define L3GXXXX_EXTR_EN (0x80) |
L3GXXXX_REG_CTRL2<7>
Definition at line 92 of file l3gxxxx_regs.h.
◆ L3GXXXX_EXTR_EN_S
| #define L3GXXXX_EXTR_EN_S (7) |
L3GXXXX_REG_CTRL2<7>
Definition at line 97 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_EMPTY
| #define L3GXXXX_FIFO_EMPTY (0x20) |
L3GXXXX_REG_FIFO_SRC<5>
Definition at line 147 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_EMPTY_S
| #define L3GXXXX_FIFO_EMPTY_S (5) |
L3GXXXX_REG_FIFO_SRC<5>
Definition at line 152 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_EN
| #define L3GXXXX_FIFO_EN (0x40) |
L3GXXXX_REG_CTRL5<6>
Definition at line 126 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_EN_S
| #define L3GXXXX_FIFO_EN_S (6) |
L3GXXXX_REG_CTRL5<6>
Definition at line 133 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_FFS
| #define L3GXXXX_FIFO_FFS (0x1f) |
L3GXXXX_REG_FIFO_SRC<4:0>
Definition at line 148 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_FFS_S
| #define L3GXXXX_FIFO_FFS_S (0) |
L3GXXXX_REG_FIFO_SRC<4:0>
Definition at line 153 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_MODE
| #define L3GXXXX_FIFO_MODE (0xe0) |
L3GXXXX_REG_FIFO_CTRL<7:5>
Definition at line 139 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_MODE_S
| #define L3GXXXX_FIFO_MODE_S (5) |
L3GXXXX_REG_FIFO_CTRL<7:5>
Definition at line 142 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_OVR
| #define L3GXXXX_FIFO_OVR (0x40) |
L3GXXXX_REG_FIFO_SRC<6>
Definition at line 146 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_OVR_S
| #define L3GXXXX_FIFO_OVR_S (6) |
L3GXXXX_REG_FIFO_SRC<6>
Definition at line 151 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_WATERMARK
| #define L3GXXXX_FIFO_WATERMARK (0x1f) |
L3GXXXX_REG_FIFO_CTRL<4:0>
Definition at line 140 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_WATERMARK_S
| #define L3GXXXX_FIFO_WATERMARK_S (0) |
L3GXXXX_REG_FIFO_CTRL<4:0>
Definition at line 143 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_WTM
| #define L3GXXXX_FIFO_WTM (0x80) |
L3GXXXX_REG_FIFO_SRC<7>
Definition at line 145 of file l3gxxxx_regs.h.
◆ L3GXXXX_FIFO_WTM_S
| #define L3GXXXX_FIFO_WTM_S (7) |
L3GXXXX_REG_FIFO_SRC<7>
Definition at line 150 of file l3gxxxx_regs.h.
◆ L3GXXXX_FULL_SCALE
| #define L3GXXXX_FULL_SCALE (0x30) |
L3GXXXX_REG_CTRL4<5:4>
Definition at line 121 of file l3gxxxx_regs.h.
◆ L3GXXXX_FULL_SCALE_S
| #define L3GXXXX_FULL_SCALE_S (4) |
L3GXXXX_REG_CTRL4<5:4>
Definition at line 123 of file l3gxxxx_regs.h.
◆ L3GXXXX_HL_ACTIVE
| #define L3GXXXX_HL_ACTIVE (0x20) |
L3GXXXX_REG_CTRL3<5>
Definition at line 103 of file l3gxxxx_regs.h.
◆ L3GXXXX_HL_ACTIVE_S
| #define L3GXXXX_HL_ACTIVE_S (5) |
L3GXXXX_REG_CTRL3<5>
Definition at line 112 of file l3gxxxx_regs.h.
◆ L3GXXXX_HP_ENABLED
| #define L3GXXXX_HP_ENABLED (0x10) |
L3GXXXX_REG_CTRL5<4>
Definition at line 128 of file l3gxxxx_regs.h.
◆ L3GXXXX_HP_ENABLED_S
| #define L3GXXXX_HP_ENABLED_S (4) |
L3GXXXX_REG_CTRL5<4>
Definition at line 135 of file l3gxxxx_regs.h.
◆ L3GXXXX_HPF_CUTOFF
| #define L3GXXXX_HPF_CUTOFF (0x0f) |
L3GXXXX_REG_CTRL2<3:0>
Definition at line 95 of file l3gxxxx_regs.h.
◆ L3GXXXX_HPF_MODE
| #define L3GXXXX_HPF_MODE (0x30) |
L3GXXXX_REG_CTRL2<5:4>
Definition at line 94 of file l3gxxxx_regs.h.
◆ L3GXXXX_HPF_MODE_S
| #define L3GXXXX_HPF_MODE_S (4) |
L3GXXXX_REG_CTRL2<5:4>
Definition at line 99 of file l3gxxxx_regs.h.
◆ L3GXXXX_IG_SEL
| #define L3GXXXX_IG_SEL (0x0c) |
L3GXXXX_REG_CTRL5<3:2>
Definition at line 129 of file l3gxxxx_regs.h.
◆ L3GXXXX_IG_SEL_S
| #define L3GXXXX_IG_SEL_S (2) |
L3GXXXX_REG_CTRL5<3:2>
Definition at line 136 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_ACTIVE
| #define L3GXXXX_INT1_ACTIVE (0x40) |
L3GXXXX_REG_IG_SRC<6>
Definition at line 173 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_AND_OR
| #define L3GXXXX_INT1_AND_OR (0x80) |
L3GXXXX_REG_IG_CFG<7>
Definition at line 155 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_AND_OR_S
| #define L3GXXXX_INT1_AND_OR_S (7) |
L3GXXXX_REG_IG_CFG<7>
Definition at line 164 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_BOOT
| #define L3GXXXX_INT1_BOOT (0x40) |
L3GXXXX_REG_CTRL3<6>
Definition at line 102 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_BOOT_S
| #define L3GXXXX_INT1_BOOT_S (6) |
L3GXXXX_REG_CTRL3<6>
Definition at line 111 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_DURATION
| #define L3GXXXX_INT1_DURATION (0x3f) |
L3GXXXX_REG_IG_DURATION<6:0>
Definition at line 176 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_DURATION_S
| #define L3GXXXX_INT1_DURATION_S (0) |
L3GXXXX_REG_IG_DURATION<6:0>
Definition at line 179 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_IG
| #define L3GXXXX_INT1_IG (0x80) |
L3GXXXX_REG_CTRL3<7>
Definition at line 101 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_IG_S
| #define L3GXXXX_INT1_IG_S (7) |
L3GXXXX_REG_CTRL3<7>
Definition at line 110 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_LATCH
| #define L3GXXXX_INT1_LATCH (0x40) |
L3GXXXX_REG_IG_CFG<6>
Definition at line 156 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_LATCH_S
| #define L3GXXXX_INT1_LATCH_S (6) |
L3GXXXX_REG_IG_CFG<6>
Definition at line 165 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_WAIT
| #define L3GXXXX_INT1_WAIT (0x80) |
L3GXXXX_REG_IG_DURATION<7>
Definition at line 175 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_WAIT_S
| #define L3GXXXX_INT1_WAIT_S (7) |
L3GXXXX_REG_IG_DURATION<7>
Definition at line 178 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_X_HIGH
| #define L3GXXXX_INT1_X_HIGH (0x02) |
L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1>
Definition at line 161 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_X_HIGH_S
| #define L3GXXXX_INT1_X_HIGH_S (1) |
L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1>
Definition at line 170 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_X_LOW
| #define L3GXXXX_INT1_X_LOW (0x01) |
L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0>
Definition at line 162 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_X_LOW_S
| #define L3GXXXX_INT1_X_LOW_S (0) |
L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0>
Definition at line 171 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Y_HIGH
| #define L3GXXXX_INT1_Y_HIGH (0x08) |
L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3>
Definition at line 159 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Y_HIGH_S
| #define L3GXXXX_INT1_Y_HIGH_S (3) |
L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3>
Definition at line 168 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Y_LOW
| #define L3GXXXX_INT1_Y_LOW (0x04) |
L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2>
Definition at line 160 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Y_LOW_S
| #define L3GXXXX_INT1_Y_LOW_S (2) |
L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2>
Definition at line 169 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Z_HIGH
| #define L3GXXXX_INT1_Z_HIGH (0x20) |
L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5>
Definition at line 157 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Z_HIGH_S
| #define L3GXXXX_INT1_Z_HIGH_S (5) |
L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5>
Definition at line 166 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Z_LOW
| #define L3GXXXX_INT1_Z_LOW (0x10) |
L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4>
Definition at line 158 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT1_Z_LOW_S
| #define L3GXXXX_INT1_Z_LOW_S (4) |
L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4>
Definition at line 167 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_DRDY
| #define L3GXXXX_INT2_DRDY (0x08) |
L3GXXXX_REG_CTRL3<3>
Definition at line 105 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_DRDY_S
| #define L3GXXXX_INT2_DRDY_S (3) |
L3GXXXX_REG_CTRL3<3>
Definition at line 114 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_EMPTY
| #define L3GXXXX_INT2_EMPTY (0x01) |
L3GXXXX_REG_CTRL3<0>
Definition at line 108 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_EMPTY_S
| #define L3GXXXX_INT2_EMPTY_S (0) |
L3GXXXX_REG_CTRL3<0>
Definition at line 117 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_ORUN
| #define L3GXXXX_INT2_ORUN (0x02) |
L3GXXXX_REG_CTRL3<1>
Definition at line 107 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_ORUN_S
| #define L3GXXXX_INT2_ORUN_S (1) |
L3GXXXX_REG_CTRL3<1>
Definition at line 116 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_WTM
| #define L3GXXXX_INT2_WTM (0x04) |
L3GXXXX_REG_CTRL3<2>
Definition at line 106 of file l3gxxxx_regs.h.
◆ L3GXXXX_INT2_WTM_S
| #define L3GXXXX_INT2_WTM_S (2) |
L3GXXXX_REG_CTRL3<2>
Definition at line 115 of file l3gxxxx_regs.h.
◆ L3GXXXX_LOW_ODR
| #define L3GXXXX_LOW_ODR (0x01) |
L3GXXXX_REG_LOW_ODR<0>
Definition at line 183 of file l3gxxxx_regs.h.
◆ L3GXXXX_LOW_ODR_S
| #define L3GXXXX_LOW_ODR_S (0) |
L3GXXXX_REG_LOW_ODR<0>
Definition at line 187 of file l3gxxxx_regs.h.
◆ L3GXXXX_LVL_EN
| #define L3GXXXX_LVL_EN (0x40) |
L3GXXXX_REG_CTRL2<6>
Definition at line 93 of file l3gxxxx_regs.h.
◆ L3GXXXX_LVL_EN_S
| #define L3GXXXX_LVL_EN_S (6) |
L3GXXXX_REG_CTRL2<6>
Definition at line 98 of file l3gxxxx_regs.h.
◆ L3GXXXX_ODR
| #define L3GXXXX_ODR (0xc0) |
L3GXXXX_REG_CTRL1<7:6>
Definition at line 74 of file l3gxxxx_regs.h.
◆ L3GXXXX_ODR_BW
| #define L3GXXXX_ODR_BW (0xf0) |
L3GXXXX_REG_CTRL1<7:4>
Definition at line 76 of file l3gxxxx_regs.h.
◆ L3GXXXX_ODR_BW_S
| #define L3GXXXX_ODR_BW_S (4) |
L3GXXXX_REG_CTRL1<7:4>
Definition at line 85 of file l3gxxxx_regs.h.
◆ L3GXXXX_ODR_S
| #define L3GXXXX_ODR_S (6) |
L3GXXXX_REG_CTRL1<7:6>
Definition at line 83 of file l3gxxxx_regs.h.
◆ L3GXXXX_OUT_SEL
| #define L3GXXXX_OUT_SEL (0x03) |
L3GXXXX_REG_CTRL5<1:0>
Definition at line 130 of file l3gxxxx_regs.h.
◆ L3GXXXX_OUT_SEL_S
| #define L3GXXXX_OUT_SEL_S (0) |
L3GXXXX_REG_CTRL5<1:0>
Definition at line 137 of file l3gxxxx_regs.h.
◆ L3GXXXX_POWER_MODE
| #define L3GXXXX_POWER_MODE (0x08) |
L3GXXXX_REG_CTRL1<3>
Definition at line 77 of file l3gxxxx_regs.h.
◆ L3GXXXX_POWER_MODE_S
| #define L3GXXXX_POWER_MODE_S (3) |
L3GXXXX_REG_CTRL1<3>
Definition at line 86 of file l3gxxxx_regs.h.
◆ L3GXXXX_PP_OD
| #define L3GXXXX_PP_OD (0x10) |
L3GXXXX_REG_CTRL3<4>
Definition at line 104 of file l3gxxxx_regs.h.
◆ L3GXXXX_PP_OD_S
| #define L3GXXXX_PP_OD_S (4) |
L3GXXXX_REG_CTRL3<4>
Definition at line 113 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_CTRL1
| #define L3GXXXX_REG_CTRL1 (0x20) |
Register address CTRL1.
Definition at line 30 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_CTRL2
| #define L3GXXXX_REG_CTRL2 (0x21) |
Register address CTRL2.
Definition at line 31 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_CTRL3
| #define L3GXXXX_REG_CTRL3 (0x22) |
Register address CTRL3.
Definition at line 32 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_CTRL4
| #define L3GXXXX_REG_CTRL4 (0x23) |
Register address CTRL4.
Definition at line 33 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_CTRL5
| #define L3GXXXX_REG_CTRL5 (0x24) |
Register address CTRL5.
Definition at line 34 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_FIFO_CTRL
| #define L3GXXXX_REG_FIFO_CTRL (0x2e) |
Register address FIFO_CTRL.
Definition at line 44 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_FIFO_SRC
| #define L3GXXXX_REG_FIFO_SRC (0x2f) |
Register address FIFO_SRC.
Definition at line 45 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_CFG
| #define L3GXXXX_REG_IG_CFG (0x30) |
Register address IG_CFG.
Definition at line 46 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_DURATION
| #define L3GXXXX_REG_IG_DURATION (0x38) |
Register address IG_DURATION.
Definition at line 54 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_SRC
| #define L3GXXXX_REG_IG_SRC (0x31) |
Register address IG_SRC.
Definition at line 47 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_XH
| #define L3GXXXX_REG_IG_THS_XH (0x32) |
Register address IG_THS_XH.
Definition at line 48 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_XL
| #define L3GXXXX_REG_IG_THS_XL (0x33) |
Register address IG_THS_XL.
Definition at line 49 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_YH
| #define L3GXXXX_REG_IG_THS_YH (0x34) |
Register address IG_THS_YH.
Definition at line 50 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_YL
| #define L3GXXXX_REG_IG_THS_YL (0x35) |
Register address IG_THS_YL.
Definition at line 51 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_ZH
| #define L3GXXXX_REG_IG_THS_ZH (0x36) |
Register address IG_THS_ZH.
Definition at line 52 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_IG_THS_ZL
| #define L3GXXXX_REG_IG_THS_ZL (0x37) |
Register address IG_THS_ZL.
Definition at line 53 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_LOW_ODR
| #define L3GXXXX_REG_LOW_ODR (0x39) |
Register address LOW_ODR.
Definition at line 55 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_TEMP
| #define L3GXXXX_REG_OUT_TEMP (0x26) |
Register address OUT_TEMP.
Definition at line 36 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_X_H
| #define L3GXXXX_REG_OUT_X_H (0x29) |
Register address OUT_X_H.
Definition at line 39 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_X_L
| #define L3GXXXX_REG_OUT_X_L (0x28) |
Register address OUT_X_L.
Definition at line 38 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_Y_H
| #define L3GXXXX_REG_OUT_Y_H (0x2b) |
Register address OUT_Y_H.
Definition at line 41 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_Y_L
| #define L3GXXXX_REG_OUT_Y_L (0x2a) |
Register address OUT_Y_L.
Definition at line 40 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_Z_H
| #define L3GXXXX_REG_OUT_Z_H (0x2d) |
Register address OUT_Z_H.
Definition at line 43 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_OUT_Z_L
| #define L3GXXXX_REG_OUT_Z_L (0x2c) |
Register address OUT_Z_L.
Definition at line 42 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_REFERENCE
| #define L3GXXXX_REG_REFERENCE (0x25) |
Register address REFERENCE.
Definition at line 35 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_STATUS
| #define L3GXXXX_REG_STATUS (0x27) |
Register address STATUS.
Definition at line 37 of file l3gxxxx_regs.h.
◆ L3GXXXX_REG_WHO_AM_I
| #define L3GXXXX_REG_WHO_AM_I (0x0f) |
Register address WHO_AM_I.
Definition at line 29 of file l3gxxxx_regs.h.
◆ L3GXXXX_STOP_ON_WTM
| #define L3GXXXX_STOP_ON_WTM (0x20) |
L3GXXXX_REG_CTRL5<5>
Definition at line 127 of file l3gxxxx_regs.h.
◆ L3GXXXX_STOP_ON_WTM_S
| #define L3GXXXX_STOP_ON_WTM_S (5) |
L3GXXXX_REG_CTRL5<5>
Definition at line 134 of file l3gxxxx_regs.h.
◆ L3GXXXX_SW_RESET
| #define L3GXXXX_SW_RESET (0x04) |
L3GXXXX_REG_LOW_ODR<2>
Definition at line 182 of file l3gxxxx_regs.h.
◆ L3GXXXX_SW_RESET_S
| #define L3GXXXX_SW_RESET_S (2) |
L3GXXXX_REG_LOW_ODR<2>
Definition at line 186 of file l3gxxxx_regs.h.
◆ L3GXXXX_X_ENABLED
| #define L3GXXXX_X_ENABLED (0x01) |
L3GXXXX_REG_CTRL1<0>
Definition at line 80 of file l3gxxxx_regs.h.
◆ L3GXXXX_X_ENABLED_S
| #define L3GXXXX_X_ENABLED_S (1) |
L3GXXXX_REG_CTRL1<0>
Definition at line 89 of file l3gxxxx_regs.h.
◆ L3GXXXX_XDA
| #define L3GXXXX_XDA (0x01) |
L3GXXXX_REG_STATUS<0>
Definition at line 69 of file l3gxxxx_regs.h.
◆ L3GXXXX_XOR
| #define L3GXXXX_XOR (0x10) |
L3GXXXX_REG_STATUS<4>
Definition at line 65 of file l3gxxxx_regs.h.
◆ L3GXXXX_XYZ_ENABLED
| #define L3GXXXX_XYZ_ENABLED (0x07) |
L3GXXXX_REG_CTRL1<2:0>
Definition at line 81 of file l3gxxxx_regs.h.
◆ L3GXXXX_XYZ_ENABLED_S
| #define L3GXXXX_XYZ_ENABLED_S (0) |
L3GXXXX_REG_CTRL1<2:0>
Definition at line 90 of file l3gxxxx_regs.h.
◆ L3GXXXX_Y_ENABLED
| #define L3GXXXX_Y_ENABLED (0x02) |
L3GXXXX_REG_CTRL1<1>
Definition at line 79 of file l3gxxxx_regs.h.
◆ L3GXXXX_Y_ENABLED_S
| #define L3GXXXX_Y_ENABLED_S (1) |
L3GXXXX_REG_CTRL1<1>
Definition at line 88 of file l3gxxxx_regs.h.
◆ L3GXXXX_YDA
| #define L3GXXXX_YDA (0x02) |
L3GXXXX_REG_STATUS<1>
Definition at line 68 of file l3gxxxx_regs.h.
◆ L3GXXXX_YOR
| #define L3GXXXX_YOR (0x20) |
L3GXXXX_REG_STATUS<5>
Definition at line 64 of file l3gxxxx_regs.h.
◆ L3GXXXX_Z_ENABLED
| #define L3GXXXX_Z_ENABLED (0x04) |
L3GXXXX_REG_CTRL1<2>
Definition at line 78 of file l3gxxxx_regs.h.
◆ L3GXXXX_Z_ENABLED_S
| #define L3GXXXX_Z_ENABLED_S (2) |
L3GXXXX_REG_CTRL1<2>
Definition at line 87 of file l3gxxxx_regs.h.
◆ L3GXXXX_ZDA
| #define L3GXXXX_ZDA (0x04) |
L3GXXXX_REG_STATUS<2>
Definition at line 67 of file l3gxxxx_regs.h.
◆ L3GXXXX_ZOR
| #define L3GXXXX_ZOR (0x40) |
L3GXXXX_REG_STATUS<6>
Definition at line 63 of file l3gxxxx_regs.h.
◆ L3GXXXX_ZYXDA
| #define L3GXXXX_ZYXDA (0x08) |
L3GXXXX_REG_STATUS<3>
Definition at line 66 of file l3gxxxx_regs.h.
◆ L3GXXXX_ZYXOR
| #define L3GXXXX_ZYXOR (0x80) |
L3GXXXX_REG_STATUS<7>
Definition at line 62 of file l3gxxxx_regs.h.
