Loading...
Searching...
No Matches
periph_cpu.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef F2XX_G2XX_PERIPH_CPU_H
20#define F2XX_G2XX_PERIPH_CPU_H
21
22#include <stdbool.h>
23
24#include "periph_cpu_common.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
34#define HAVE_SPI_MODE_T
43typedef enum {
44 SPI_MODE_0 = (UCCKPH),
46 SPI_MODE_2 = (UCCKPL | UCCKPH),
47 SPI_MODE_3 = (UCCKPL)
55#define HAVE_SPI_CLK_T
59typedef enum {
60 SPI_CLK_100KHZ = 100000,
61 SPI_CLK_400KHZ = 400000,
62 SPI_CLK_1MHZ = 1000000,
63 SPI_CLK_5MHZ = 5000000,
65} spi_clk_t;
72#define PERIPH_SPI_NEEDS_INIT_CS
73#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
74#define PERIPH_SPI_NEEDS_TRANSFER_REG
75#define PERIPH_SPI_NEEDS_TRANSFER_REGS
83typedef enum {
84#ifdef __MSP430_HAS_USCI_AB0__
85 MSP430_USCI_ID_A0,
86 MSP430_USCI_ID_B0,
87#endif
88#ifdef __MSP430_HAS_USCI_AB1__
89 MSP430_USCI_ID_A1,
90 MSP430_USCI_ID_B1,
91#endif
94
109
118
122typedef struct {
124 uint8_t br0;
125 uint8_t br1;
126 uint8_t mctl;
128
139
154
158typedef struct {
161
178
182typedef struct {
184} spi_conf_t;
185
190
195
214 const msp430_usci_conf_t *conf);
215
222
236
241
246
251
256
261
266
267#ifdef __cplusplus
268}
269#endif
270
271#endif /* F2XX_G2XX_PERIPH_CPU_H */
#define REG8
Register types.
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
#define UCSSEL_ACLK
Clock USCI using auxiliary clock.
#define UCSSEL_SMCLK
Clock USCI using sub-system master clock.
#define UCSSEL_UCLKI
Clock USCI using CLKI (n/a in SPI mode)
msp430_port_p7_p8_t PORT_8
Register map of GPIO PORT 8.
const msp430_usci_spi_params_t usci_b1_as_spi
MSP430 F2xx/G2xx USCI B1 in SPI configuration.
void msp430_usci_acquire(const msp430_usci_params_t *params, const msp430_usci_conf_t *conf)
Acquire and initialize USCI for use a SPI/UART peripheral.
void msp430_usci_release(const msp430_usci_params_t *params)
Release an USCI, so that it can be used to provide other peripherals.
const msp430_usci_spi_params_t usci_a1_as_spi
MSP430 F2xx/G2xx USCI A1 in SPI configuration.
msp430_port_p7_p8_t PORT_7
Register map of GPIO PORT 7.
const msp430_usci_spi_params_t usci_b0_as_spi
MSP430 F2xx/G2xx USCI B0 in SPI configuration.
const msp430_usci_uart_params_t usci_a1_as_uart
MSP430 F2xx/G2xx USCI A1 in UART configuration.
msp430_usci_clk_t
MSP430 F2xx/G2xx USCI clock source.
Definition periph_cpu.h:113
@ USCI_CLK_SUBMAIN
sub-system master clock source
Definition periph_cpu.h:116
@ USCI_CLK_AUX
auxiliary clock source
Definition periph_cpu.h:115
@ USCI_CLK_UCLKI
UCLKI clock source (not supported yet)
Definition periph_cpu.h:114
const msp430_usci_spi_params_t usci_a0_as_spi
MSP430 F2xx/G2xx USCI A0 in SPI configuration.
const msp430_usci_uart_params_t usci_a0_as_uart
MSP430 F2xx/G2xx USCI A0 in UART configuration.
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
msp430_usci_prescaler_t msp430_usci_prescale(uint32_t target_hz)
Calculate prescaler settings for the given target frequency.
msp430_usci_id_t
Identifiers for USCI instances.
Definition periph_cpu.h:83
@ MSP430_USCI_ID_NUMOF
Number of USCI IDs (also: number of USCI instances)
Definition periph_cpu.h:92
GPIO Port 7/8 (different register layout than Ports 1-6)
Definition msp430_regs.h:75
Universal Serial Control Interface Type B (USCI_B) Registers.
MSP430 F2xx/G2xx USCI configuration registers.
Definition periph_cpu.h:135
uint8_t ctl0
USCI control register 0.
Definition periph_cpu.h:137
msp430_usci_prescaler_t prescaler
Prescaler configuration.
Definition periph_cpu.h:136
MSP430 F2xx/G2xx USCI configuration.
Definition periph_cpu.h:100
REG8 * interrupt_enable
The interrupt enable register matching the USCI.
Definition periph_cpu.h:103
msp430_usci_b_t * dev
The USCI device to use.
Definition periph_cpu.h:101
REG8 * interrupt_flag
The interrupt flag register matching the USCI.
Definition periph_cpu.h:104
uint8_t rx_irq_mask
The bitmask to enable the TX IRQ for this USCI.
Definition periph_cpu.h:106
msp430_usci_id_t id
ID of the USCI.
Definition periph_cpu.h:107
uint8_t tx_irq_mask
The bitmask to enable the TX IRQ for this USCI.
Definition periph_cpu.h:105
MSP430 F2xx/G2xx USCI prescaler configuration.
Definition periph_cpu.h:122
uint8_t br0
What to write in the BR0 register.
Definition periph_cpu.h:124
msp430_usci_clk_t clk_source
Clock source to use.
Definition periph_cpu.h:123
uint8_t br1
What to write in the BR1 register.
Definition periph_cpu.h:125
uint8_t mctl
USCI modulation control register.
Definition periph_cpu.h:126
MSP430 F2xx/G2xx SPI configuration, CPU level.
Definition periph_cpu.h:172
gpio_t mosi
COPI (MOSI) pin.
Definition periph_cpu.h:175
gpio_t miso
CIPO (MISO) pin.
Definition periph_cpu.h:174
msp430_usci_params_t usci_params
The USCI parameters.
Definition periph_cpu.h:173
MSP430 F2xx/G2xx UART configuration, CPU level.
Definition periph_cpu.h:149
msp430_usci_params_t usci_params
The USCI params.
Definition periph_cpu.h:150
SPI device configuration.
Definition periph_cpu.h:337
const msp430_usci_spi_params_t * spi
The SPI configuration to use.
Definition periph_cpu.h:183
UART device configuration.
Definition periph_cpu.h:218
const msp430_usci_uart_params_t * uart
The UART configuration to use.
Definition periph_cpu.h:159