23#ifndef F2XX_G2XX_MSP430_REGS_H
24#define F2XX_G2XX_MSP430_REGS_H
44#define MSP430_USCI_A_B_OFFSET 3U
57#define MSP430_USCI_B_FROM_USCI_A(usci_a) \
58 ((msp430_usci_b_t *)((uintptr_t)(usci_a) + MSP430_USCI_A_B_OFFSET))
124#define UCSSEL_UCLKI UCSSEL_0
125#define UCSSEL_ACLK UCSSEL_1
126#define UCSSEL_SMCLK UCSSEL_2
128#if (UCSSEL0 == 0x40) || DOXYGEN
131# error "USSEL field in USCI CTL1 register is at unexpected position"
143#define UCBRS_MASK UCBRS_7
145#if (UCBRS_7 == 0x0E) || defined(DOXYGEN)
151# error "UCBRS field in the UCAxMCTL register at unexpected position."
172 uintptr_t usci_b = (uintptr_t)usci_a + offsetof(
msp430_usci_a_t, CTL0);
#define REG8
Register types.
msp430_usci_a_t USCI_A0
USCI_A0 register map.
msp430_usci_b_t USCI_B1
USCI_B1 register map.
msp430_usci_b_t USCI_B0
USCI_B0 register map.
static msp430_usci_b_t * msp430_usci_b_from_usci_a(msp430_usci_a_t *usci_a)
"Convert" a USCI A into an USCI B interface
msp430_usci_a_t USCI_A1
USCI_A1 register map.
Cortex CMSIS style definition of MSP430 registers.
GPIO Port 1/2 (with interrupt functionality)
REG8 SEL
alternative function select
REG8 IES
interrupt edge select
REG8 REN
pull resistor enable
msp430_port_t base
common GPIO port registers
GPIO Port 7/8 (different register layout than Ports 1-6)
uint8_t _padding1
unrelated I/O
uint8_t _padding3
unrelated I/O
REG8 SEL
alternative function select
uint8_t _padding2
unrelated I/O
Common MSP GPIO Port Registers.
Universal Serial Control Interface Type A (USCI_A) Registers.
REG8 MCTL
modulation control
REG8 IRTCTL
IrDA transmit control.
REG8 TXBUF
transmit buffer
REG8 ABCTL
auto baud rate control
REG8 BR1
baud rate control 1
REG8 BR0
baud rate control 0
REG8 IRRCTL
IrDA receive control.
Universal Serial Control Interface Type B (USCI_B) Registers.
REG8 BR1
baud rate control 1
REG8 BR0
baud rate control 0
REG8 TXBUF
transmit buffer
REG8 MCTL
modulation control