Loading...
Searching...
No Matches
cpu_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2023 Mesotic SAS
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
20
21#ifdef CPU_MODEL_NRF5340_APP
22#include "vendor/nrf5340_application.h"
23#include "vendor/nrf5340_application_bitfields.h"
24#include "vendor/nrf5340_application_peripherals.h"
25#elif defined(CPU_MODEL_NRF5340_NET)
26#include "vendor/nrf5340_network.h"
27#include "vendor/nrf5340_network_bitfields.h"
28#include "vendor/nrf5340_network_peripherals.h"
29#else
30#error "The CPU_MODEL of your board is currently not supported"
31#endif
32
33#include "cpu_conf_common.h"
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
43#define CPU_DEFAULT_IRQ_PRIO (1U)
44
45#ifdef CPU_MODEL_NRF5340_APP
46#define CPU_FLASH_BASE (0x00000000)
47#define CPU_IRQ_NUMOF (69U)
48#endif /* def CPU_MODEL_NRF5340_APP */
50
55#define FLASHPAGE_SIZE (4096U)
56#define FLASHPAGE_NUMOF (256U)
57
58/* The minimum block size which can be written is 4B. However, the erase
59 * block is always FLASHPAGE_SIZE.
60 */
61#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
62/* Writing should be always 4 bytes aligned */
63#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
65
66#ifdef __cplusplus
67}
68#endif
69