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cpu_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2023 Mesotic SAS
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#ifdef CPU_MODEL_NRF5340_APP
20#include "vendor/nrf5340_application.h"
21#include "vendor/nrf5340_application_bitfields.h"
22#include "vendor/nrf5340_application_peripherals.h"
23#elif defined(CPU_MODEL_NRF5340_NET)
24#include "vendor/nrf5340_network.h"
25#include "vendor/nrf5340_network_bitfields.h"
26#include "vendor/nrf5340_network_peripherals.h"
27#else
28#error "The CPU_MODEL of your board is currently not supported"
29#endif
30
31#include "cpu_conf_common.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
41#define CPU_DEFAULT_IRQ_PRIO (1U)
42
43#ifdef CPU_MODEL_NRF5340_APP
44#define CPU_FLASH_BASE (0x00000000)
45#define CPU_IRQ_NUMOF (69U)
46#endif /* def CPU_MODEL_NRF5340_APP */
48
53#define FLASHPAGE_SIZE (4096U)
54#define FLASHPAGE_NUMOF (256U)
55
56/* The minimum block size which can be written is 4B. However, the erase
57 * block is always FLASHPAGE_SIZE.
58 */
59#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
60/* Writing should be always 4 bytes aligned */
61#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
63
64#ifdef __cplusplus
65}
66#endif
67