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pll3.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2025 Technische Universität Hamburg
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "cfg_clock_default.h"
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/* PLL3 configuration (DEFAULT): the following parameters configure a 48MHz USB clock
25 * with HSE (8MHz/25MHz) or HSI (64MHz) or CSI (4MHz) as PLL input clock. */
26#ifndef CONFIG_CLOCK_PLL3_M
27# if IS_ACTIVE(CONFIG_USE_CSI_PLL)
28# define CONFIG_CLOCK_PLL3_M (1)
29# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
30# if CONFIG_CLOCK_HSE == MHZ(8)
31# define CONFIG_CLOCK_PLL3_M (4)
32# elif CONFIG_CLOCK_HSE == MHZ(25)
33# define CONFIG_CLOCK_PLL3_M (5)
34# endif
35# else /* HSI - 64MHz */
36# define CONFIG_CLOCK_PLL3_M (8)
37# endif
38#endif
39
40#ifndef CONFIG_CLOCK_PLL3_N
41# if IS_ACTIVE(CONFIG_USE_CSI_PLL)
42# define CONFIG_CLOCK_PLL3_N (240)
43# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
44# if CONFIG_CLOCK_HSE == MHZ(8)
45# define CONFIG_CLOCK_PLL3_N (480)
46# elif CONFIG_CLOCK_HSE == MHZ(25)
47# define CONFIG_CLOCK_PLL3_N (192)
48# endif
49# else /* HSI */
50# define CONFIG_CLOCK_PLL3_N (120)
51# endif
52#endif
53
54#ifndef CONFIG_CLOCK_PLL3_P
55# if IS_ACTIVE(CONFIG_USE_CSI_PLL)
56# define CONFIG_CLOCK_PLL3_P (2)
57# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
58# if CONFIG_CLOCK_HSE == MHZ(8)
59# define CONFIG_CLOCK_PLL3_P (2)
60# elif CONFIG_CLOCK_HSE == MHZ(25)
61# define CONFIG_CLOCK_PLL3_P (2)
62# endif
63# else /* HSI */
64# define CONFIG_CLOCK_PLL3_P (2) /* 480 MHz with HSI */
65# endif
66#endif
67
68#ifndef CONFIG_CLOCK_PLL3_Q
69# if IS_ACTIVE(CONFIG_USE_CSI_PLL)
70# define CONFIG_CLOCK_PLL3_Q (20)
71# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
72# if CONFIG_CLOCK_HSE == MHZ(8)
73# define CONFIG_CLOCK_PLL3_Q (20)
74# elif CONFIG_CLOCK_HSE == MHZ(25)
75# define CONFIG_CLOCK_PLL3_Q (20)
76# endif
77# else /* HSI */
78# define CONFIG_CLOCK_PLL3_Q (20) /* Alternative 48MHz clock (USB/SDIO/SDMMC) */
79# endif
80#endif
81
82#ifndef CONFIG_CLOCK_PLL3_R
83# if IS_ACTIVE(CONFIG_USE_CSI_PLL)
84# define CONFIG_CLOCK_PLL3_R (2)
85# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
86# if CONFIG_CLOCK_HSE == MHZ(8)
87# define CONFIG_CLOCK_PLL3_R (2)
88# elif CONFIG_CLOCK_HSE == MHZ(25)
89# define CONFIG_CLOCK_PLL3_R (2)
90# endif
91# else /* HSI */
92# define CONFIG_CLOCK_PLL3_R (2) /* LTDC Clock, with HSI - 480MHz */
93# endif
94#endif
95
96/* PLL3 needed? */
97#if IS_ACTIVE(CONFIG_USE_HSI_PLL) || IS_ACTIVE(CONFIG_CLOCK_HSE_PLL) || \
98 IS_ACTIVE(CONFIG_USE_CSI_PLL)
99/* Configure these values using KCONFIG */
100# define CLOCK_PLL3_M CONFIG_CLOCK_PLL3_M
101# define CLOCK_PLL3_N CONFIG_CLOCK_PLL3_N
102# define CLOCK_PLL3_P CONFIG_CLOCK_PLL3_P
103# define CLOCK_PLL3_Q CONFIG_CLOCK_PLL3_Q
104# define CLOCK_PLL3_R CONFIG_CLOCK_PLL3_R
105
106/* PLL3 input selection */
107# if IS_ACTIVE(CONFIG_USE_HSI_PLL)
108# define CLOCK_PLL3_INPUT CLOCK_HSI
109# elif IS_ACTIVE(CONFIG_USE_HSE_PLL)
110# define CLOCK_PLL3_INPUT CLOCK_HSE
111# elif IS_ACTIVE(CONFIG_USE_CSI_PLL)
112# define CLOCK_PLL3_INPUT CLOCK_CSI
113# endif
114
115/* PLL3 output frequencies */
116# define CLOCK_PLL3_VCO ((CLOCK_PLL3_INPUT * CLOCK_PLL3_N) / (CLOCK_PLL3_M))
117# define CLOCK_PLL3_P_OUT (CLOCK_PLL3_VCO / CLOCK_PLL3_P)
118# define CLOCK_PLL3_Q_OUT (CLOCK_PLL3_VCO / CLOCK_PLL3_Q)
119# define CLOCK_PLL3_R_OUT (CLOCK_PLL3_VCO / CLOCK_PLL3_R)
120#endif /* PLL usage */
121
122#ifdef __cplusplus
123}
124#endif
125
cfg_clock_default.h
Main header for STM32H7 clock configuration (STM32H753ZI)