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qma6100p_regs.h
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1/*
2 * SPDX-FileCopyrightText: 2026 Baptiste Le Duc <baptiste.leduc@etik.com>
3 * SPDX-FileCopyrightText: 2026 Léandre Le Duc <leandre.leduc38@gmail.com>
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
28
33#define QMA6100P_REG_CHIP_ID (0x00)
35
46#define QMA6100P_REG_DX_LSB (0x01)
47#define QMA6100P_REG_DX_MSB (0x02)
48#define QMA6100P_REG_DY_LSB (0x03)
49#define QMA6100P_REG_DY_MSB (0x04)
50#define QMA6100P_REG_DZ_LSB (0x05)
51#define QMA6100P_REG_DZ_MSB (0x06)
53
58#define QMA6100P_REG_RANGE (0x0F)
59#define QMA6100P_REG_ODR (0x10)
60#define QMA6100P_REG_PM (0x11)
61#define QMA6100P_REG_SW_RESET (0x36)
62#define QMA6100P_REG_NVM (0x33)
63#define QMA6100P_REG_CHIP_STATE (0x45)
64#define QMA6100P_REG_ULPS (0x46)
65#define QMA6100P_REG_TST0_ANA (0x4A)
66#define QMA6100P_REG_AFE_ANA (0x56)
67#define QMA6100P_REG_TST1_ANA (0x5F)
69
74#define QMA6100P_REG_INT_ST2 (0x0B)
75#define QMA6100P_REG_INT_EN1 (0x17)
76#define QMA6100P_REG_INT1_MAP1 (0x1A)
77#define QMA6100P_REG_INT2_MAP1 (0x1C)
78#define QMA6100P_REG_INTPIN_CONF (0x20)
79#define QMA6100P_REG_INT_CFG (0x21)
82
89#define QMA6100P_CHIP_ID_MASK (0xF0)
91#define QMA6100P_CHIP_ID_VAL (0x90)
93
98#define QMA6100P_NEWDATA_FLAG_MASK (1 << 0)
100
105#define QMA6100P_INT_ST2_DATA_INT_MASK (1 << 4)
107
113#define QMA6100P_RANGE_MASK (0b00001111)
115#define QMA6100P_RANGE_LPF_HPF_MASK (1 << 6)
117
122#define QMA6100P_2G_RESOLUTION (244)
123#define QMA6100P_4G_RESOLUTION (488)
124#define QMA6100P_8G_RESOLUTION (977)
125#define QMA6100P_16G_RESOLUTION (1950)
126#define QMA6100P_32G_RESOLUTION (3810)
128
139#define QMA6100P_ODR_MASK (0b00011111)
140#define QMA6100P_NLPF_MASK (0b11100000)
142
147#define QMA6100P_PM_MODE_MASK (1 << 7)
148#define QMA6100P_PM_MCLK_MASK (0b00001111)
150
155#define QMA6100P_INT_EN1_DATA_MASK (1 << 4)
157
162#define QMA6100P_INT_MAP1_DATA_MASK (1 << 4)
164
171#define QMA6100P_INTPIN_INT1_LVL_MASK (1 << 0)
173#define QMA6100P_INTPIN_INT1_OD_MASK (1 << 1)
175#define QMA6100P_INTPIN_INT2_LVL_MASK (1 << 2)
177#define QMA6100P_INTPIN_INT2_OD_MASK (1 << 3)
179
185#define QMA6100P_INT_CFG_SHADOW_MASK (1 << 6)
187
192#define QMA6100P_INT_CFG_SHADOW_EN (0)
193#define QMA6100P_INT_CFG_SHADOW_DIS (1)
195
202#define QMA6100P_NVM_LOAD_DONE (1 << 0)
204#define QMA6100P_NVM_RDY (1 << 2)
206
211#define QMA6100P_SW_RESET_VAL (0xB6)
213
218#define QMA6100P_ANA_TST1_TMODE (1 << 7)
220
221#ifdef __cplusplus
222}
223#endif
224